Micromachining Silicon Structures on Thin Membranes Us Zhong Ren , Mark E McNie, Colin C Welch, Mike C Oxford Instruments Plasma Technology, Yatton, BS49 4AP, U e-mail: [email protected] Keywords: inductively coupled plasma (ICP) etch; silicon membrane; cantil electro-mechanical systems (MEMS); deep silicon etch (DSiE) Micromachining detailed silicon structures on thin membranes is regarded a fabrication techniques, but also one of the more difficult processes. There chemical loading effect, as the silicon clears from the membrane layer whi from etching structures on a membrane decreases significantly as the m exothermic etch reaction can even cause the resist pattern and etch pass associated heat is focused in a small area. There is a need for very high etch to expose the membrane, but also a need for very precise profile control in fa features. The bulk etch can use an anisotropic wet etch that is selective t planes, such as KOH or TMAH. The wet chemistry is only suitable for low results in a characteristic slope at a 54.74º for <100> silicon wafers that l packing density [1]. A Bosch (or gas-chopping) deep silicon etching (DS deposition and etch steps can realize a vertical profile at high aspect-ratio 30μm/min, and can etch arbitrary shapes as defined by the mask pattern [2, 3] This paper reports a technique which addresses these problems, and gives ex structures, using a DSiE tool (Oxford Instruments PlasmaPro 100 Estrelas) in chemistry). Most DSiE process tools are optimised for high rate anisotropic e ability to perform precision, lower rate processes. Such fast switching significant minimum power to maintain the plasma during the transition be steps. This tool can operate successfully over more than an order of mag plasma (ICP) source power, from <500W to >5kW, opening the possibility o low rate processes in the same chamber. The minimum time of a single pr removing polymer which enables a full cycle of deposition, break through Results given here used cycle times up to 2.5 s. Whilst an electrostatic chuck wafer surface in contact and to conductive layers on the membrane, where clamping plane the gap is large and so heat removal efficiency via Helium bac reduced. Thus in order to be able to etch structures on membranes without profile control, a low power process capability is also required. Three devices have been realized using this combination of high ate and p resonator high-Q cavity with a vertical profile (90º) and uniform scallop s periodic deep grating with 50:1 high AR (Figures 3 and 4); and a large leng photoresist (PR) membrane where avoiding mask overheating and not underneath the cantilever was key (Figures 5 and 6). Moreover, high quali also achieved on these etched structures. [1] H. Seidel, L. Csepregi, A. Heuberger, H. Baumgartel, J. Electrochem. Soc [2] F. Laermer, A. Schilp, German Patent DE-4241045, 1994 [3] Z.Ren, M.E.McNie, Microelec. Eng. 141 (2015) 261-266 The authors would like to thank Dr. S Vollmeke (CiS Forschungsinstitut fur for providing cantilever samples for etching at Oxford Instruments and permis sing Plasma Etching Cooke United Kingdom lever; Bosch process; micro- as one of the primary MEMS e is a very sharp transition in ilst the lateral heat dissipation membrane is approached. The sivation to degrade when the h rates to remove bulk material abricating micro- or nano-scale to the <111> crystallographic aspect ratio (AR) features and limits geometric freedom and SiE) process with alternating (AR) with etch rates of up to ] with high packing density. xample results on three typical n the Bosch process (SF6-C4F8 etch but may be limited in their etch processes often need a etween etching and deposition gnitude of inductively coupled of both high rate and precision, rocess step is 100-300 ms for and etch to be as low as 1 s. k (ESC) clamps over the whole e membranes are proud of the ack side cooling is dramatically t overheating and maintaining precision processing: a micro- size (Figures 1 and 2); a fine gth-width ratio cantilever on a damaging the polymer film ity and smooth sidewalls were c. 137 (11) (1990) 3614–3626 r Mikrosensoik GmbH, Erfurt) ssion to use the SEM images. Figure 1. Schematic section of a micro-resonator on a Si3N4 membrane: back cavity by KOH etching and the top pattern defined in a 60μm thick silicon membrane using the Bosch process Figure 3. Schematic section of gratings in a SOI wafer: the back cavity defined by a high rate Bosch etch and fine period optical gratings realised in the device layer using a precision Bosch etch. Figure 5. Challenges on Si membrane etch: (a) grass and striations in corners; (b) optimized etch gives striation-free and smooth sidewall; (c) PR mask burnt out during Bosch etch; (d) optimized etch avoids overheating on PR mask. Figure 2. Micro-resonator structure: (a) side view with vertical profile and a 60μm etch depth; (b) sidewall roughness (scallop size) of 78nm Figure 4. High aspect-ratio (50:1) fine period (200nm) gratings etched by a Bosch process: (a) Etch depth 5μm; (b) minimal bow at top of trenches Figure 6. Si cantilever: (a) Illustration of cantilever fabrication in Si membrane by means wet-etching and Bosch process; (b) 5 mm length × 200 μm width × 50 μm thickness cantilever; (c) and (d) Enlarged view of the cantilever after polymer removal.