Microelectronics Lab ELCT706 IC Design Lab Session #1 IC ...

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Microelectronics Lab ELCT706

IC Design Lab Session #1

IC Layout

Dr. Eman Azab

Eng. Samar Shukry

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1.VLSI Circuit Design Flow

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2.CMOS Circuits Layout

- Layout Representation: output of physical design

step

- Physical Design: Translation of circuit schematics

into Silicon form

- Layout Design: Generating layout masks needed

for fabrication and the Silicon processing

- Layout Design Rules: Common language between

VLSI designers and process engineers, they reflect a

limit of a process describing minimum width,

minimum spacing, overlap obeying the Micron rules.

- Stick Diagram: Initial step needed for planning the

layout and routing of the circuit

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2.CMOS Circuits Layout

CMOS Composite Layout:

The integrated circuit layout is the representation of the integrated circuit in

terms of planar geometric shapes corresponding to metal,oxide or

semiconducting layers used for building up different components in the

integrated circuit.

Layout Layers:

1. OD active layer.

2. nplus “NP” layer.

3. pplus “PP” layer.

4. Poly.

5. Nwell.

6. Active contact.

7. Metal1.

8. Metal2.

9. Via.

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2.CMOS Circuits Layout

Layout Design Rules:

1. Active layer rules: a) Minimum width = 0.06.

b) Minimum spacing Active-Active = 0.14.

c) Minimum spacing Active-PP/NP = 0.02.

d) Minimum spacing Active N/P well = 0.17.

e) Minimum source/drain width = 0.23.

f) Minimum extension distance Active-Active contact

= 0.04.

g) Minimum overlap distance Active-Poly = 0.15.

2. Poly layer rules: a) Minimum width = 0.1.

b) Minimum spacing poly-poly = 0.14.

c) Minimum extension outside active = 0.16.

d) Minimum spacing poly-Active contact = 0.07.

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3. N/P wells, NP/PP, Metal 1 and Metal 2 layers:

Active contact exact square area = 0.12 * 0.12

*Minimum spacing for a layer of certain type refers to

minimum spacing between similar layers of that type.

i.e. minimum spacing of Metal1 layer = 0.12 means the

minimum spacing between any two metal1 layers is 0.12.

Note: all Design Rules are in microns by default.

Layer Minimum width Minimum spacing*

N/P well 0.62 0.62

NP/PP 0.24 0.24

Metal 1 0.12 0.12

Metal 2 0.14 0.14

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Example on drawing a layout of CMOS inverter:

Firstly, draw the schematic of the CMOS inverter circuit

using the cadence tool then:

Launch layout XL, the following window will pop up:

We choose to create a new layout using an automatic

configuration and then press OK.

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In this window, we choose the library in which we are

going to save our layout design which is the same library

in which the schematic is saved, choose a name for the

cell and choose its view to be layout which is called

calibre view. The following window is going to appear:

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This is the space where we are going to design our layout

using the different layers from the Layer Selection

Window (LSW) which is a window that contains all layers

we are going to need in building up the design where

there is a colour format that gives each layer a colour to

distinguish it from other layers.

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Now we are going to draw the CMOS inverter layout step

by step starting by drawing the layout of the NMOS

transistor layer by layer as follows:

1. The Active Diffusion Layer:

We are going to draw a rectangular active area using

the active layer “OD layer” from the LSW to define

the source and drain diffusion regions of the

transistor where the width of the rectangle is

defined by the width of the transistor specified in

the properties of the transistor in the schematic.

Create Shape Rectangle or press “R”, notice

that a shape of a rectangle will be attached to the

cursor.

Click once to select the first corner of the rectangle

and move the cursor to the opposite corner.

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To adjust the dimensions of the rectangle, we can use a

ruler, Tools Create ruler or press “k” and select the

two sides you want to measure the length between

them, we can also move each side of the rectangle

seperately to adjust the dimensions as required by

pressing the shortcut key “S” and select the side to be

moved and drag.

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2. The gate poly:

The second step is to draw the polysilicon gate of the

transistor, we will draw another rectangle using the

poly “PO” layer from the LSW to represent the channel

noting that the length of the transistor determines the

width of the poly rectangle.

Note that the poly rectangle is drawn in the middle of the

diffusion area.

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3. Active contacts:

These active contacts represent an access to the

drain and source regions of the transistor(holes in

the oxide layer) .They will be drawn as squares using

the “CO” layer from the LSW.

The other contact in the source/drain diffusion region

can be drawn like the first one or we can simply copy it.

Click on the contact to select it then press “C” and click

once again, you will notice that a ghost of the contact is

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attached to the cursor, move to the other diffusion area

where the contact should be drawn and click to be

located.

Alignment:

Note that: when you move to locate the copied contact,

it has to be aligned with the original one to fullfill the

same design rules applied concerning the spacings with

the diffusion and poly layers and to do so we can use the

Display options.

Options Display Snap mode Create and Edit:

Orthogonal, if we choose “any angle” we can move the

components in any direction but orthogonal will only

move in a perpendicular direction.

From the same window, we can adjust the increments in

which the cursor moves in x and y directions.

Options Display X snap spacing and y snap spacing,

these spacings are chosen to be very small so as to ease

moving and locating the components within tiny

increments if needed like in case of requiring a

dimension of 0.56 for eg. an increment of 0.1 will not

help but that of 0.05 for instance will do.

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4. Covering contacts with metal1: Active contacts define the connection terminals but

the real connection to the corresponding

source/drain diffusion region is made by metal1

layer. We draw a rectangular area of Metal1

covering the active contacts.

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5. The NP layer: We should use a layer to define the type of diffusion used

in the source and drain regions of the transistor and in

case of nmos, we use the NP layer that defines the source

and drain regions to be highly doped with donor atoms i.e.

n-type diffusion. We draw a rectangular layer of NP layer

surrounding the whole device from all directions, to be

extended over the poly and OD layers with extension

distances that obey the Design rules defined by the

factory.

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6. The Pwell: Draw a rectangle surrounding the transistor using

the PDKREC layer from the LSW to represent that the

nmos device is mounted on a p-type substrate.

Note that the pmos device layout can be built up

following the same steps, replacing the Pwell with

Nwell(using NW layer) and NP layer with PP layer.

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7. Bulk Connections: The bulk is the fourth terminal in the nmos or pmos devices, we

should create a bulk or substrate contact that is a n+ contact in

case of pmos, as it is a contact used to bias a n-type

substrate(Nwell) and it will be a p+ contact in case of nmos, since

the substrate used is p-type so we are going to create a diffusion

area of n and p types (using OD layer + NP or PP layer) and create

an access to it using an active contact in order to bias the

substrate of both devices properly.

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we are going to attach the bulk terminals to the

corresponding devices and extend the well of each

device to contain it with its four terminals.

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Routing Steps:

We now have the devices (nmos and pmos transistors)

ready to be connected in same configuration as given by

the schematic to build up our inverter layout design.

1. connect the bulk terminals of both nmos and pmos

devices to their source terminals respectively using

Metal1 layer.

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2. the drain of nmos is connected to that of pmos:

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3. gates are connected using a poly layer.

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4. create the power rails (Vdd and Gnd) using Metal1

layer:

The last step is to generate the pins of Vin, Vout,

Vdd,and Gnd.

Note: we should use a via to connect the Metal1

layer with the poly gate to conduct Vin signal.