Features • High Performance, Low Power AVR ® 8-Bit Microcontroller • Advanced RISC Architecture – 131 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 20 MIPS Throughput at 20 MHz – On-chip 2-cycle Multiplier • High Endurance Non-volatile Memory Segments – 4/8/16/32K Bytes of In-System Self-Programmable Flash progam memory (ATmega48PA/88PA/168PA/328P) – 256/512/512/1K Bytes EEPROM (ATmega48PA/88PA/168PA/328P) – 512/1K/1K/2K Bytes Internal SRAM (ATmega48PA/88PA/168PA/328P) – Write/Erase Cycles: 10,000 Flash/100,000 EEPROM – Data retention: 20 years at 85°C/100 years at 25°C (1) – Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation – Programming Lock for Software Security • Peripheral Features – Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode – Real Time Counter with Separate Oscillator – Six PWM Channels – 8-channel 10-bit ADC in TQFP and QFN/MLF package Temperature Measurement – 6-channel 10-bit ADC in PDIP Package Temperature Measurement – Programmable Serial USART – Master/Slave SPI Serial Interface – Byte-oriented 2-wire Serial Interface (Philips I 2 C compatible) – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator – Interrupt and Wake-up on Pin Change • Special Microcontroller Features – Power-on Reset and Programmable Brown-out Detection – Internal Calibrated Oscillator – External and Internal Interrupt Sources – Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended Standby • I/O and Packages – 23 Programmable I/O Lines – 28-pin PDIP, 32-lead TQFP, 28-pad QFN/MLF and 32-pad QFN/MLF • Operating Voltage: – 1.8 - 5.5V for ATmega48PA/88PA/168PA/328P • Temperature Range: – -40°C to 85°C • Speed Grade: – 0 - 20 MHz @ 1.8 - 5.5V • Low Power Consumption at 1 MHz, 1.8V, 25°C for ATmega48PA/88PA/168PA/328P: – Active Mode: 0.2 mA – Power-down Mode: 0.1 μA – Power-save Mode: 0.75 μA (Including 32 kHz RTC) 8-bit Microcontroller with 4/8/16/32K Bytes In-System Programmable Flash ATmega48PA ATmega88PA ATmega168PA ATmega328P Summary Rev. 8161CS–AVR–05/09
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8-bit Microcontroller with 4/8/16/32K Bytes In-SystemProgrammable Flash
ATmega48PAATmega88PAATmega168PAATmega328P
Summary
Rev. 8161CS–AVR–05/09
Features• High Performance, Low Power AVR® 8-Bit Microcontroller• Advanced RISC Architecture
– 131 Powerful Instructions – Most Single Clock Cycle Execution– 32 x 8 General Purpose Working Registers– Fully Static Operation– Up to 20 MIPS Throughput at 20 MHz– On-chip 2-cycle Multiplier
• High Endurance Non-volatile Memory Segments– 4/8/16/32K Bytes of In-System Self-Programmable Flash progam memory
(ATmega48PA/88PA/168PA/328P)– 256/512/512/1K Bytes EEPROM (ATmega48PA/88PA/168PA/328P)– 512/1K/1K/2K Bytes Internal SRAM (ATmega48PA/88PA/168PA/328P)– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM– Data retention: 20 years at 85°C/100 years at 25°C(1)
– Optional Boot Code Section with Independent Lock BitsIn-System Programming by On-chip Boot ProgramTrue Read-While-Write Operation
– Programming Lock for Software Security• Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
Mode– Real Time Counter with Separate Oscillator– Six PWM Channels– 8-channel 10-bit ADC in TQFP and QFN/MLF package
Temperature Measurement– 6-channel 10-bit ADC in PDIP Package
Temperature Measurement– Programmable Serial USART– Master/Slave SPI Serial Interface– Byte-oriented 2-wire Serial Interface (Philips I2C compatible)– Programmable Watchdog Timer with Separate On-chip Oscillator– On-chip Analog Comparator– Interrupt and Wake-up on Pin Change
• Special Microcontroller Features– Power-on Reset and Programmable Brown-out Detection– Internal Calibrated Oscillator– External and Internal Interrupt Sources– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby,
1.1.3 Port B (PB7:0) XTAL1/XTAL2/TOSC1/TOSC2Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). ThePort B output buffers have symmetrical drive characteristics with both high sink and sourcecapability. As inputs, Port B pins that are externally pulled low will source current if the pull-upresistors are activated. The Port B pins are tri-stated when a reset condition becomes active,even if the clock is not running.
Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscil-lator amplifier and input to the internal clock operating circuit.
Depending on the clock selection fuse settings, PB7 can be used as output from the invertingOscillator amplifier.
If the Internal Calibrated RC Oscillator is used as chip clock source, PB7..6 is used as TOSC2..1input for the Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set.
The various special features of Port B are elaborated in ”Alternate Functions of Port B” on page76 and ”System Clock and Clock Options” on page 26.
1.1.4 Port C (PC5:0)Port C is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). ThePC5..0 output buffers have symmetrical drive characteristics with both high sink and sourcecapability. As inputs, Port C pins that are externally pulled low will source current if the pull-upresistors are activated. The Port C pins are tri-stated when a reset condition becomes active,even if the clock is not running.
1.1.5 PC6/RESETIf the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical char-acteristics of PC6 differ from those of the other pins of Port C.
If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pinfor longer than the minimum pulse length will generate a Reset, even if the clock is not running.The minimum pulse length is given in Table 28-3 on page 308. Shorter pulses are not guaran-teed to generate a Reset.
The various special features of Port C are elaborated in ”Alternate Functions of Port C” on page79.
1.1.6 Port D (PD7:0)Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). ThePort D output buffers have symmetrical drive characteristics with both high sink and sourcecapability. As inputs, Port D pins that are externally pulled low will source current if the pull-upresistors are activated. The Port D pins are tri-stated when a reset condition becomes active,even if the clock is not running.
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The various special features of Port D are elaborated in ”Alternate Functions of Port D” on page82.
1.1.7 AVCC
AVCC is the supply voltage pin for the A/D Converter, PC3:0, and ADC7:6. It should be externallyconnected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC
through a low-pass filter. Note that PC6..4 use digital supply voltage, VCC.
1.1.8 AREFAREF is the analog reference pin for the A/D Converter.
1.1.9 ADC7:6 (TQFP and QFN/MLF Package Only)In the TQFP and QFN/MLF package, ADC7:6 serve as analog inputs to the A/D converter.These pins are powered from the analog supply and serve as 10-bit ADC channels.
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2. OverviewThe ATmega48PA/88PA/168PA/328P is a low-power CMOS 8-bit microcontroller based on theAVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, theATmega48PA/88PA/168PA/328P achieves throughputs approaching 1 MIPS per MHz allowingthe system designer to optimize power consumption versus processing speed.
2.1 Block Diagram
Figure 2-1. Block Diagram
The AVR core combines a rich instruction set with 32 general purpose working registers. All the32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independentregisters to be accessed in one single instruction executed in one clock cycle. The resulting
PORT C (7)PORT B (8)PORT D (8)
USART 0
8bit T/C 2
16bit T/C 18bit T/C 0 A/D Conv.
InternalBandgap
AnalogComp.
SPI TWI
SRAMFlash
EEPROM
WatchdogOscillator
WatchdogTimer
OscillatorCircuits /
ClockGeneration
PowerSupervisionPOR / BOD &
RESET
VC
C
GN
D
PROGRAMLOGIC
debugWIRE
2
GND
AREF
AVCC
DAT
AB
US
ADC[6..7]PC[0..6]PB[0..7]PD[0..7]
6
RESET
XTAL[1..2]
CPU
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architecture is more code efficient while achieving throughputs up to ten times faster than con-ventional CISC microcontrollers.
The ATmega48PA/88PA/168PA/328P provides the following features: 4/8/16/32K bytes of In-System Programmable Flash with Read-While-Write capabilities, 256/512/512/1K bytesEEPROM, 512/1K/1K/2K bytes SRAM, 23 general purpose I/O lines, 32 general purpose work-ing registers, three flexible Timer/Counters with compare modes, internal and externalinterrupts, a serial programmable USART, a byte-oriented 2-wire Serial Interface, an SPI serialport, a 6-channel 10-bit ADC (8 channels in TQFP and QFN/MLF packages), a programmableWatchdog Timer with internal Oscillator, and five software selectable power saving modes. TheIdle mode stops the CPU while allowing the SRAM, Timer/Counters, USART, 2-wire Serial Inter-face, SPI port, and interrupt system to continue functioning. The Power-down mode saves theregister contents but freezes the Oscillator, disabling all other chip functions until the next inter-rupt or hardware reset. In Power-save mode, the asynchronous timer continues to run, allowingthe user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduc-tion mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimizeswitching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator isrunning while the rest of the device is sleeping. This allows very fast start-up combined with lowpower consumption.
The device is manufactured using Atmel’s high density non-volatile memory technology. TheOn-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPIserial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot pro-gram running on the AVR core. The Boot program can use any interface to download theapplication program in the Application Flash memory. Software in the Boot Flash section willcontinue to run while the Application Flash section is updated, providing true Read-While-Writeoperation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on amonolithic chip, the Atmel ATmega48PA/88PA/168PA/328P is a powerful microcontroller thatprovides a highly flexible and cost effective solution to many embedded control applications.
The ATmega48PA/88PA/168PA/328P AVR is supported with a full suite of program and systemdevelopment tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators,In-Circuit Emulators, and Evaluation kits.
2.2 Comparison Between ATmega48PA, ATmega88PA, ATmega168PA and ATmega328PThe ATmega48PA, ATmega88PA, ATmega168PA and ATmega328P differ only in memorysizes, boot loader support, and interrupt vector sizes. Table 2-1 summarizes the different mem-ory and interrupt vector sizes for the three devices.
ATmega88PA, ATmega168PA and ATmega328P support a real Read-While-Write Self-Pro-gramming mechanism. There is a separate Boot Loader Section, and the SPM instruction canonly execute from there. In ATmega48PA, there is no Read-While-Write support and no sepa-rate Boot Loader Section. The SPM instruction can execute from the entire Flash.
3. Resources A comprehensive set of development tools, application notes and datasheets are available fordownload on http://www.atmel.com/avr.
Note: 1.
4. Data RetentionReliability Qualification results show that the projected data retention failure rate is much lessthan 1 PPM over 20 years at 85°C or 100 years at 25°C.
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5. Register SummaryAddress Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
0x1E (0x3E) GPIOR0 General Purpose I/O Register 0 25
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
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Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written.
2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega48PA/88PA/168PA/328P is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also Halide free and fully Green.
3. See ”Speed Grades” on page 306.4. NiPdAu Lead Finish.
Speed (MHz) Power Supply Ordering Code(2) Package(1) Operational Range
Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also Halide free and fully Green.
3. See ”Speed Grades” on page 306.4. NiPdAu Lead Finish.
Speed (MHz) Power Supply Ordering Code(2) Package(1) Operational Range
Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also Halide free and fully Green.
3. See ”Speed Grades” on page 312.4. NiPdAu Lead Finish.
Speed (MHz)(3) Power Supply Ordering Code(2) Package(1) Operational Range
Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also Halide free and fully Green.
3. See Figure 28-1 on page 316.
Speed (MHz) Power Supply Ordering Code(2) Package(1) Operational Range
Note: 1. Dimensions D and E1 do not include mold Flash or Protrusion.Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
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9. Errata
9.1 Errata ATmega48PAThe revision letter in this section refers to the revision of the ATmega48PA device.
9.1.1 Rev. DNo known errata.
9.2 Errata ATmega88PAThe revision letter in this section refers to the revision of the ATmega88PA device.
9.2.1 Rev. FNo known errata.
9.3 Errata ATmega168PAThe revision letter in this section refers to the revision of the ATmega168PA device.
9.3.1 Rev ENo known errata.
9.4 Errata ATmega328PThe revision letter in this section refers to the revision of the ATmega328P device.
9.4.1 Rev DNo known errata.
9.4.2 Rev CNot sampled.
9.4.3 Rev B• Unstable 32 kHz Oscillator
1. Unstable 32 kHz OscillatorThe 32 kHz oscillator does not work as system clock.
The 32 kHz oscillator used as asynchronous timer is inaccurate.
Problem Fix/ WorkaroundNone
9.4.4 Rev A• Unstable 32 kHz Oscillator
1. Unstable 32 kHz OscillatorThe 32 kHz oscillator does not work as system clock.
The 32 kHz oscillator used as asynchronous timer is inaccurate.
Problem Fix/ WorkaroundNone
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10. Datasheet Revision HistoryPlease note that the referring page numbers in this section are referred to this document. Thereferring revision in this section are referring to the document revision.
10.1 Rev. 8161C – 05/09
10.2 Rev. 8161B – 01/09
1. Updated ”Features” on page 1 for ATmega48PA/88PA/168PA/328P.
2. Updated ”Overview” on page 5 included the Table 2-1 on page 6.
3. Updated ”AVR Memories” on page 16 included ”Register Description” on page 21 and inserted Figure 7-1 on page 17.
4. Updated ”Register Description” on page 44.
5. Updated ”System Control and Reset” on page 46.
6. Updated ”Interrupts” on page 57.
7. Updated ”External Interrupts” on page 70.
8. Updated ”Boot Loader Support – Read-While-Write Self-Programming, ATmega88PA, ATmega168PA and ATmega328P” on page 277.
9. Inserted ”ATmega168PA DC Characteristics” on page 315.
10. Inserted ”ATmega328P DC Characteristics” on page 316.
11. Inserted ”ATmega168PA Typical Characteristics” on page 375.
12. Inserted ”ATmega328P Typical Characteristics” on page 399.
13. Inserted Ordering Information for ”ATmega168PA” on page 432.
14. Inserted Ordering Information for ”ATmega328P” on page 433.
15. Inserted ”Errata ATmega328P” on page 438.
16. Editing updates.
1. Updated ”Features” on page 1 for ATmega48PA and updated the book accordingly.
2. Updated ”Overview” on page 5 included the Table 2-1 on page 6.
3. Updated ”AVR Memories” on page 16 included ”Register Description” on page 21 and inserted Figure 7-1 on page 17.
4. Updated ”Register Description” on page 44.
5. Updated ”System Control and Reset” on page 46.
6. Updated ”Interrupts” on page 57.
7. Updated ”External Interrupts” on page 70.
8. Inserted Typical characteristics for ”ATmega48PA Typical Characteristics” on page 327.
9. Updated figure names in Typical characteristics for ”ATmega88PA Typical Character-istics” on page 351.
10. Inserted ”ATmega48PA DC Characteristics” on page 314.
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10.3 Rev. 8161A – 11/08
11. Updated Table 28-1 on page 317 by removing the footnote from Vcc/User calibration
12. Updated Table 28-7 on page 323 by removing Max value (2.5 LSB) from Absoluteaccuracy, VREF = 4V, VCC = 4V, ADC clock = 200 kHz.
13. Inserted Ordering Information for ”ATmega48PA” on page 430.
1. Initial revision (Based on the ATmega48P/88P/168P/328P datasheet 8025F-AVR-08/08).
2. Changes done compared to ATmega48P/88P/168P/328P datasheet 8025F-AVR-08/08:
– Updated ”DC Characteristics” on page 313 with new typical values for ICC.
– Updated ”Speed Grades” on page 316.
– New graphics in ”Typical Characteristics” on page 326.
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