Microcomputer Systems 1 ADSP-BF533 Ez-Kit Lite Audio Interface.

Microcomputer Systems 1ADSP-BF533 Ez-Kit Lite Audio Interface

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*Veton Kpuska*Lab #3 Audio Interface

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*Veton Kpuska*ADSP-BF533 Ez-Kit Lite Audio InterfaceSPISPORT0

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*Veton Kpuska*BF533 EZ-Kit Lite Audio InterfaceEZ-Kit Lite contains AD1836 Audio Codec

The AD1836 audio codec provides three channels of stereo audio output and two channels of multi-channel/stereo 96 kHz input. The SPORT0 interface of the processor links with the stereo audio data input and output pins of the AD1836 codec.

The processor is capable of transferring data to the audio codec in time-division multiplexed (TDM) or two-wire interface (TWI) mode.

The TDM mode can operate at a maximum of 48 kHz sample rate but allows simultaneous use of all input and output channels.

The TWI mode allows the codec to operate at a 96 kHz sample rate but limits the output channels to two. When using TWI mode, the TSCLK0 and RSCLK0 pins, as well as the TFS0 and RFS0 pins of the processor, must be tied together external to the processor. This is accomplished with the SW9 DIP switch (see Push Button Enable Switch (SW9) on page 2-12 for more information).

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*Veton Kpuska*Blackfin Audio Interface UsageTwo-Wire Interface (TWI) and Serial Peripheral Interface (SPI)Forward channel used to configure and control audio convertersReverse channel relays feedback info from converters

SPORTs Used as data channel for audio dataSPORT TX connects to audio DACSPORT RX connects to audio ADCFull-duplex SPORT RX/TX connects to audio codec

In some codecs (e.g., AC97), SPORT also can serve as the codec control channel

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*Veton Kpuska*BF533 Interface with AD1871Configuration & ControlData Transfer & Synch

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*Veton Kpuska*SW9 Switch ConfigurationMake sure that SW9 switches 5 and 6 are ON & SW12 is ON. See explanation bellow:

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*Veton Kpuska*Switch Default Configuration

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*Veton Kpuska*Push-buttons and LEDs

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*Veton Kpuska*Push Button Enable Switch (SW9 & SW12)SW9Positions 1 through 4:Disconnects the drivers associated with the push buttons from the PF pins of the processor.Positions 5 and 6: Used to connect the transmit and receive frame syncs and clocks of SPORT0. This is important when the AD1836 audio/video decoder and the processor are communicating in I2S mode.SW12When is set to OFF, SW12 disconnects SPORT0 from the audio codec. The default is the ON position.

Table 2-6 in the next slide shows which PF is driven when the switch is in the default (ON) position.

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*Veton Kpuska*Push Button Enable Switch (SW9)Table 2-6 shows which PF is driven when the switch is in the default (ON) position

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*Veton Kpuska*SPORT0 interface to AD1836 audio codecThe SPORT0 connects to the AD1836 audio codec and the expansion interface.

The AD1836 codec uses both the primary and secondary data transmit and receive pins to input and output data from the audio inputs and outputs.

The SPORT1 connects to the SPORT connector (P3) and the expansion interface.

The pinout of the SPORT connector and the expansion interface connectors can be found in ADSP-BF533 EZ-KIT Lite Schematic on page B-1.

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*Veton Kpuska*The pin layout of the SPORT connector & expansion interface connectorsSW12

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*Veton Kpuska*Audio Interface ConfigurationThe AD1836 audio codecs internal configuration registers are configured using the Serial Port Interface - SPI port of the processor (see Slide #6). The processors PF4 - programmable flag pin is used as the select for this device.For information on how to configure the multi-channel codec, go to www.analog.com/UploadedFiles/Datasheets/344740003AD1836_prc.pdf.

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*Veton Kpuska*Audio Interface and Programmable FlagsThe processor has 15 programmable flag pins (PFs). The pins are multifunctional and depend on the processor setup. Table 2-1 in the ADSP-BF533 EZ-KIT Lite Evaluation System Manual provides the summary of the programmable flag pins used on the EZ-Kit Lite.

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*Veton Kpuska*Programmable Flag Connections

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*Veton Kpuska*Audio Interface Configuration (cont.)The general-purpose IO pin PA0 of flash A is a source for the AD1836 codec reset. See Flash General-Purpose IO on page 1-12 for more information about the pin of ADSP-BF533 EZ-KIT Lite Evaluation System Manual.Also information given in the next slide.

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*Veton Kpuska*AD1836 codec reset via PA0

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*Veton Kpuska*Flash General-Purpose IOGeneral-purpose IO signals are controlled by means of setting appropriate registers of the flash A or flash B. These registers are mapped into the processors address space, as shown in the Table below (ADSP-BF533 EZ-KIT Lite Evaluation System Manual Flash Memory)

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*Veton Kpuska*Flash General-Purpose IOFlash device IO pins are arranged as 8-bit ports labeled A through G. There is a set of 8-bit registers associated with each port. These registers are Direction, Data In, and Data Out. Note that the Direction and Data Out registers are cleared to all zeros at power-up or hardware reset.

The Direction register controls IO pins direction. This is a 8-bit read-write register.When a bit is 0, a corresponding pin functions as an input. When the bit is 1, a corresponding pin is an output.

The Data In register allows reading the status of ports pins. This is a 8-bit read-only register.

The Data Out register allows clearing an output pin to 0 or setting it to 1. This is a 8-bit read-write register.

The ADSP-BF533 EZ-KIT Lite board employs only flash A and flash B ports A and B. Table 1-5 and Table 1-6 provide configuration register addresses for flash A and flash B, respectively (only ports A and B are listed in the next slide). The following bits connect to the expansion board connector.Flash A: port A bits 7 and 6, as well as port B bits 7 and 6Flash B: port A bits 70

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*Veton Kpuska*Flash A & B Configuration Registers for Ports A and B.Table 1-5. Flash A Configuration Registers for Ports A and B

Table 1-6. Flash B Configuration Registers for Ports A and B

Register NamePort A AddressPort B AddressData In (read-only)0x2027 00000x2027 0001Data Out (read-write)0x2027 00040x2027 0005Direction (read-write)0x2027 00060x2027 0007

Register NamePort A AddressPort B AddressData In (read-only)0x202E 00000x202E 0001Data Out (read-write)0x202E 00040x202E 0005Direction (read-write)0x202E 00060x202E 0007

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*Veton Kpuska*IO Assignments for Port A and BTable 1-7 Flash A Port A Controls.

Bit NumberUser IOBit Value7Not definedAny6Not definedAny5PPI clock select bit 100=local OSC (27MHz)4PPI clock select bit 001=video decoder pixel clock1x=expansion board PPI clock3Video decoder reset0=reset ON; 1=reset OFF2Video encoder reset0=reset ON; 1=reset OFF1ReservedAny0Codec reset0=reset ON; 1=reset OFF

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Talk-ThroughAnalysis of Lab Exercise

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*Veton Kpuska*main.c//--------------------------------------------------------------------------//// //// Name: Talkthrough for the ADSP-BF533 EZ-KIT Lite //// ////--------------------------------------------------------------------------//// ////(C) Copyright 2003 - Analog Devices, Inc. All rights reserved. //// ////Project Name:BF533 C Talkthrough TDM //// ////Date Modified:04/03/03HDRev 1.0 //// ////Software:VisualDSP++3.1 //// ////Hardware:ADSP-BF533 EZ-KIT Board //// ////Connections:Connect an input source (such as a radio) to the Audio ////input jack and an output source (such as headphones) to ////the Audio output jack //// ////Purpose:This program sets up the SPI port on the ADSP-BF533 to ////configure the AD1836 codec. The SPI port is disabled ////after initialization. The data to/from the codec are ////transfered over SPORT0 in TDM mode //// ////--------------------------------------------------------------------------//

#include "Talkthrough.h"#include "sysreg.h"#include "ccblkfn.h"#include

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*Veton Kpuska*Talkthrough.h#ifndef __Talkthrough_DEFINED#define __Talkthrough_DEFINED//--------------------------------------------------------------------------//// Header files ////--------------------------------------------------------------------------//#include #include #include #include //--------------------------------------------------------------------------//// Symbolic constants ////--------------------------------------------------------------------------//// addresses for Port B in Flash A#define pFlashA_PortA_Dir (volatile unsigned char *)0x20270006#define pFlashA_PortA_Data (volatile unsigned char *)0x20270004

// names for codec registers, used for iCodec1836TxRegs[]#define DAC_CONTROL_10x0000#define DAC_CONTROL_20x1000#define DAC_VOLUME_00x2000#define DAC_VOLUME_10x3000#define DAC_VOLUME_20x4000#define DAC_VOLUME_30x5000#define DAC_VOLUME_40x6000#define DAC_VOLUME_50x7000#define ADC_0_PEAK_LEVEL 0x8000#define ADC_1_PEAK_LEVEL 0x9000#define ADC_2_PEAK_LEVEL 0xA000#define ADC_3_PEAK_LEVEL 0xB000#define ADC_CONTROL_10xC000#define ADC_CONTROL_20xD000#define ADC_CONTROL_30xE000

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*Veton Kpuska*Flash A & B Configuration Registers for Ports A and B.Table 1-5. Flash A Configuration Registers for Ports A and B

Table 1-6. Flash B Configuration Registers for Ports A and B

Register NamePort A AddressPort B AddressData In (read-only)0x2027 00000x2027 0001Data Out (read-write)0x2027 00040x2027 0005Direction (read-write)0x2027 00060x2027 0007

Register NamePort A AddressPort B AddressData In (read-only)0x202E 00000x202E 0001Data Out (read-write)0x202E 00040x202E 0005Direction (read-write)0x202E 00060x202E 0007

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*Veton Kpuska*DAC Control Register 1 & 2From: AD1836A Multi-channel Codec Manual#define DAC_CONTROL_10x0000 #define DAC_CONTROL_20x1000

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*Veton Kpuska*DAC Volume Control Registers#define DAC_VOLUME_00x2000 #define DAC_VOLUME_10x3000 #define DAC_VOLUME_20x4000 #define DAC_VOLUME_30x5000 #define DAC_VOLUME_40x6000 #define DAC_VOLUME_50x7000

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*Veton Kpuska*ADC Peak Level Registers#define ADC_0_PEAK_LEVEL 0x8000 #define ADC_1_PEAK_LEVEL 0x9000 #define ADC_2_PEAK_LEVEL 0xA000 #define ADC_3_PEAK_LEVEL 0xB000

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*Veton Kpuska*ADC Control Register 1#define ADC_CONTROL_10xC000 #define ADC_CONTROL_20xD000 #define ADC_CONTROL_30xE000

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*Veton Kpuska*Talkthrough.h (cont. 1)// names for slots in ad1836 audio frame#define INTERNAL_ADC_L00#define INTERNAL_ADC_L11#define INTERNAL_ADC_R04#define INTERNAL_ADC_R15#define INTERNAL_DAC_L00#define INTERNAL_DAC_L11#define INTERNAL_DAC_L22#define INTERNAL_DAC_R04#define INTERNAL_DAC_R15#define INTERNAL_DAC_R26

// size of array iCodec1836TxRegs and iCodec1836RxRegs#define CODEC_1836_REGS_LENGTH11

// SPI transfer mode#define TIMOD_DMA_TX 0x0003

// SPORT0 word length#define SLEN_320x001f

// DMA flow mode#define FLOW_10x1000

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*Veton Kpuska*Talkthrough.h (cont. 2)//--------------------------------------------------------------------------//// Global variables ////--------------------------------------------------------------------------//extern int iChannel0LeftIn;extern int iChannel0RightIn;extern int iChannel0LeftOut;extern int iChannel0RightOut;extern int iChannel1LeftIn;extern int iChannel1RightIn;extern int iChannel1LeftOut;extern int iChannel1RightOut;extern volatile short sCodec1836TxRegs[];extern volatile int iRxBuffer1[];extern volatile int iTxBuffer1[];

//--------------------------------------------------------------------------//// Prototypes ////--------------------------------------------------------------------------//// in file Initialisation.cvoid Init_EBIU(void);void Init_Flash(void);void Init1836(void);void Init_Sport0(void);void Init_DMA(void);void Init_Sport_Interrupts(void);void Enable_DMA_Sport0(void);

// in file Process_data.cvoid Process_Data(void);

// in file ISRs.cEX_INTERRUPT_HANDLER(Sport0_RX_ISR);

#endif //__Talkthrough_DEFINED

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*Veton Kpuska*main.c#include "Talkthrough.h"#include "sysreg.h"#include "ccblkfn.h"#include //--------------------------------------------------------------------------//// Variables //// //// Description: The variables iChannelxLeftIn and iChannelxRightIn contain ////the data coming from the codec AD1836. The (processed) ////playback data are written into the variables ////iChannelxLeftOut and iChannelxRightOut respectively, which ////are then sent back to the codec in the SPORT0 ISR. ////The values in the array iCodec1836TxRegs can be modified to ////set up the codec in different configurations according to ////the AD1885 data sheet. ////--------------------------------------------------------------------------//// left input data from ad1836int iChannel0LeftIn, iChannel1LeftIn;// right input data from ad1836int iChannel0RightIn, iChannel1RightIn;// left ouput data for ad1836int iChannel0LeftOut, iChannel1LeftOut;// right ouput data for ad1836int iChannel0RightOut, iChannel1RightOut;

// SPORT0 DMA transmit buffervolatile int iTxBuffer1[8];// SPORT0 DMA receive buffervolatile int iRxBuffer1[8];

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*Veton Kpuska*main.c (cont 1)// array for registers to configure the ad1836 names are defined in "Talkthrough.h"volatile short sCodec1836TxRegs[CODEC_1836_REGS_LENGTH] = {DAC_CONTROL_1| 0x000,DAC_CONTROL_2| 0x000,DAC_VOLUME_0| 0x3ff,DAC_VOLUME_1| 0x3ff,DAC_VOLUME_2| 0x3ff,DAC_VOLUME_3| 0x3ff,DAC_VOLUME_4| 0x3ff,DAC_VOLUME_5| 0x3ff,ADC_CONTROL_1| 0x000,ADC_CONTROL_2| 0x180,ADC_CONTROL_3| 0x000 };

#define DAC_CONTROL_10x0000 | 0x000 = 0x0000 #define DAC_CONTROL_20x1000 | 0x000 = 0x1000 #define DAC_VOLUME_00x2000 | 0x3ff = 0x23ff #define DAC_VOLUME_10x3000 | 0x3ff = 0x33ff #define DAC_VOLUME_20x4000 | 0x3ff = 0x43ff #define DAC_VOLUME_30x5000 | 0x3ff = 0x53ff #define DAC_VOLUME_40x6000 | 0x3ff = 0x63ff #define DAC_VOLUME_50x7000 | 0x3ff = 0x73ff#define ADC_CONTROL_10xC000 | 0x000 = 0xC000 #define ADC_CONTROL_20xD000 | 0x180 = 0xD180 #define ADC_CONTROL_30xE000 | 0x000 = 0xE000

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*Veton Kpuska*DAC Volume Control Registers#define DAC_VOLUME_00x23ff0010 0011 1111 1111 #define DAC_VOLUME_10x33ff0011 0011 1111 1111 #define DAC_VOLUME_20x43ff0100 0011 1111 1111 #define DAC_VOLUME_30x53ff 0101 0011 1111 1111 #define DAC_VOLUME_40x63ff0110 0011 1111 1111 #define DAC_VOLUME_50x73ff0111 0011 1111 1111

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*Veton Kpuska*ADC Peak Level Registers#define ADC_0_PEAK_LEVEL 0x8000 #define ADC_1_PEAK_LEVEL 0x9000 #define ADC_2_PEAK_LEVEL 0xA000 #define ADC_3_PEAK_LEVEL 0xB000

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*Veton Kpuska*ADC Control Register 1#define ADC_CONTROL_10xC000 1100 000 000 000

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*Veton Kpuska*ADC Control Register 2#define ADC_CONTROL_20xD180 1101 0001 1000 0000

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*Veton Kpuska*ADC Control Register 3#define ADC_CONTROL_30xE0001110 0000 0000 0000

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*Veton Kpuska*ADC Master Mode

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*Veton Kpuska*ADC Slave Mode

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*Veton Kpuska*main.c (cont 2) // SPORT0 DMA transmit buffervolatile int iTxBuffer1[8];// SPORT0 DMA receive buffervolatile int iRxBuffer1[8];

////////////////////// BTC Definitions////////////////////#define MAXBTCBUF 24000

int BTCLeft[MAXBTCBUF];int BTCRight[MAXBTCBUF];

int BTCLeftVolume = 0;int BTCRightVolume = 0;

BTC_MAP_BEGIN// Channel Name, Starting Address, Length (bytes)BTC_MAP_ENTRY("Audio Left Channel", (long)&BTCLeft, sizeof(BTCLeft))BTC_MAP_ENTRY("Audio Right Channel", (long)&BTCRight, sizeof(BTCRight))BTC_MAP_ENTRY("Audio Left Volume", (long)&BTCLeftVolume, sizeof(BTCLeftVolume))BTC_MAP_ENTRY("Audio Right Volume", (long)&BTCRightVolume, sizeof(BTCRightVolume))BTC_MAP_END

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*Veton Kpuska*main.c (cont. 3)//--------------------------------------------------------------------------//// Function:main //// //// Description:After calling a few initalization routines, main() just ////waits in a loop forever. The code to process the incoming ////data can be placed in the function Process_Data() in the ////file "Process_Data.c". ////--------------------------------------------------------------------------//void main(void){

sysreg_write(reg_SYSCFG, 0x32); //Initialize System Configuration RegisterInit_EBIU();Init_Flash();Init1836();Init_Sport0();Init_DMA();Init_Sport_Interrupts();Enable_DMA_Sport0();btc_init();

while(1) {btc_poll();}}

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*Veton Kpuska*Background Telemetry Channels (BTCs)Background telemetry channels (BTCs) enable VisualDSP++ and a processor to exchange data via the JTAG interface while the processor is executing.Before BTC, all communication between VisualDSP++ and a processor took place while the processor was in a halted state.

Note: Background telemetry channels are supported only in SHARC and Blackfin emulator sessions.

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*Veton Kpuska*BTC Definitions in the ProgramBackground telemetry channels are defined on a per program (.DXE) basis. The channels are defined when a specific program is loaded onto a processor. BTC channels are defined in a program by using simple macros. The following example code shows channel definitions.

#include "btc.h

BTC_MAP_BEGIN// Channel Name, Starting Address, Length (bytes)BTC_MAP_ENTRY("Audio Left Channel", (long)&BTCLeft, sizeof(BTCLeft))BTC_MAP_ENTRY("Audio Right Channel", (long)&BTCRight, sizeof(BTCRight))BTC_MAP_ENTRY("Audio Left Volume", (long)&BTCLeftVolume, sizeof(BTCLeftVolume))BTC_MAP_ENTRY("Audio Right Volume", (long)&BTCRightVolume, sizeof(BTCRightVolume))BTC_MAP_END

The first step in defining channels in a program is to include the BTC macros by using the #include btc.h statement. Then each channel is defined with the macros. The definitions begin with BTC_MAP_BEGIN, which marks the beginning of the BTC map. Next, each individual channel is defined with the BTC_MAP_ENTRY macro, which takes the parameters described in Table 2-17 in VisualDSP++ 4.5 Users Guide.

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*Veton Kpuska*BTC_MAP_ENTRY Macro

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Initialize.cEBIU setupFlash setupFIO setupADI1836SPORT0DMA configurationSPORT IRSDMA SupportEndless loop and processing Flag Interrupts

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*Veton Kpuska*External Bus Interface Unit (EBIU) Setup#include "Talkthrough.h"

//--------------------------------------------------------------------------//// Function:Init_EBIU //// //// Description: This function initializes and enables asynchronous memory ////banks in External Bus Interface Unit so that Flash A can be ////accessed. ////--------------------------------------------------------------------------//void Init_EBIU(void){*pEBIU_AMBCTL0= 0x7bb07bb0;*pEBIU_AMBCTL1= 0x7bb07bb0;*pEBIU_AMGCTL= 0x000f;}

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*Veton Kpuska*External Bus Interface UnitThe EBIU services requests for external memory from theCore or from a DMA channel.

The priority of the requests is determined by the External Bus Controller. The address of the request determines whether the request is serviced by the EBIU SDRAM Controller or the EBIU Asynchronous Memory Controller.

The EBIU is clocked by the system clock (SCLK). All synchronous memories interfaced to the processor operate at the SCLK frequency.

The ratio between core frequency and SCLK frequency is programmable using a phase-locked loop (PLL) system memory-mapped register (MMR).

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*Veton Kpuska*EBIU Programming ModelThis programming model is based on system memory-mapped registers used to program the EBIU.

There are six control registers and one status register in the EBIU. They are:

Asynchronous Memory Global Control register (EBIU_AMGCTL)Asynchronous Memory Bank Control 0 register (EBIU_AMBCTL0)Asynchronous Memory Bank Control 1 register (EBIU_AMBCTL1)

SDRAM Memory Global Control register (EBIU_SDGCTL)SDRAM Memory Bank Control register (EBIU_SDBCTL)SDRAM Refresh Rate Control register (EBIU_SDRRC)

SDRAM Control Status register (EBIU_SDSTAT)

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*Veton Kpuska*The Asynchronous Memory Interface The asynchronous memory interface allows interfaceing to a variety of memory and peripheral types. These include SRAM, ROM, EPROM,flash memory, and FPGA/ASIC designs.

Four asynchronous memory regions are supported. Each has a unique memory select associated with it, shown in Table 17-3.

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*Veton Kpuska*Asynchronous Memory Bank Address Range

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*Veton Kpuska*EBIU_AMGCTL RegisterThe Asynchronous Memory Global Control register (EBIU_AMGCTL) configures global aspects of the controller. The EBIU_AMGCTL register should be the last control register written to when configuring the processor to access external memory-mapped asynchronous devices.

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*Veton Kpuska*Initialization.c//--------------------------------------------------------------------------//// Function:Init_EBIU //// //// Parameters:None //// //// Return:None //// //// Description:This function initializes and enables the asynchronous ////memory banks for the External Bus Interface Unit (EBIU), so ////that access to Flash A is possible. ////--------------------------------------------------------------------------//void Init_EBIU(void){*pEBIU_AMBCTL0= 0x7bb07bb0;*pEBIU_AMBCTL1= 0x7bb07bb0;*pEBIU_AMGCTL= 0x000f;}Asynchronous Memory Global Control Register

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*Veton Kpuska*Asynchronous Memory Global Control Register EBIU_AMGCTL0x000f = 0000 0000 0000 1111

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*Veton Kpuska*Initialization.c//--------------------------------------------------------------------------//// Function:Init_EBIU //// //// Parameters:None //// //// Return:None //// //// Description:This function initializes and enables the asynchronous ////memory banks for the External Bus Interface Unit (EBIU), so ////that access to Flash A is possible. ////--------------------------------------------------------------------------//void Init_EBIU(void){*pEBIU_AMBCTL0= 0x7bb07bb0;*pEBIU_AMBCTL1= 0x7bb07bb0;*pEBIU_AMGCTL= 0x000f;}Asynchronous Memory Control Register

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*Veton Kpuska*EBIU_AMBCTL0 and EBIU_AMBCTL1 RegistersThe EBIU asynchronous memory controller has two Asynchronous Memory Bank Control registers:EBIU_AMBCTL0 and EBIU_AMBCTL1. They contain bits for counters for:setup, strobe, and hold time; bits to determine memory type and size; andbits to configure use of ARDY.

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*Veton Kpuska*Asynchronous Memory Bank Control 0 Register0x7bb07bb0 = 0111 1011 1011 0000 0111 1011 1011 0000

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*Veton Kpuska*External Memory MapThe three SDRAM control registers must be initialized in order to use the MT48LC32M16 64 MB (32M x 16 bits) SDRAM memory of EZ-Kit Lite:EBIU_SDGCTL: SDRAM Memory Global Control register EBIU_SDBCTL: SDRAM Memory Bank Control register EBIU_SDRRC: SDRAM Refresh Rate Control register

The External Memory Map supported by BF533 is provided in the Figure 17-1.

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*Veton Kpuska*EBIU_SDGCTL RegisterThe SDRAM Memory Global Control register (EBIU_SDGCTL) includes all programmable parameters associated with the SDRAM access timing and configuration. Figure 17-10 shows the EBIU_SDGCTL register bit definitions.

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*Veton Kpuska*SDRAM Memory Global Control register: EBIU_SDGCTL

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Initialize.cEBIU setupFlash setupFIO setupADI1836SPORT0DMA configurationSPORT IRSDMA SupportEndless loop and processing Flag Interrupts

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*Veton Kpuska*Initialize.c//--------------------------------------------------------------------------//// Function:Init_Flash //// //// Description: This function initializes pin direction of Port A in Flash A ////to output. The AD1836_RESET on the ADSP-BF533 EZ-KIT board ////is connected to Port A. ////--------------------------------------------------------------------------//void Init_Flash(void){*pFlashA_PortA_Dir = 0x1;}

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*Veton Kpuska*Initialize.c//--------------------------------------------------------------------------//// Function:Init_Flash //// //// Description: This function initializes pin direction of Port A in Flash A ////to output. The AD1836_RESET on the ADSP-BF533 EZ-KIT board ////is connected to Port A. ////--------------------------------------------------------------------------//void Init_Flash(void){*pFlashA_PortA_Dir = 0x1;}

0x1 = 0001The Direction register controls IO pins direction. This is a 8-bit read-write register.When a bit is 0, a corresponding pin functions as an input. When the bit is 1, a corresponding pin is an output. See Slide #13 for details or EZ-Kit Lite HRM.Direction Configuration

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Initialize.cEBIU setupFlash setupFIO setupADC1836SPORT0DMA configurationSPORT IRSDMA SupportEndless loop and processing Flag Interrupts

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*Veton Kpuska*Initialize.c//--------------------------------------------------------------------------//// Function:Init1836() //// //// Description: This function sets up the SPI port to configure the AD1836. ////The content of the array sCodec1836TxRegs is sent to the ////codec. ////--------------------------------------------------------------------------//void Init1836(void){int i;int j;static unsigned char ucActive_LED = 0x01;// write to Port A to reset AD1836*pFlashA_PortA_Data = 0x00;// write to Port A to enable AD1836*pFlashA_PortA_Data = ucActive_LED;// wait to recover from resetfor (i=0; i

*Veton Kpuska*Serial Peripheral Interface (SPI)The processor has a Serial Peripheral Interface (SPI) port that provides an I/O interface to a wide variety of SPI compatible peripheral devices.

SPI is a four-wire interface consisting of two data pins (IN & OUT), a device select pin (SPISS), and a clock (CLK) pin.

SPI is a full-duplex synchronous serial interface, supporting master modes, slave modes, and multimaster environments.

The SPI compatible peripheral implementation also supports programmable baud rate and clock phase/polarities.

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*Veton Kpuska*Serial Peripheral Interface (SPI)Typical SPI compatible peripheral devices that can be used to interface to the SPI compatible interface include:Other CPUs or microcontrollersCodecsA/D convertersD/A convertersSample rate convertersSP/DIF or AES/EBU digital audio transmitters and receiversLCD displaysShift registersFPGAs with SPI emulation

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*Veton Kpuska*Serial Peripheral Interface (SPI)The SPI is an industry-standard synchronous serial link that supports communication with multiple SPI compatible devices. The SPI peripheral is a synchronous, four-wire interface consisting of two data pins:Master Out Slave In (MOSI) and Master In Slave Out (MISO) one device select pin Serial Peripheral Interface Slave Select (SPISS) Input Signal, and a gated clock pin Serial Peripheral Interface Clock (SCK) Signal. With the two data pins, it allows for full-duplex operation to other SPI compatible devices.

The SPI also includes programmable baud rates, clock phase, and clock polarity.

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*Veton Kpuska*Serial Peripheral Interface (SPI)The SPI can operate in a multimaster environment by interfacing with several other devices, acting as either a master device or a slave device.

Figure 10-1 provides a block diagram of the SPI. The interface is essentially a shift register that serially transmits and receives data bits, one bit at a time at the SCK rate, to and from other SPI devices. SPI data is transmitted and received at the same time through the use of a shift register.

When an SPI transfer occurs, data is simultaneously transmitted (shifted serially out of the shift register) as new data is received (shifted serially into the other end of the same shift register).

The SCK synchronizes the shifting and sampling of the data on the two serial data pins.

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*Veton Kpuska*SPI Block Diagram

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SPI Interface SignalsEBIU setupFlash setupFIO setupADI1836 - SPISPORT0DMA configurationSPORT IRSDMA SupportEndless loop and processing Flag Interrupts

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*Veton Kpuska*Serial Peripheral Interface Clock Signal (SCK)The SCK signal is the SPI clock signal. This control signal is driven by the master and controls the rate at which data is transferred. The master may transmit data at a variety of baud rates. The SCK signal cycles once for each bit transmitted. It is an output signal if the device is configured as a master, and an input signal if the device is configured as a slave.

The SCK is a gated clock that is active during data transfers only for the length of the transferred word. The number of active clock edges is equal to the number of bits driven on the data lines. Slave devices ignore the serial clock if the Serial Peripheral Slave Select Input (SPISS) is driven inactive (high).

The SCK is used to shift out and shift in the data driven on the MISO and MOSI lines. The data is always shifted out on active edges of the clock and sampled on inactive edges of the clock.

Clock polarity and clock phase relative to data are programmable in the SPI Control register (SPI_CTL) and define the transfer format.

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*Veton Kpuska*Serial Peripheral Interface Slave Select InputSignalThe SPISS signal is the SPI Serial Peripheral Slave Select Input signal. This is an active-low signal used to enable a processor when it is configured as a slave device. This input-only pin behaves like a chip select and is provided by the master device for the slave devices.

For a master device, it can act as an error signal input in case of the multimaster environment. In multimaster mode, if the SPISS input signal of a master is asserted (driven low), and the PSSE bit in the SPI_CTL register is enabled, an error has occurred. This means that another device is also trying to be the master device.

Note: The SPISS signal is the same pin as the PF0 pin.

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*Veton Kpuska*Master Out Slave In (MOSI)& Master In Slave Out (MISO)Master Out Slave In (MOSI)The MOSI pin is the Master Out Slave In pin, one of the bidirectional I/O data pins. If the processor is configured as a master, the MOSI pin becomes a data transmit (output) pin, transmitting output data. If the processor is configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving input data.

In an SPI interconnection, the data is shifted out from the MOSI output pin of the master and shifted into the MOSI input(s) of the slave(s).

Master In Slave Out (MISO)The MISO pin is the Master In Slave Out pin, one of the bidirectional I/O data pins. If the processor is configured as a master, the MISO pin becomes a data receive (input) pin, receiving input data. If the processor is configured as a slave, the MISO pin becomes a data transmit (output) pin,

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*Veton Kpuska*ADSP-BF533 as Slave SPI Device

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*Veton Kpuska*Interrupt OutputThe SPI has two interrupt output signals: a data interrupt and an error interrupt

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*Veton Kpuska*SPI Data Interrupt OutputThe behavior of the SPI data interrupt signal depends on the Transfer Initiation Mode bit field (TIMOD) in the SPI Control register (discussed next). In DMA mode (TIMOD = 1X), the data interrupt acts as a DMA request and is generated when the DMA FIFO is ready to be written to (TIMOD = 11) or read from (TIMOD = 10). In non-DMA mode (TIMOD = 0X), a data interrupt is generatedwhen the SPI_TDBR is ready to be written to (TIMOD = 01) or when the SPI_RDBR is ready to be read from (TIMOD = 00).

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*Veton Kpuska*SPI Error Interrupt OutputAn SPI Error interrupt is generated in a master when a Mode Fault Error occurs, in both DMA and non-DMA modes. An error interrupt can also be generated in DMA mode when there is an underflow (TXE when TIMOD = 11) or an overflow (RBSY when TIMOD = 10) error condition. In non-DMA mode, the underflow and overflow conditions set the TXE and RBSY bits in the SPI_STAT register, respectively, but do not generate an error interrupt.

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*Veton Kpuska*SPI RegistersThe SPI peripheral includes a number of user-accessible registers. Some of these registers are also accessible through the DMA bus. Four registers contain control and status information: SPI_BAUD, SPI_CTL, SPI_FLG, andSPI_STAT.

Two registers are used for buffering receive and transmit data:SPI_RDBR and SPI_TDBR

For information about DMA-related registers, see Chapter 9 of ADSP-BF533 Blackfin Processor Hardware Reference, Direct Memory Access. also discussed next.

The shift register, SFDR, is internal to the SPI module and is not directly accessible.

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*Veton Kpuska*SPI Registers: SPI_BAUD RegisterThe SPI Baud Rate register (SPI_BAUD) is used to set the bit transfer rate for a master device.When configured as a slave, the value written to this register is ignored. The serial clock frequency is determined by this formula:SCK Frequency = (Peripheral clock frequency SCLK)/(2 x SPI_BAUD)

SCK Clock Divide FactorSPI_BAUD = 16 & assuming SCLK = 100 MHz SCK = 100 MHz/32 = 3125 kHz.

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*Veton Kpuska*SPI_BAUD Register

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*Veton Kpuska*SCLK & CCLKRead PLL Clock Multiplier Ratios section of chapter 8 Dynamic Power Management of ADSP-BF533 Blackfin Processor Hardware Reference manual.

Brief summary of the clock sources and clock rates:

The clock source on EZ Kit is 270 MHz oscillator.

The default SCLK is 54 MHz.

The SCLK value can be calculated from the PLL_CTL and PLL_DIV register values. By default the PLL_CTL = 0x1400, here the MSEL = 10, so the VCO frequency is 10x27 = 270 MHz.

By default the PLL_DIV = 0x0005, here CSEL = 0 and SSEL = 5, so CCLK = 270/1 = 270 MHz and SCLK = 270/5 = 54 MHz.

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*Veton Kpuska*Note on SPORT Clock division and frame syncThe clock division parameters are located in the SPORTx_TCLKDIV and SPORTx_RCLKDIV registers.To specify a clock frequency for the SPORT, use the following equation:

Where: f(sclk) is the frequency of the core (54 Mhz default on the EZ-KIT LITE), SPORTx_yCLK (y is T - for transmit, R for receive) frequency is the specified clock frequency of the SPORT, and SPORTx_yCLKDIV is the value needed to be input into the specified transmit/receive clock division register.Frame sync parameters are the number of serial clock cycles before a frame sync is generated. This value must not be less than the serial word length (SLEN), otherwise corrupt data will be received.# of serial clock cycles between frame syncs = SPORTx_yFSDIV + 1

For example, if one wanted a serial clock frequency of 375 kHz, and 32 bit words were used, then SPORTx_yCLKDIV = 54MHz/(2*375kHz) - 1 = 72 - 1 = 71 = 0x0048SPORTx_yFSDIV = 32 - 1 = 31 = 0x001f

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*Veton Kpuska*SPI_CTL RegisterThe SPI Control register (SPI_CTL) is used to configure and enable the SPI system.

This register is used to enable the SPI interface, select the device as a master or slave, and determine the data transfer format and word size.

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*Veton Kpuska*SPI_CTL Register DetailsThe term word refers to a single data transfer of either 8 bits or 16 bits, depending on the word length (SIZE) bit in SPI_CTL. There are two special bits which can also be modified by the hardware: SPE and MSTR.

The TIMOD field is used to specify the action that initiates transfers to/from the receive/transmit buffers. When set to 00, a SPI port transaction is begun when the receive buffer is read. Data from the first read will need to be discarded since the read is needed to initiate the first SPI port transaction.When set to 01, the transaction is initiated when the transmit buffer is written. A value of 10 selects DMA Receive Mode and the first transaction is initiated by enabling the SPI for DMA Receive mode. Subsequent individual transactions are initiated by a DMA read of the SPI_RDBR. A value of 11 selects DMA Transmit Mode and the transaction is initiated by a DMA write of the SPI_TDBR.

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*Veton Kpuska*SPI_CTL Register DetailsThe PSSE bit is used to enable the SPISS input for master. When not used, SPISS can be disabled, freeing up a chip pin as general-purpose I/O.

The EMISO bit enables the MISO pin as an output. This is needed in an environment where the master wishes to transmit to various slaves at one time (broadcast). Only one slave is allowed to transmit data back to the master. Except for the slave from whom the master wishes to receive, all other slaves should have this bit cleared.

The SPE and MSTR bits can be modified by hardware when the MODF bit of the Status register is set. See Mode Fault Error on page 10-27 of ADSP-BF533 Blackfin Processor Hardware Reference manual.

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*Veton Kpuska*SPI_CTL Register Details*pSPI_CTL = TIMOD_DMA_TX | SIZE | MSTR TIMOD_DMA_TX 0x0003 = 0000 0000 0000 0011 SIZE = 0000 0001 0000 0000 MSTR = 0001 0000 0000 0000

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*Veton Kpuska*Summary of SPI Register Functions

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BF533 Direct Memory Access - DMABF533 DMA Support

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*Veton Kpuska*ADSP-BF533 Ez-Kit Lite Audio InterfaceSPISPORT0EBIU

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*Veton Kpuska*Processor Memory ArchitectureDMA ControllerEBIUDMA PeripheralsCore ProcessorL1 Memory

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*Veton Kpuska*BF533 DMA SupportThe processor has multiple, independent DMA controllers that support automated data transfers with minimal overhead for the core. DMA transfers can occur between the internal memories and any of its DMA-capable peripherals.Additionally, DMA transfers can be accomplished between any of the DMA-capable peripherals and external devices connected to the external memory interfaces, including the SDRAM controller and the asynchronous memory controller. DMA-capable peripherals include the SPORTs, SPI port, UART, and PPI.

Each individual DMA-capable peripheral has at least one dedicated DMA channel.

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*Veton Kpuska*BF533 DMA SupportThe DMA controller supports both one-dimensional (1D) andtwo-dimensional (2D) DMA transfers.

DMA transfer initialization can be implemented from registers or from sets of parameters called descriptor blocks.

The 2D DMA capability supports arbitrary row and column sizes up to 64K elements by 64K elements, and arbitrary row and column step sizes up to +/- 32K elements. Furthermore, the column step size can be less than the row step size, allowing implementation of interleaved datastreams. This feature is especially useful in video applications where data can be de-interleaved on the fly.

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*Veton Kpuska*Generic Names of the DMA Memory-Mapped Registers

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*Veton Kpuska*DMA Channel Map

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ADI1836 SPI DMA ConfigurationEBIU setupFlash setupFIO setupADI1836 - DMASPORT0DMA configurationSPORT IRSDMA SupportEndless loop and processing Flag Interrupts

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*Veton Kpuska*Initialize.c: Init1836()// Set up DMA5 to transmit// Map DMA5 to SPI*pDMA5_PERIPHERAL_MAP= 0x5000;

// Configure DMA5// 16-bit transfers*pDMA5_CONFIG = WDSIZE_16;// Start address of data buffer*pDMA5_START_ADDR = sCodec1836TxRegs;// DMA inner loop count*pDMA5_X_COUNT = CODEC_1836_REGS_LENGTH;// Inner loop address increment*pDMA5_X_MODIFY = 2;// enable DMAs*pDMA5_CONFIG = (*pDMA5_CONFIG | DMAEN);// enable spi*pSPI_CTL = (*pSPI_CTL | SPE);// wait until dma transfers for spi are finished for (j=0; j

*Veton Kpuska*DMA Channels Peripheral Map RegisterEach DMA channels Peripheral Map register (DMAx_PERIPHERAL_MAP) contains bits that:Map the channel to a specific peripheral.Identify whether the channel is a Peripheral DMA channel or a Memory DMA channel.

*pDMA5_PERIPHERAL_MAP= 0x5000;

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*Veton Kpuska*DMA Configuration RegisterThe DMA Configuration register (DMAx_CONFIG/MDMA_yy_CONFIG), shown in Figure 9-3 of ADSP-BF533 Blackfin Processor Hardware Reference, also in this slide is used to set up DMA parameters and operating modes.*pDMA5_CONFIG= 0000 0000 0000 0100 = 0x0004;

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*Veton Kpuska*main.c (cont 1)// array for registers to configure the ad1836 names are defined in "Talkthrough.h"volatile short sCodec1836TxRegs[CODEC_1836_REGS_LENGTH] = {DAC_CONTROL_1| 0x000,DAC_CONTROL_2| 0x000,DAC_VOLUME_0| 0x3ff,DAC_VOLUME_1| 0x3ff,DAC_VOLUME_2| 0x3ff,DAC_VOLUME_3| 0x3ff,DAC_VOLUME_4| 0x3ff,DAC_VOLUME_5| 0x3ff,ADC_CONTROL_1| 0x000,ADC_CONTROL_2| 0x180,ADC_CONTROL_3| 0x000 };

#define DAC_CONTROL_10x0000 | 0x000 = 0x0000 #define DAC_CONTROL_20x1000 | 0x000 = 0x1000 #define DAC_VOLUME_00x2000 | 0x3ff = 0x23ff #define DAC_VOLUME_10x3000 | 0x3ff = 0x33ff #define DAC_VOLUME_20x4000 | 0x3ff = 0x43ff #define DAC_VOLUME_30x5000 | 0x3ff = 0x53ff #define DAC_VOLUME_40x6000 | 0x3ff = 0x63ff #define DAC_VOLUME_50x7000 | 0x3ff = 0x73ff#define ADC_CONTROL_10xC000 | 0x000 = 0xC000 #define ADC_CONTROL_20xD000 | 0x180 = 0xD180 #define ADC_CONTROL_30xE000 | 0x000 = 0xE000

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*Veton Kpuska*DMA Start Address RegisterThe Start Address register (DMAx_START_ADDR/MDMA_yy_START_ADDR), shown in Figure 9-2 of ADSP-BF533 Blackfin Processor Hardware Reference, also in the next slide, contains the start address of the data buffer currently targeted for DMA.

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*Veton Kpuska*DMA Count RegisterFor 1D DMA, it specifies the number of elements to read in. For 2D DMA details, see Two-Dimensional DMA on page 9-45 of ADSP-BF533 Blackfin Processor Hardware Reference. A value of 0 in X_COUNT corresponds to 65,536 elements.

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*Veton Kpuska*DMAx Modify RegisterThe Inner Loop Address Increment register (DMAx_X_MODIFY/MDMA_yy_X_MODIFY) contains a signed, twos-complement byte-address increment. In 1D DMA, this increment is the stride that is applied after transferring each element.Note X_MODIFY is specified in bytes, regardless of the DMA transfer size.

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*Veton Kpuska*DMA Configuration Register *pDMA5_CONFIG = WDSIZE_16; WDSIZE_16 = 0x0004; *pDMA5_CONFIG = (*pDMA5_CONFIG | DMAEN); DMAEN = 0x0001*pDMA5_CONFIG = 0x0005

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*Veton Kpuska*SPI_CTL Register Details*pSPI_CTL = TIMOD_DMA_TX | SIZE | MSTR TIMOD_DMA_TX 0x0003 = 0000 0000 0000 0011*pSPI_CTL = *pSPI_CTL | SPE SPE 0x4000 = 0100 0000 0000 0000

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Serial Port Controllers: SPORTEBIU setupFlash setupFIO setupADI1836 - DMASPORT0DMA configurationSPORT IRSDMA SupportEndless loop and processing Flag Interrupts

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*Veton Kpuska*ADSP-BF533 Ez-Kit Lite Audio InterfaceSPISPORT0EBIU

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*Veton Kpuska*Serial Port Controllers (SPORT)The processor has two identical synchronous serial ports, or SPORTs. These support a variety of serial data communications protocols and can provide a direct interconnection between processors in a multiprocessor system.

The serial ports (SPORT0 and SPORT1) provide an I/O interface to a wide variety of peripheral serial devices. SPORTs provide synchronous serial data transfer only; The processor provides asynchronous RS-232 data transfer via the UART.

Each SPORT has one group of pins:primary data, secondary data, clock, and frame sync for transmit and a second set of pins for receive. The receive and transmit functions are programmed separately.

Each SPORT is a full duplex device, capable of simultaneous data transfer in both directions. The SPORTs can be programmed by writing to memory-mapped registers for bit rate,frame sync, and number of bits per word

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*Veton Kpuska*SPORT (cont.)Both SPORTs have the same capabilities and are programmed in the same way.

Each SPORT has its own set of control registers and data buffers.

The SPORTs use frame sync pulses to indicate the beginning of each word or packet, and the bit clock marks the beginning of each data bit.

External bit clock and frame sync are available for the TX and RX buffers.

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*Veton Kpuska*SPORT (cont.)With a range of clock and frame synchronization options, the SPORTs allow a variety of serial communication protocols.

The SPORTs can operate at up to an SCLK/2 clock rate with an externally generated clock, or 1/2 the system clock rate for an internally generated serial port clock.The SPORT external clock must always be less than the SCLK frequency. Independent transmit and receive clocks provide greater flexibility for serial communications.

SPORT clocks and frame syncs can be internally generated by the system or received from an external source.

The SPORTs can operate with a transmission format of LSB first or MSB first, with word lengths selectable from 3 to 32 bits.

They offer selectable transmit modes and optional -law or A-law companding in hardware. SPORT data can be automatically transferred between on-chip and off-chip memories using DMA block transfers.

Additionally, each of the SPORTs offers a TDM (Time-Division-Multiplexed) Multichannel mode.

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*Veton Kpuska*SPORT Features for Audio ExerciseProvides Direct Memory Access transfer to and from memory under DMA Master control. DMA can be autobuffer-based (a repeated, identical range of transfers) or descriptor-based (individual or repeated ranges of transfers with differing DMA parameters).

Executes DMA transfers to and from on-chip memory. Each SPORT can automatically receive and transmit an entire block of data.

Permits chaining of DMA operations for multiple data blocks.

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*Veton Kpuska*SPORT Pins

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*Veton Kpuska*SPORTA SPORT Receives serial data on its DRxPRI and DRxSEC inputs and Transmits serial data on its DTxPRI and DTxSEC outputs. It can receive and transmit simultaneously for full-duplex operation. For transmit: The data bits (DTxPRI and DTxSEC) are synchronous to the transmit clock (TSCLKx).For receive: The data bits (DRxPRI and DRxSEC) are synchronous to the receive clock (RSCLKx). The serial clock is an output if the processor generates it, or an input if the clock is externally generated. Frame synchronization signals RFSx and TFSx are used to indicate the start of a serial data word or stream of serial words.Data to be transmitted is written from an internal processor register to the SPORTs SPORTx_TX register via the peripheral bus. This data is optionally compressed by the hardware and automatically transferred to the TX Shift register. The bits in the Shift register are shifted out on the SPORTs DTxPRI/DTxSEC pin, MSB first or LSB first, Synchronous to the serial clock on the TSCLKx pin.The receive portion of the SPORT accepts data from theDRxPRI/DRxSEC pin synchronous to the serial clock on the RSCLKx pin.When an entire word is received, the data is optionally expanded, thenautomatically transferred to the SPORTs SPORTx_RX register, and theninto the RX FIFO where it is available to the processor.

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*Veton Kpuska*SPORT Generic OperationWriting to a SPORTs SPORTx_TX register readies the SPORT for transmission. The TFS signal initiates the transmission of serial data. Once transmission has begun, each value written to the SPORTx_TX register is transferred through the FIFO to the internal Transmit Shift register. The bits are then sent, beginning with either the MSB or the LSB as specified in the SPORTx_TCR1 register. Each bit is shifted out on the driving edge of TSCLKx. The driving edge of TSCLKx can be configured to be rising or falling.

The SPORT generates the transmit interrupt or requests a DMA transfer as long as there is space in the TX FIFO.

As a SPORT receives bits, they accumulate in an internal receive register. When a complete word has been received, it is written to the SPORT FIFO register and the receive interrupt for that SPORT is generated or A DMA transfer is initiated.

Interrupts are generated differently if DMA block transfers are performed. For information about DMA, see Chapter 9, Direct Memory Access.

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*Veton Kpuska*Generic Multichannel SPORT Connectivity

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*Veton Kpuska*AD1836 and SPORT

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*Veton Kpuska*Initialize.c : Init_Sport0//--------------------------------------------------------------------------//// Function:Init_Sport0 //// //// Description: Configure Sport0 for TDM mode, to transmit/receive data ////to/from the AD1836. Configure Sport for external clocks and ////frame syncs. ////--------------------------------------------------------------------------//void Init_Sport0(void){// Sport0 receive configuration// External CLK, External Frame sync, MSB first// 32-bit data*pSPORT0_RCR1 = RFSR;*pSPORT0_RCR2 = SLEN_32;// Sport0 transmit configuration// External CLK, External Frame sync, MSB first// 24-bit data*pSPORT0_TCR1 = TFSR;*pSPORT0_TCR2 = SLEN_32;// Enable MCM 8 transmit & receive channels*pSPORT0_MTCS0 = 0x000000FF;*pSPORT0_MRCS0 = 0x000000FF;// Set MCM configuration register and enable MCM mode*pSPORT0_MCMC1 = 0x0000;*pSPORT0_MCMC2 = 0x101c;}

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*Veton Kpuska*Setting SPORT ModesSPORT configuration is accomplished by setting bit and field values in configuration registers. Each SPORT must be configured prior to being enabled. Once the SPORT is enabled, further writes to the SPORT Configuration registers are disabled (except for SPORTx_RCLKDIV, SPORTx_TCLKDIV, and Multichannel Mode Channel Select registers).

To change values in all other SPORT Configuration registers, disable the SPORT by clearing TSPEN in SPORTx_TCR1 and/or RSPEN in SPORTx_RCR1.

Each SPORT has its own set of control registers and data buffers. These registers are described in detail in the following sections as they relate to audio LABs.

All control and status bits in the SPORT registers are active high unless otherwise noted.

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*Veton Kpuska*SPORTx_RCR1 and SPORTx_RCR2 RegistersThe main control registers for the receive portion of each SPORT are the Receive Configuration registers:SPORTx_RCR1 and SPORTx_RCR2.

A SPORT is enabled for receive if Bit 0 (RSPEN) of the Receive Configuration 1 register is set to 1. This bit is cleared during either a hard reset or a soft reset, disabling all SPORT reception.

When the SPORT is enabled to receive (RSPEN bit is set), corresponding SPORT Configuration register writes are not allowed except for SPORTx_RCLKDIV and Multichannel Mode Channel Select registers. Writes to disallowed registers have no effect. While the SPORT is enabled, SPORTx_RCR1 is not written except for bit 0 (RSPEN). For example:

write (SPORTx_RCR1, 0x0001) ; /* SPORT RX Enabled */write (SPORTx_RCR1, 0xFF01) ; /* ignored, no effect */write (SPORTx_RCR1, 0xFFF0) ; /* SPORT disabled, SPORTx_RCR1still equal to 0x0000 */

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*Veton Kpuska*SPORTx Receive Configuration 1 Register*pSPORT0_RCR1 = RFSR;RFSR = 0x0000 or 0x0400;

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*Veton Kpuska*SPORTx Receive Configuration 2 Register*pSPORT0_RCR2 = SLEN_32 SLEN_32 = 0x001f;

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*Veton Kpuska*SPORTx_RCR1 and SPORTx_RCR2 RegistersAdditional information for the SPORTx_RCR1 and SPORTxRCR2 Receive Configuration register bits:Receive Enable (RSPEN). This bit selects whether the SPORT is enabled to receive (if set) or disabled (if cleared).

Setting the RSPEN bit turns on the SPORT and causes it to sample data from the data receive pins as well asthe receive bit clock and Receive Frame Sync pins if so programmed.

Setting RSPEN enables the SPORTx receiver, which can generate a SPORTx RX interrupt. For this reason, the code should initialize the ISR and the DMA control registers first, and should be ready to service RX interrupts before setting RSPEN. Setting RSPEN also generates DMA requests if DMA is enabled and data is received.

Set all DMA control registers before setting RSPEN.

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*Veton Kpuska*SPORTx_RCR1 and SPORTx_RCR2 RegistersClearing RSPEN causes the SPORT tostop receiving data; it also shuts down the internal SPORT receive circuitry. In low power applications, battery life can be extended by clearing RSPEN whenever the SPORT is not in use.

Internal Receive Clock Select. (IRCLK). This bit selects the internal receive clock (if set) or external receive clock (if cleared). The RCLKDIV MMR value is not used when an external clock is selected.

Data Formatting Type Select. (RDTYPE). The two RDTYPE bits specify one of four data formats used for single and multichannel operation.

Bit Order Select. (RLSBIT). The RLSBIT bit selects the bit order of the data words received over the SPORTs.

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*Veton Kpuska*SPORTx_RCR1 and SPORTx_RCR2 RegistersSerial Word Length Select. (SLEN). The serial word length (the number of bits in each word received over the SPORTs) is calculated by adding 1 to the value of the SLEN field. The SLEN field can be set to a value of 2 to 31; 0 and 1 are illegal values for this field.

Internal Receive Frame Sync Select. (IRFS). This bit selects whether the SPORT uses an internal RFS (if set) or an external RFS (if cleared).

Receive Frame Sync Required Select. (RFSR). This bit selects whether the SPORT requires (if set) or does not require (if cleared) a Receive Frame Sync for every data word.

Low Receive Frame Sync Select. (LRFS). This bit selects an active low RFS (if set) or active high RFS (if cleared).

Late Receive Frame Sync. (LARFS). This bit configures late frame syncs (if set) or early frame syncs (if cleared).

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*Veton Kpuska*SPORTx_RCR1 and SPORTx_RCR2 RegistersClock Drive/Sample Edge Select. (RCKFE). This bit selects which edge of the RSCLK clock signal the SPORT uses for sampling data, for sampling externally generated frame syncs, and for driving internally generated frame syncs. If set, internally generated frame syncs are driven on the falling edge, and data and externally generated frame syncs are sampled on the rising edge. If cleared, internally generated frame syncs are driven on the rising edge, and data and externally generated frame syncs are sampled on the falling edge.

RxSec Enable. (RXSE). This bit enables the receive secondary side of the serial port (if set).

Stereo Serial Enable. (RSFSE). This bit enables the Stereo Serial operating mode of the serial port (if set). By default this bit is cleared, enabling normal clocking and frame sync.

Left/Right Order. (RRFST). If this bit is set, the right channel is received first in Stereo Serial operating mode. By default this bit is cleared, and the left channel is received first.

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*Veton Kpuska*SPORTx_TCR1 and SPORTx_TCR2 RegistersThe main control registers for the transmit portion of each SPORT are the Transmit Configuration registers, SPORTx_TCR1 and SPORTx_TCR2.A SPORT is enabled for transmit if Bit 0 (TSPEN) of the Transmit Configuration 1 register is set to 1. This bit is cleared during either a hard reset or a soft reset, disabling all SPORT transmission.

When the SPORT is enabled to transmit (TSPEN set), corresponding SPORT Configuration register writes are not allowed except for SPORTx_TCLKDIV and Multichannel Mode Channel Select registers. Writes to disallowed registers have no effect. While the SPORT is enabled, SPORTx_TCR1 is not written except for bit 0 (TSPEN). For example:

write (SPORTx_TCR1, 0x0001) ; /* SPORT TX Enabled */write (SPORTx_TCR1, 0xFF01) ; /* ignored, no effect */write (SPORTx_TCR1, 0xFFF0) ; /* SPORT disabled, SPORTx_TCR1still equal to 0x0000 */

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*Veton Kpuska*SPORTX Transmit Configuration 1 Register: SPORTx_TCR1*pSPORT0_TCR1 = TFSR;TFSR = 0x0000 or 0x0400;

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*Veton Kpuska*SPORTX Transmit Configuration 2 Register: SPORTx_TCR2*pSPORT0_TCR2 = SLEN_32; SLEN_32 = 0x001f;

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*Veton Kpuska*SPORTx_TCR1 and SPORTx_TCR2 RegistersAdditional information for the SPORTx_TCR1 and SPORTx_TCR2 Transmit Configuration register bits includes:

Transmit Enable (TSPEN). This bit selects whether the SPORT is enabled to transmit (if set) or disabled (if cleared). Setting TSPEN causes an immediate assertion of a SPORT TX interrupt, indicating that the TX data register is empty and needs to be filled. This is normally desirable because it allows centralization of the transmit data write code in the TX interrupt service routine (ISR). For this reason, the code should initialize the ISR and be ready to service TX interrupts before setting TSPEN.

Similarly, if DMA transfers will be used, DMA control should be configured correctly before setting TSPEN. Set all DMA control registers before setting TSPEN.Clearing TSPEN causes the SPORT to stop driving data, TSCLK, and frame sync pins; it also shuts down the internal SPORT circuitry. In low power applications, battery life can be extended by clearing TSPEN whenever the SPORT is not in use.

All SPORT control registers should be programmed before TSPEN is set. Typical SPORT initialization code first writes all control registers, including DMA control if applicable. The last step in the code is to write SPORTx_TCR1 with all of the necessary bits, including TSPEN.

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*Veton Kpuska*SPORTx_TCR1 and SPORTx_TCR2 RegistersInternal Transmit Clock Select. (ITCLK). This bit selects the internal transmit clock (if set) or the external transmit clock on the TSCLK pin (if cleared). The TCLKDIV MMR value is not used when an external clock is selected.

Data Formatting Type Select. The two TDTYPE bits specify data formats used for single and multichannel operation.

Bit Order Select. (TLSBIT). The TLSBIT bit selects the bit order of the data words transmitted over the SPORT.

Serial Word Length Select. (SLEN). The serial word length (the number of bits in each word transmitted over the SPORTs) is calculated by adding 1 to the value of the SLEN field: Serial Word Length = SLEN + 1;

The SLEN field can be set to a value of 2 to 31; 0 and 1 are illegal values for this field. Three common settings for the SLEN field are 15, to transmit a full 16-bit word; 7, to transmit an 8-bit byte; and 23, to transmit a 24-bit word. The processor can load 16- or 32-bit values into the transmit buffer via DMA or an MMR write instruction; the SLEN field tells the SPORT how many of those bits to shift out of the register over the serial link. The serial port transfers bits [SLEN:0] from the transmit buffer.

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*Veton Kpuska*SPORTx_TCR1 and SPORTx_TCR2 RegistersInternal Transmit Frame Sync Select. (ITFS). This bit selects whether the SPORT uses an internal TFS (if set) or an external TFS (if cleared).

Transmit Frame Sync Required Select. (TFSR). This bit selects whether the SPORT requires (if set) or does not require (if cleared) a Transmit Frame Sync for every data word.

Data-Independent Transmit Frame Sync Select. (DITFS). This bit selects whether the SPORT generates a data-independent TFS (sync at selected interval) or a data-dependent TFS (sync when data is present in SPORTx_TX) for the case of internal frame sync select (ITFS = 1). The DITFS bit is ignored when external frame syncs are selected.

The frame sync pulse marks the beginning of the data word. If DITFS is set, the frame sync pulse is issued on time, whether the SPORTx_TX register has been loaded or not; if DITFS is cleared, the frame sync pulse is only generated if the SPORTx_TX data register has been loaded. If the receiver demands regular frame sync pulses, DITFS should be set, and the processor should keep loading the SPORTx_TX register on time. If the receiver can tolerate occasional late frame sync pulses, DITFS should be cleared to prevent the SPORT from transmitting old data twice or transmitting garbled data if the processor is late in loading the SPORTx_TX register.

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*Veton Kpuska*SPORTx_TCR1 and SPORTx_TCR2 RegistersLow Transmit Frame Sync Select. (LTFS). This bit selects an active low TFS (if set) or active high TFS (if cleared).

Late Transmit Frame Sync. (LATFS). This bit configures late frame syncs (if set) or early frame syncs (if cleared).

Clock Drive/Sample Edge Select. (TCKFE). This bit selects which edge of the TCLKx signal the SPORT uses for driving data, for driving internally generated frame syncs, and for sampling externally generated frame syncs. If set, data and internally generated frame syncs are driven on the falling edge, and externally generated frame syncs are sample on the rising edge. If cleared, data and internally generated frame syncs are driven on the rising edge, and externally generated frame syncs are sampled on the falling edge.

TxSec Enable. (TXSE). This bit enables the transmit secondary side of the serial port (if set).

Stereo Serial Enable. (TSFSE). This bit enables the Stereo Serial operating mode of the serial port (if set). By default this bit is cleared, enabling normal clocking and frame sync.

Left/Right Order. (TRFST). If this bit is set, the right channel is transmitted first in Stereo Serial operating mode. By default this bit is cleared, and the left channel is transmitted first.

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*Veton Kpuska*Data Word FormatsThe format of the data words transferred over the SPORTs is configured by the combination of:transmit SLEN and receive SLEN;RDTYPE; TDTYPE; RLSBIT; andTLSBIT bits of the SPORTx_TCR1, SPORTx_TCR2, SPORTx_RCR1, and SPORTx_RCR2 registers.

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*Veton Kpuska*SPORTs Multichannel OperationIn Multichannel mode, RSCLK can either be provided externally or generated internally by the SPORT, and it is used for both transmit and receive functions.

Leave TSCLK disconnected if the SPORT is used only in multichannel mode.

If RSCLK is externally or internally provided, it will be internally distributed to both the receiver and transmitter circuitry.

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*Veton Kpuska*SPORTs Multichannel OperationImportant Note:

The SPORT Multichannel Transmit Select register and the SPORT Multichannel Receive Select register must be programmed before enabling SPORTx_TX or SPORTx_RX operation for Multichannel Mode.

This is especially important in DMA data unpacked mode, since SPORT FIFO operation begins immediately after RSPEN and TSPEN are set, enabling both RX and TX.

The MCMEN bit (in SPORTx_MCMC2) must be enabled prior to enabling SPORTx_TX or SPORTx_RX operation. When disabling the SPORT from multichannel operation, first disable TXEN and then disable RXEN.

Note both TXEN and RXEN must be disabled before reenabling. Disabling only TX or RX is not allowed.

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*Veton Kpuska*SPORTs Multichannel Operation SPORTx_MTCSn Registers

The Multichannel Selection registers are used to enable and disable individual channels. The four SPORTx Multichannel Transmit Select registers (SPORTx_MTCSn) specify the active transmit channels.

There are four registers, each with 32 bits, corresponding to the 128 channels: Setting a bit enables that channel so that the serial port selects that word for transmit from the multiple word block of data. For example, setting bit 0 selects word 0, setting bit 12 selects word 12, and so on.

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*Veton Kpuska*SPORTs Multichannel OperationSetting a particular bit in a SPORTx_MTCSn register causes the serial port to transmit the word in that channels position of the datastream. Clearing the bit in the SPORTx_MTCSn register causes the serial ports data transmit pin to three-state during the time slot of that channel.

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*Veton Kpuska*SPORTs Multichannel OperationSPORTx_MRCSn Registers

The Multichannel Selection registers are used to enable and disable individual channels. The SPORTx Multichannel Receive Select registers (SPORTx_MRCSn) specify the active receive channels.

There are four registers, each with 32 bits, corresponding to the 128 channels. Setting a bit enables that channel so that the serial port selects that word for receive from the multiple word block of data. For example, setting bit 0 selects word 0, setting bit 12 selects word 12, and so on.

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*Veton Kpuska*SPORTx Multichannel Transmit Select Registers*pSPORT0_MTCS0 = 0x000000FF;

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*Veton Kpuska*SPORTx Multichannel Receive Select Registers*pSPORT0_MRCS0 = 0x000000FF;

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*Veton Kpuska*SPORTx_MCMCn RegistersSPORTx_MCMCn RegistersThere are two SPORTx Multichannel Configuration registers (SPORTx_MCMCn) for each SPORT.

The SPORTx_MCMCn registers are used to configure the multichannel operation of the SPORT. The two control registers are shown below.

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*Veton Kpuska*SPORTx_MCMCn Registers*pSPORT0_MCMC1 = 0x0000;Desired Window Size = 8

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*Veton Kpuska*SPORTx_MCMCn Registers*pSPORT0_MCMC2 = 0x101c; 0x101c = 0001 0000 0001 1100

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Initialize.cEBIU setupFlash setupFIO setupADI1836 - DMASPORT0DMA ConfigurationSPORT IRSDMA SupportEndless loop and processing Flag Interrupts

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DMA ConfigurationInit_DMA()

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*Veton Kpuska*Init_DMA()//--------------------------------------------------------------------------//// Function:Init_DMA //// //// Description: Initialize DMA1 in autobuffer mode to receive and DMA2 in ////autobuffer mode to transmit ////--------------------------------------------------------------------------//void Init_DMA(void){// Set up DMA1 to receive// Map DMA1 to Sport0 RX*pDMA1_PERIPHERAL_MAP = 0x1000;// Configure DMA1// 32-bit transfers, Interrupt on completion, Autobuffer mode*pDMA1_CONFIG = WNR | WDSIZE_32 | DI_EN | FLOW_1;// Start address of data buffer*pDMA1_START_ADDR = iRxBuffer1;// DMA inner loop count*pDMA1_X_COUNT = 8;// Inner loop address increment*pDMA1_X_MODIFY= 4;// Set up DMA2 to transmit// Map DMA2 to Sport0 TX*pDMA2_PERIPHERAL_MAP = 0x2000;// Configure DMA2// 32-bit transfers, Autobuffer mode*pDMA2_CONFIG = WDSIZE_32 | FLOW_1;// Start address of data buffer*pDMA2_START_ADDR = iTxBuffer1;// DMA inner loop count*pDMA2_X_COUNT = 8;// Inner loop address increment*pDMA2_X_MODIFY= 4;}

Setting up DMA1-SPORT0 as Input/Receive Channel

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*Veton Kpuska*Initialize.c : Init_DMA()//--------------------------------------------------------------------------//// Function:Init_DMA //// //// Description: Initialize DMA1 in autobuffer mode to receive and DMA2 in ////autobuffer mode to transmit ////--------------------------------------------------------------------------//void Init_DMA(void){// Set up DMA1 to receive// Map DMA1 to Sport0 RX*pDMA1_PERIPHERAL_MAP = 0x1000;// Configure DMA1// 32-bit transfers, Interrupt on completion, Autobuffer mode*pDMA1_CONFIG = WNR | WDSIZE_32 | DI_EN | FLOW_1;// Start address of data buffer*pDMA1_START_ADDR = iRxBuffer1;// DMA inner loop count*pDMA1_X_COUNT = 8;// Inner loop address increment*pDMA1_X_MODIFY= 4;// Set up DMA2 to transmit// Map DMA2 to Sport0 TX*pDMA2_PERIPHERAL_MAP = 0x2000;// Configure DMA2// 32-bit transfers, Autobuffer mode*pDMA2_CONFIG = WDSIZE_32 | FLOW_1;// Start address of data buffer*pDMA2_START_ADDR = iTxBuffer1;// DMA inner loop count*pDMA2_X_COUNT = 8;// Inner loop address increment*pDMA2_X_MODIFY= 4;}

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*Veton Kpuska*DMA Configuration RegisterThe DMA Configuration register (DMAx_CONFIG/MDMA_yy_CONFIG), shown in Figure 9-3 of ADSP-BF533 Blackfin Processor Hardware Reference, also in this slide is used to set up DMA parameters and operating modes.*pDMA1_CONFIG = WNR | WDSIZE_32 | DI_EN | FLOW_1;

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*Veton Kpuska*DMA Start Address RegisterThe Start Address register (DMAx_START_ADDR/MDMA_yy_START_ADDR), shown in Figure 9-2 of ADSP-BF533 Blackfin Processor Hardware Reference, also in the next slide, contains the start address of the data buffer currently targeted for DMA.*pDMA1_START_ADDR = iRxBuffer1;

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*Veton Kpuska*DMA Count RegisterFor 1D DMA, it specifies the number of elements to read in. For 2D DMA details, see Two-Dimensional DMA on page 9-45 of ADSP-BF533 Blackfin Processor Hardware Reference. A value of 0 in X_COUNT corresponds to 65,536 elements.*pDMA1_X_COUNT = 8;

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*Veton Kpuska*DMAx Modify RegisterThe Inner Loop Address Increment register (DMAx_X_MODIFY/MDMA_yy_X_MODIFY) contains a signed, twos-complement byte-address increment. In 1D DMA, this increment is the stride that is applied after transferring each element.Note X_MODIFY is specified in bytes, regardless of the DMA transfer size.*pDMA1_X_MODIFY= 4;

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*Veton Kpuska*Init_DMA()//--------------------------------------------------------------------------//// Function:Init_DMA //// //// Description: Initialize DMA1 in autobuffer mode to receive and DMA2 in ////autobuffer mode to transmit ////--------------------------------------------------------------------------//void Init_DMA(void){// Set up DMA1 to receive// Map DMA1 to Sport0 RX*pDMA1_PERIPHERAL_MAP = 0x1000;// Configure DMA1// 32-bit transfers, Interrupt on completion, Autobuffer mode*pDMA1_CONFIG = WNR | WDSIZE_32 | DI_EN | FLOW_1;// Start address of data buffer*pDMA1_START_ADDR = iRxBuffer1;// DMA inner loop count*pDMA1_X_COUNT = 8;// Inner loop address increment*pDMA1_X_MODIFY= 4;// Set up DMA2 to transmit// Map DMA2 to Sport0 TX*pDMA2_PERIPHERAL_MAP = 0x2000;// Configure DMA2// 32-bit transfers, Autobuffer mode*pDMA2_CONFIG = WDSIZE_32 | FLOW_1;// Start address of data buffer*pDMA2_START_ADDR = iTxBuffer1;// DMA inner loop count*pDMA2_X_COUNT = 8;// Inner loop address increment*pDMA2_X_MODIFY= 4;}

Setting up DMA2-SPORT0 as Output/Transmit Channel

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*Veton Kpuska*DMA Configuration RegisterThe DMA Configuration register (DMAx_CONFIG/MDMA_yy_CONFIG), shown in Figure 9-3 of ADSP-BF533 Blackfin Processor Hardware Reference, also in this slide is used to set up DMA parameters and operating modes.*pDMA2_CONFIG = WDSIZE_32 | FLOW_1;

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*Veton Kpuska*DMA Start Address RegisterThe Start Address register (DMAx_START_ADDR/MDMA_yy_START_ADDR), shown in Figure 9-2 of ADSP-BF533 Blackfin Processor Hardware Reference, also in the next slide, contains the start address of the data buffer currently targeted for DMA.*pDMA2_START_ADDR = iTxBuffer1;

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*Veton Kpuska*DMA Count RegisterFor 1D DMA, it specifies the number of elements to read in. For 2D DMA details, see Two-Dimensional DMA on page 9-45 of ADSP-BF533 Blackfin Processor Hardware Reference. A value of 0 in X_COUNT corresponds to 65,536 elements.*pDMA2_X_COUNT = 8;

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Initialize.cEBIU setupFlash setupFIO setupADI1836 - DMASPORT0DMA ConfigurationSPORT IRSEnable DMA SupportEndless loop and processing Flag Interrupts

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DMA ConfigurationInit_DMA()

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*Veton Kpuska*DMAx Modify RegisterThe Inner Loop Address Increment register (DMAx_X_MODIFY/MDMA_yy_X_MODIFY) contains a signed, twos-complement byte-address increment. In 1D DMA, this increment is the stride that is applied after transferring each element.Note X_MODIFY is specified in bytes, regardless of the DMA transfer size.*pDMA2_X_MODIFY= 4;

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*Veton Kpuska*Initialize.c : Enable_DMA_Sport()//--------------------------------------------------------------------------//// Function:Enable_DMA_Sport //// //// Description:Enable DMA1, DMA2, Sport0 TX and Sport0 RX ////--------------------------------------------------------------------------//void Enable_DMA_Sport0(void){// enable DMAs*pDMA2_CONFIG= (*pDMA2_CONFIG | DMAEN);*pDMA1_CONFIG= (*pDMA1_CONFIG | DMAEN);// enable Sport0 TX and RX*pSPORT0_TCR1 = (*pSPORT0_TCR1 | TSPEN);*pSPORT0_RCR1 = (*pSPORT0_RCR1 | RSPEN);}

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*Veton Kpuska*SPORTX Transmit Configuration 1 Register: SPORTx_TCR1*pSPORT0_TCR1 = TFSR; TFSR = 0x0000; *pSPORT0_TCR1 = (*pSPORT0_TCR1 | TSPEN);

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*Veton Kpuska*SPORTx Receive Configuration 1 Register : SPORTx_RCR1*pSPORT0_RCR1 = RFSR; RFSR = 0x0000; *pSPORT0_RCR1 = (*pSPORT0_RCR1 | RSPEN);

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Initialize.cEBIU setupFlash setupFIO setupADI1836 - DMASPORT0DMA ConfigurationSPORT IRSEnable DMA SupportEndless loop and processing Flag Interrupts

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Event Controller for Interrupts and Exceptions

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*Veton Kpuska*Event ControllerThe Event Controller of the processor manages five types of activities or events:EmulationResetNonmaskable interrupts (NMI)ExceptionsInterrupts (11)

Note the word event describes all f

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