Microcomputer & Interfacing Lecture 3 The 8086 Instruction sets BY: Tsegamlak Terefe.

Microcomputer & InterfacingLecture 3

The 8086 Instruction sets

BY: Tsegamlak Terefe

Objective

Introduction Introduction to an instruction

Instruction set of 8086 Addressing mode


Introduction

Programs in microprocessors are stored in successive memory locations for fetching followed by decoding and execution in general.

There are in general three levels of programming languages.

Machine Language Assembly Language

High Level Language


4

Machine Language

These are the binary codes for the instructions you want the microcomputer to execute

It is hard or impossible for a programmer to write code in machine language, because it requires memorizing all the instructions in binary form and soon the programming will Become difficult.

11101001000000000101000

Introduction


5

Assembly Language

Uses two, three, or four letter mnemonics to represent each instruction type

The letters in an assembly language mnemonic are usually initials or a short form of the English word(s) for the operation performed by the instruction

e.g., SUB for subtract , XOR for Exclusive OR ,ROR for rotate Wright , etc

Assembly language program has to be translated to machine language so that it can be loaded into memory and run – This is done by the assembler

Introduction


6

High-Level Languages

These languages use program statements which are even more English-like than those of assembly language

e.g. BASIC, C, C++, Java, ...

Each high-level statement may represent many machine code instructions

An interpreter (compiler) program is used to translate higher-level language statements to machine codes, which can be loaded into memory and executed.

Introduction


7

An instruction will have two major parts

An opcode and an address/operand to store the result after execution or to operate on respectively.

Opcode : is the operation code which is decoded by the processor to activate the necessary circuitry for the execution of an instruction.

Instructions


Opcode Address (Operands)

8

The 8086 microprocessor have variable length instructions ranging from 8 bit to 48 bits.

Instructions


9


10

For Example lets take the following 16 bit instruction 8BEC.

8BEC= 1000 1011 1110 1100 The first six bits will tell us the opcode 100010= MOV The next two bits tell us D=1=> Data will move to REG from R/M W=1=> Data is 16 bit in size on the next byte MOD=11 => data is transferred b/n two registers or R/M is register REG=101 The first register involved is BP R/M=100 The second register involved is SP

Hence the assembly equivalence of this machine code will be MOV BP,SP

Instructions


11

Now that we got a grip of what an instruction look like in 8086 we can generalize the instruction sets (opcode) in to six general group.

Data transfer instructions Arithmetic instructionsBit manipulation instructionsString manipulation instructionsControl transfer instructionsProcessor control instructions

Instructions


12

Now that we got a grip of what an instruction look like in 8086 we can generalize the instruction sets (opcode) in to six general group.

Data transfer instructions Arithmetic instructionsBit manipulation instructionsString manipulation instructionsControl transfer instructionsProcessor control instructions

Instruction Sets


13

Used to transfer data from source operand to destination operand

Memory to register e.g. MOV AX, [0005h] (AX←[0005h]) Register to memory e.g. PUSH AL Immediate to memory/register e.g. MOV AH, 09h I/O device to register e.g. IN AX, 4 Register to I/O device e.g. OUT AL, 2

All the store, move, load, exchange, input and output instructions belong to this category

MOV , PUSH, POP , XCHG, XLAT, IN, OUT, LEA, PUSHF, POPF,LAHF,….

Data transfer instructions


14

Perform arithmetic operations

Addition e.g. ADD, ADC, INC, AAA, Subtraction e.g. SUB, SBB, DEC, CMP Multiplication e.g. MUL, IMUL Division e.g. DIV, IDIV

e.g. ADD AL, 5 (AL←AL+5)MUL BL (AX ←AL*BL)MUL BX (DX:AX ←AX*BX)

Arithmetic Instructions


15

Bit Manipulation Instruction


Logical instructionsNOT, AND, OR, XOR Shift instructionsSHL, SHR, SAL, SAR Rotate instructionsROL, ROR, RCL, RCR

e.g. MOV AL, 1Ch (AL←1Ch (00011100b))ROR AL, 1 (rotate AL one bit to the right) (AL = 00001110b)

Byte/WordCF

Byte/WordCF

RCL

RCR

16

String Manipulation Instructions


A string is a series of bytes or a series of words in sequential memory locations. It often consists of ASCII character codese.g. LODSB – Load byte at DS: [SI] into AL. Update SI STOSW – Store word in AX into ES:[DI]. Update DI CMPSB – Compare bytes: ES:[DI] from DS:[SI]

17

Control Transfer Instructions


These instructions are used to tell the processor to start fetching instructions from some new address, rather than continuing in sequence Unconditional transfer instructions e.g. CALL, RET, JMP Conditional transfer instructions e.g. JE, JG, JGE, JL, JLE, JZ Iteration control instructions e.g. LOOP, LOOPE, JCXZ Interrupt instructions e.g. INT, IRETe.g. SUB AX, 32JZ label …label: MOV BX, 10

AX=AX-32;If(AX==0)

{BX=10;

}

18

Processor Control Instructions


Set/clear flags, control the operation of the processorFlag instructions

e.g. STC – set carry flagExternal hardware synchronization instructions

e.g. WAIT - Do nothing until signal on the TEST pin is lowNo operation instructions e.g. NOP

19

Addressing Modes


Addressing mode: Describe the types of operands and the way they are accessed for executing an instruction

The operand part of an instructions are accessed from a memory location or a register in various mode of addressing.

The 8086 microprocessor have the following addressing modes.

20

Addressing Modes


ImmediateDirect

RegisterRegister Indirect

IndexedRegister Relative Based IndexedRelative Based Indexed

21

Immediate Addressing


Immediate data is a part of instruction, and appears inthe form of successive byte(s)

e.g. MOV AX, 0005H (AX←0005H)

Here, 0005H is the immediate data. The immediatedata may be 8-bit or 16-bit in size.

22

Direct Addressing


In the direct addressing mode, a 16-bit memory address (offset) is directly specified in the instruction

e.g. MOV AX, [5000H ] (AX←[DS:5000H])

Here, data resides in a memory location in the datasegment, whose effective address may be computedusing 5000H as the offset address and content of DSas segment address.

23

Register Addressing


In register addressing mode, the data is stored in a register and it is referred using the particular register

All the registers, except IP, may be used in this mode

e.g. MOV AX, BX (AX←BX)

Here, data is transferred from register BX to register AX

24

Register Indirect Addressing


Sometimes, the address of the memory location, which contains data or operand, is determined in an indirect way, using the offset registers

The offset address of data is in either BX, SI or DI registers. The default segment is either DS or ES.

e.g. MOV AX, [BX ] (AX←[DS:BX])

Here, data is present in a memory location in DS whose offset address is in BX.

25

Indexed Addressing


Offset of the operand is stored in one of the index registers (SI and DI). DS and ES are the default segments for SI and DI respectively

This mode is a special case of register indirect addressing mode

e.g. MOV AX, [SI ] (AX←[DS:SI])

Here, data is present in a memory location in DS whose offset address is in SI.

26

Base Indexed Addressing


The effective address of data is formed by adding content of a base register (BX or BP) to the content of an index register (SI or DI)

e.g. MOV AX, [BX ][SI] (AX←[DS:BX+SI])

27

Relative Base Indexed Addressing


The effective address is formed by adding an 8 or 16-bit displacement with the sum of contents of any one of the base registers (BX or BP) and any one of the index registers (SI or DI), in a default segment

e.g. MOV AX, 50H[BX ][SI] (AX←[DS:BX+SI+50])

28

Summary of addressing modes


29

Next Lecture


Programming the 8086 Emu8086

30

Additional Reference


Dr Manoj’s handout, chapter 2 The Intel Microprocessors, Barry B.

Microcomputer & Interfacing Lecture 3 The 8086 Instruction sets BY: Tsegamlak Terefe.

Documents