Department of Instrumentation & Control Engineering, MIT, Manipal Lecture #07 Basics of CMOS 1
Jun 24, 2015
Department of Instrumentation & Control Engineering, MIT, Manipal
Lecture #07
Basics of CMOS
1
Department of Instrumentation & Control Engineering, MIT, Manipal
Contents
1. Introduction – Transistor Types
2. Silicon Lattice
3. Dopants
4. p n Junction Diodes
5. n MOS Transistors
6. p MOS Transistors
7. Transistors as Switches
8. CMOS Inverters and NAND Gates
9. Compound Gates
2
Introduction – Transistor Types
3
• Bipolar transistors
– npn or pnp silicon structure
– Small current into very thin base layer controls large currents between emitter and collector
– Base currents limit integration density (power dissipation issue)
• Metal Oxide Semiconductor Field Effect Transistors
– nMOS and pMOS MOSFETs
– Voltage applied to insulated gate controls current between source and drain
– Low power allows very high integration (ideally zero static power)
S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
Silicon Lattice
4
• Transistors are built on a silicon substrate
• Silicon is a Group IV material
• Forms crystal lattice with bonds to four neighbours
S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
Si SiSi
Si SiSi
Si SiSi
Dopants
5
• Silicon is a semiconductor
• Pure silicon has no free carriers and conducts poorly
• Adding dopants increases the conductivity
• Group V (Arsenic): extra electron (n-type)
• Group III (Boron): missing electron, called hole (p-type)
S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
As SiSi
Si SiSi
Si SiSi
B SiSi
Si SiSi
Si SiSi
-
+
+
-
p n Junctions
6
• A junction between p-type and n-type semiconductor forms adiode.
• Current flows only in one direction
S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
p-type n-type
anode cathode
nMOS Transistors
7
• Four terminals: gate, source, drain, body
• Gate – oxide – body stack looks like a capacitor
– Gate and body are conductors
– SiO2 (oxide) is a very good insulator
– Called metal – oxide – semiconductor (MOS) capacitor
S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
nMOS Operation
8
• Body is commonly tied to ground (0 V)
• When the gate is at a low voltage:
– P-type body is at low voltage
– Source-body and drain-body diodes are OFF
– No current flows, transistor is OFF
S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+D
0
S
nMOS Operation Contd…
9
• When the gate is at a high voltage:
– Positive charge on gate of MOS capacitor
– Negative charge attracted to body
– Inserts a channel under gate to n-type
– Now current can flow through n-type silicon from source
through channel to drain, transistor is ON
S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+D
1
S
pMOS Operation
10
• Similar, but doping and voltages reversed
– Body tied to high voltage (VDD)
– Gate low: transistor ON
– Gate high: transistor OFF
– Bubble indicates inverted behavior
S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
Power Supply Voltage
11
• GND = 0 V
• In 1980’s, VDD = 5V
• VDD has decreased in modern processes due to scaling
– High VDD would damage modern tiny transistors
– Lower VDD saves power (Dynamic power is proportional to
C.VDD2.f.a)
• VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …
S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
Transistors as Switches
12
• We can view MOS transistors as electrically controlled
switches
• Voltage at gate controls path from source to drain
S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
g
s
d
g = 0
s
d
g = 1
s
d
g
s
d
s
d
s
d
nMOS
pMOS
OFFON
ONOFF
CMOS Inverter
13S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
A Y
0
1
VDD
A Y
GNDA Y
CMOS Inverter
14S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
A Y
0 1
1 0
VDD
A=0 Y=1
GND
OFF
ON
A Y
CMOS Inverter
15S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
A Y
0 1
1 0
VDD
A=1 Y=0
GND
ON
OFF
A Y
CMOS NAND Gate
16S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
A B Y
0 0
0 1
1 0
1 1
A
B
Y
CMOS NAND Gate
17S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
A B Y
0 0 1
0 1
1 0
1 1
A=0
B=0
Y=1
OFF
ON ON
OFF
CMOS NAND Gate
18S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
A B Y
0 0 1
0 1 1
1 0
1 1
A=0
B=1
Y=1
OFF
OFF ON
ON
CMOS NAND Gate
19S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
A B Y
0 0 1
0 1 1
1 0 1
1 1
A=1
B=0
Y=1
ON
ON OFF
OFF
CMOS NAND Gate
20S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
Series and Parallel
21
• nMOS: 1 = ON
• pMOS: 0 = ON
• Series: both must be ON
• Parallel: either can be ON
S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
(a)
a
b
a
b
g1
g2
0
0
a
b
0
1
a
b
1
0
a
b
1
1
OFF OFF OFF ON
(b)
a
b
a
b
g1
g2
0
0
a
b
0
1
a
b
1
0
a
b
1
1
ON OFF OFF OFF
(c)
a
b
a
b
g1 g2 0 0
OFF ON ON ON
(d) ON ON ON OFF
a
b
0
a
b
1
a
b
11 0 1
a
b
0 0
a
b
0
a
b
1
a
b
11 0 1
a
b
g1 g2
Compound Gates
22
• Compound gates can do any inverting function
• Ex:
S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
(AND-AND-OR-INVERT, AOI22)Y A B C D= +i i
A
B
C
D
A
B
C
D
A B C DA B
C D
B
D
YA
CA
C
A
B
C
D
B
D
Y
(a)
(c)
(e)
(b)
(d)
(f)
Compound Gates
23
• O3AI
• Ex:
S.Meenatchisundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
( )Y A B C D= + + i
A B
Y
C
D
DC
B
A