-
MIC4540419V 5A Ultra-Low Profile DC-to-DC Power Module
Features• Input Voltage Range: 4.5V to 19V• Output Current: Up
to 5A• 82% Peak Efficiency at 12 VIN, 0.9 VOUT• Pin-Selectable
Output Voltages: 0.7V, 0.8V, 0.9V,
1.0V, 1.2V, 1.5V, 1.8V, 2.5V, 3.3V• ±1% Output Voltage Accuracy•
Supports Safe Pre-Biased Start-up• Pin-Selectable Current Limit•
Pin-Selectable Switching Frequency• Internal Soft Start• Thermal
Shutdown• Hiccup Mode Short-Circuit Protection• Available in a
54-Lead 6 mm x 10 mm QFN
Package• Ultra-Low Profile: 2.0 mm Height• -40°C to +125°C
Junction Temperature Range
Applications• Servers, Data Storage, Routers and Base Stations•
FPGAs, DSP and Low-Voltage ASIC Power
General DescriptionThe MIC45404 device is an ultra-low profile,
synchro-nous step-down regulator module, featuring a unique2.0 mm
height. The module incorporates a DC-to-DCregulator, bootstrap
capacitor, high-frequency inputcapacitor and an inductor in a
single package. Themodule pinout is optimized to simplify the
PrintedCircuit Board (PCB) layout process.
This highly integrated solution expedites systemdesign and
improves product time to market. The inter-nal MOSFETs and inductor
are optimized to achievehigh efficiency at low output voltage. Due
to the fullyoptimized design, MIC45404 can deliver up to 5Acurrent
with a wide input voltage range of 4.5V to 19V.
The MIC45404 is available in a 54-lead 6 mm x10 mm x 2.0 mm QFN
package with a junction operat-ing temperature range from -40C to
+125C, whichmakes an excellent solution for systems in which
PCBreal-estate and height are important limiting factors,and air
flow is restricted.
Typical Application
MIC45404 12V 5A DC-to-DC Converter
VINOUT
VIN 4.5V to 19V
FREQ
VDDA
VOSET1
PG
GND
GND
VOSET0
COMP
EN/DLY
OUTSNS
MIC45404
VDDA
Power-GoodEnable
VDDA
VDDA
OutputVoltage
Selection
VDDAFrequency
Selection
ILIM
VDDACurrent Limit
Selection
VOUT
2015 Microchip Technology Inc. DS20005478A-page 1
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MIC45404
Package Types
Functional Diagram
MIC454046 mm x 10 mm QFN*
(Bottom View)
8
26
22
24
23
3
373534
25
47
46
7
KEEPOUT
GND
GND
BS
T
PG
VD
DA
LX
OU
TGND
21
KEEPOUT
48
38
4 12
AGND
VO
SE
T1
NC
41 43
53
OU
TSN
S
SN
S
33
VO
SE
T0LX
44 45
VD
DP
313029 3252
3628
20
9
LX LXLX LXLX LXLX LX LX
OUT
OUT
12
OU
T13
OU
T14
OU
T15
OU
T16
OU
T17
OU
T18
OU
T19
GN
DV
IN
VIN
27LXLX
39 40
LX
KE
EP
OU
T
BS
T42
NC
ILIM
49 FREQ
50
51 GND
COMP
54 OUTSNS
KE
EP
OU
T10
OU
T11 6
GN
D_E
XT
5G
ND
_EX
T
MIC45404YMP
GND_EP
* Includes Exposed Thermal Pad (EP); see Table 3-1.
LX
BST
ILIM
FREQ
VDDA
VOSET1
PG
AGND
VOSET0
COMP
EN/DLYOUTSNS
VIN
PGNDVDDP
PWMRegulator
100 nF
47 pF
LX
BST
VOSET1
AGND
VOSET0
GND_EP
OUTSNS
GND
COMP
OUT
ILIM
FREQ
VDDA
PGEN/DLY
VIN
VDDP
GND_EXT
VDDP
LDO
VIN
DS20005478A-page 2 2015 Microchip Technology Inc.
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MIC45404
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†VIN to AGND
................................................................................................................................................
-0.3V to +20V
VDDP, VDDA to
AGND.....................................................................................................................................
-0.3V to +6V
VDDP to VDDA
............................................................................................................................................
-0.3V to +0.3V
VOSETX, FREQ, ILIM, to
AGND....................................................................................................................
-0.3V to +6V
BST to
LX.....................................................................................................................................................
-0.3V to +6V
BST to AGND
..............................................................................................................................................
-0.3V to +26V
EN/DLY to
AGND......................................................................................................................
-0.3V to VDDA + 0.3V, +6V
PG to AGND
..................................................................................................................................................
-0.3V to +6V
COMP, OUTSNS to AGND
.......................................................................................................
-0.3V to VDDA + 0.3V, +6V
AGND to GND
............................................................................................................................................
-0.3V to +0.3V
Junction Temperature
..........................................................................................................................................
+150°C
Storage Temperature (TS)
......................................................................................................................
-65°C to +150°C
Lead Temperature (soldering, 10s)
........................................................................................................................
260°C
ESD Rating(1)
HBM
...........................................................................................................................................................................
2kV
MM
...........................................................................................................................................................................
150V
CDM.......................................................................................................................................................................
1500V
Note 1: Devices are ESD-sensitive. Handling precautions are
recommended. Human body model, 1.5 k in serieswith 100 pF.
Operating Ratings(1)
Supply Voltage (VIN)
.....................................................................................................................................
4.5V to 19V
Externally Applied Analog and Drivers Supply Voltage (VIN = VDDA
= VDDP) .............................................. 4.5V to
5.5V
Enable Voltage
(EN/DLY)...............................................................................................................................
0V to VDDAPower Good (PG) Pull-up Voltage (VPU_PG)
................................................................................................
0V to 5.5V
Output Current
.............................................................................................................................................................
5A
Junction Temperature (TJ)
.....................................................................................................................
-40°C to +125°C
Note 1: The device is not ensured to function outside the
operating range.
† Notice: Stresses above those listed under “Maximum Ratings”
may cause permanent damage to the device. This isa stress rating
only and functional operation of the device at those or any other
conditions above those indicated inthe operational sections of this
specification is not intended. Exposure to maximum rating
conditions for extendedperiods may affect device reliability.
2015 Microchip Technology Inc. DS20005478A-page 3
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MIC45404
ELECTRICAL CHARACTERISTICS(1)
Electrical Specifications: unless otherwise specified, VIN =
12V; CVDDA= 2.2 µF, TA = +25°C. Boldface values indicate -40°C TJ
+125°C.
Parameter Symbol Min. Typ. Max. Units Test Conditions
VIN SupplyInput Range VIN 4.5 — 19 VDisable Current IVINQ — 33
60 µA EN/DLY = 0VOperating Current IVINOp — 5.35 8.5 mA EN/DLY >
1.28V,
OUTSNS = 1.15 x VOUT(NOM), no switching
VDDA 5V SupplyOperating Voltage VDDA 4.8 5.1 5.4 V EN/DLY >
0.58V,
IVDDA = 0 mA to 10 mADropout Operation 3.6 3.75 — V VIN = 4.5V,
EN/DLY > 0.58V,
IVDDA = 10 mAVDDA Undervoltage LockoutVDDA UVLO Rising UVLO_R
3.1 3.5 3.9 V VDDA Rising, EN/DLY > 1.28VVDDA UVLO Falling
UVLO_F 2.87 3.2 3.45 V VDDA Falling, EN/DLY > 1.28VVDDA UVLO
Hysteresis UVLO_H — 300 — mVEN/DLY ControlLDO Enable Threshold
EN_LDO_R — 515 600 mV Turns on VDDA LDOLDO Disable Threshold
EN_LDO_F 450 485 — mV Turns off VDDA LDOLDO Threshold Hysteresis
EN_LDO_H — 30 — mVEN/DLY Rising Threshold EN_R 1.14 1.21 1.28 V
Initiates power stage operationEN/DLY Falling Threshold EN_F — 1.06
— V Stops power stage operationEN/DLY Hysteresis EN_H — 150 —
mVEN/DLY Pull-up Current EN_I 1 2 3 µASwitching
FrequencyProgrammable Frequency (High Z)
fSZ 360 400 440 kHz FREQ = High Z (open)
Programmable Frequency 0 fS0 500 565 630 kHz FREQ= Low
(GND)Programmable Frequency 1 fS1 700 790 880 kHz FREQ = High
(VDDA)Overcurrent ProtectionHS Current Limit 0 ILIM_HS0 6.0 7.1 8.1
A ILIM = Low (GND)HS Current Limit 1 ILIM_HS1 8.1 9.3 10.3 A ILIM =
High (VDDA)HS Current Limit High Z ILIM_HSZ 9.3 10.5 11.9 A ILIM =
High Z (open)Top FET Current Limit Leading-Edge Blanking Time
LEB — 108 — ns
LS Current Limit 0 ILIM_LS0 3.0 4.6 6.3 A ILIM = Low (GND)LS
Current Limit 1 ILIM_LS1 4.0 6.2 7.9 A ILIM = High (VDDA)LS Current
Limit High Z ILIM_LSZ 5.0 6.8 8.6 A ILIM = High Z (Open)OC Events
Count for Hiccup INHICC_DE — 15 — Clock
CyclesNumber of subsequent cycles in current limit before
entering hiccup overload protection
Hiccup Wait Time tHICC_WAIT — 3 x Soft Start Time
— Duration of the High Z state on LX before new soft start.
Note 1: Specification for packaged product only.
DS20005478A-page 4 2015 Microchip Technology Inc.
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MIC45404
Pulse-Width Modulation (PWM)Minimum LX On Time TON(MIN) — 26 —
ns TA = TJ = +25°CMinimum LX Off time TOFF(MIN) 90 135 190 ns VIN =
VDDA = 5V, OUTSNS = 3V,
FREQ = Open (400 kHz setting), VOSET0 = VOSET1 = 0V (3.3V
setting),TA = TJ = +25°C
Minimum Duty Cycle DMIN — 0 — % OUTSNS > 1.1 x VOUT(NOM)Gm
Error AmplifierError Amplifier Transconductance
GmEA — 1.4 — mS
Error Amplifier DC Gain AEA — 50000 — V/VError Amplifier
Source/Sink Current
ISR_SNK -400 — +400 µA TA = TJ = +25°C
COMP Output Swing High COMP_H — 2.5 — VCOMP Output Swing Low
COMP_L — 0.8 — VCOMP-to-Inductor Current Transconductance
GmPS — 12.5 — A/V VOUT = 1.2V, IOUT = 4A
Output Voltage DC AccuracyOutput Voltage Accuracy for Ranges 1
and 2
OutErr12 -1 — 1 % 4.75V VIN 19V, VOUT = 0.7V to 1.8V,TA = TJ =
-40°C to +125°C, IOUT = 0A
Output Voltage Accuracy for Range 3
OutErr3 -1.5 — 1.5 % 4.75V VIN 19V, VOUT = 2.49V to 3.3V,TA = TJ
= -40°C to +125°C,IOUT = 0A
Load Regulation LoadReg — 0.03 — % IOUT = 0A to 5ALine
Regulation LineReg — 0.01 — % 6V < VIN < 19V, IOUT =
2AInternal Soft StartReference Soft Start Slew Rate
SS_SR — 0.42 — V/ms VOUT = 0.7V, 0.8V, 0.9V, 1.0V, 1.2V
Power Good (PG)PG Low Voltage PG_VOL — 0.17 0.4 V IPG = 4 mAPG
Leakage Current PG_ILEAK -1 0.02 1 µA PG = 5VPG Rise Threshold PG_R
90 92 95 % VOUT RisingPG Fall Threshold PG_F 87.5 90 92.5 % VOUT
FallingPG Rise Delay PG_R_DLY — 0.45 — ms VOUT RisingPG Fall Delay
PG_F_DLY — 80 — µs VOUT Falling
ELECTRICAL CHARACTERISTICS(1) (CONTINUED)Electrical
Specifications: unless otherwise specified, VIN = 12V; CVDDA= 2.2
µF, TA = +25°C. Boldface values indicate -40°C TJ +125°C.
Parameter Symbol Min. Typ. Max. Units Test Conditions
Note 1: Specification for packaged product only.
2015 Microchip Technology Inc. DS20005478A-page 5
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MIC45404
Thermal ShutdownThermal Shutdown TSHDN — 160 — °CThermal
Shutdown Hysteresis
TSHDN_HYST — 25 — °C
EfficiencyEfficiency η — 82 — % VIN = 12V, VOUT = 0.9V,
IOUT = 2A, fS = fSZ = 400 kHz, TA = +25°C
ELECTRICAL CHARACTERISTICS(1) (CONTINUED)Electrical
Specifications: unless otherwise specified, VIN = 12V; CVDDA= 2.2
µF, TA = +25°C. Boldface values indicate -40°C TJ +125°C.
Parameter Symbol Min. Typ. Max. Units Test Conditions
Note 1: Specification for packaged product only.
TEMPERATURE SPECIFICATIONSElectrical Specifications: unless
otherwise specified, VIN = 12V; CVDDA= 2.2 µF, TA = +25°C. Boldface
values indicate -40°C TJ +125°C.
Parameters Sym. Min. Typ. Max. Units Conditions
Temperature RangesOperating Ambient Junction Range TJ -40 — +125
°CStorage Temperature Range TA -65 — +150 °CMaximum Junction
Temperature TJ -40 — +150 °CPackage Thermal ResistancesThermal
Resistance, 54 Lead, 6 mm x10 mm QFN
JA — 20 — °C/W See “MIC45404 Evaluation Board User’s Guide”
DS20005478A-page 6 2015 Microchip Technology Inc.
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MIC45404
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, VIN = 12V; CVDDA= 2.2 µF, TA =
+25°C.
FIGURE 2-1: Operating Current (IQ) vs. Input Voltage.
FIGURE 2-2: VDDA Voltage vs. Input Voltage.
FIGURE 2-3: Output Current Limit vs. Input Voltage.
FIGURE 2-4: Enable Threshold vs. Input Voltage.
FIGURE 2-5: EN/DLY Pull-up Current vs. Input Voltage.
FIGURE 2-6: Operating Current (IQ) vs. Temperature.
Note: The graphs and tables provided following this note are a
statistical summary based on a limited number ofsamples and are
provided for informational purposes only. The performance
characteristics listed hereinare not tested or guaranteed. In some
graphs or tables, the data presented may be outside the
specifiedoperating range (e.g., outside specified power supply
range) and therefore outside the warranted range.
15.0017.0019.0021.0023.0025.0027.0029.0031.0033.0035.00
4 6 8 10 12 14 16 18 20
IQ (m
A)
VIN (V)
f = 565 kHzVOUT = 1.8V
f = 400 kHzVOUT = 1.0V
SwitchingIOUT = 0A
f = 790 kHzVOUT = 3.3V
4
4.2
4.4
4.6
4.8
5
5.2
4.5 6.5 8.5 10.5 12.5 14.5 16.5 18.5
V DD
A(V
)
VIN (V)
IoutSet 0IoutSet 0.01IVDDA = 0 mAIVDDA = 10 mA
5
5.5
6
6.5
7
7.5
8
8.5
4.5 5 5.5 6 8 10 12 14 16 18 19
I OU
T(A
)
VIN(V)
ILIM = GND
ILIM = VDDA
ILIM = high ZVOUT = 1.2Vf = 400 kHz
0.9
0.95
1
1.05
1.1
1.15
1.2
1.25
1.3
4.5 6.5 8.5 10.5 12.5 14.5 16.5 18.5
Enab
le (V
)
VIN (V)
Enable rising
Enable falling
11.21.41.61.8
22.22.42.62.8
3
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
Cur
rent
(µA
)
VIN (V)
EN/DLY = 0V
15
20
25
30
35
-40 -25 -10 5 20 35 50 65 80 95 110 125
IQ (m
A)
Temperature (°C)
SwitchingVIN = 12VIOUT = 0A
f = 565 kHzVOUT = 1.8V
f = 790 kHzVOUT = 3.3V
f = 400 kHzVOUT = 1.0V
2015 Microchip Technology Inc. DS20005478A-page 7
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MIC45404
Note: Unless otherwise indicated, VIN = 12V; CVDDA= 2.2 µF, TA =
+25°C.
FIGURE 2-7: EA Output Current vs. Temperature.
FIGURE 2-8: EA Transconductance vs. Temperature.
FIGURE 2-9: Efficiency vs. Output Current (VIN = 12V).
FIGURE 2-10: Efficiency vs. Output Current (VIN = 5V).
FIGURE 2-11: Output Voltage vs. Output Current (VOUT =
0.9V).
FIGURE 2-12: Output Voltage vs. Output Current (VOUT =
1.0V).
-800
-600
-400
-200
0
200
400
600
800
-40 -20 0 20 40 60 80 100 120 140
EA O
utpu
t Cur
rent
(µA
)
Temperature(°C)
VIN = 12V
Sinking
Sourcing
0.6
0.8
1
1.2
1.4
1.6
1.8
2
-40 -20 0 20 40 60 80 100 120 140
EA T
rans
cond
ucta
nce
(mS)
Temperature (°C)
VIN = 12VVOUT = 1.0V
0.00%10.00%20.00%30.00%40.00%50.00%60.00%70.00%80.00%90.00%
100.00%
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Effic
ienc
y (%
)
IOUT (A)
121212121212121212
0.7V0.8V0.9V1.0V1.2V1.5V1.8V2.5V3.3V
0.00%10.00%20.00%30.00%40.00%50.00%60.00%70.00%80.00%90.00%
100.00%
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Effic
ienc
y (%
)
IOUT (A)
555555555
0.7V0.8V0.9V1.0V1.2V1.5V1.8V2.5V3.3V
0.8910.8930.8950.8970.8990.9010.9030.9050.9070.909
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
V OU
T(V
)
IOUT (A)
512VIN = 12VVIN = 5V
0.990
0.995
1.000
1.005
1.010
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
V OU
T(V
)
IOUT (A)
512VIN = 12VVIN = 5V
DS20005478A-page 8 2015 Microchip Technology Inc.
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MIC45404
Note: Unless otherwise indicated, VIN = 12V; CVDDA= 2.2 µF, TA =
+25°C.
FIGURE 2-13: Output Voltage vs. Output Current (VOUT =
1.2V).
FIGURE 2-14: Output Voltage vs. Output Current (VOUT =
1.5V).
FIGURE 2-15: Output Voltage vs. Output Current (VOUT =
1.8V).
FIGURE 2-16: Output Voltage vs. Output Current (VOUT =
2.5V).
FIGURE 2-17: Output Voltage vs. Output Current (VOUT =
3.3V).
1.1901.1921.1941.1961.1981.2001.2021.2041.2061.2081.210
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
V OU
T(V
)
IOUT (A)
512VIN = 12VVIN = 5V
1.490
1.495
1.500
1.505
1.510
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
V OU
T(V
)
IOUT (A)
512VIN = 12VVIN = 5V
1.790
1.795
1.800
1.805
1.810
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
V OU
T(V
)
IOUT (A)
512VIN = 12VVIN = 5V
2.480
2.485
2.490
2.495
2.500
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
V OU
T(V
)
IOUTt (A)
512VIN = 12VVIN = 5V
3.2903.2923.2943.2963.2983.3003.3023.3043.3063.3083.310
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
V OU
T(V
)
IOUT (A)
512VIN = 12VVIN = 5V
2015 Microchip Technology Inc. DS20005478A-page 9
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MIC45404
Note: Unless otherwise indicated, VIN = 12V; CVDDA= 2.2 µF, TA =
+25°C.
FIGURE 2-18: VIN Turn-On.
FIGURE 2-19: VIN Turn-Off.
FIGURE 2-20: Enable Turn-On.
FIGURE 2-21: Enable Turn-Off.
FIGURE 2-22: Enable Start-up w/Pre-Biased Output.
FIGURE 2-23: Enable Start-up w/Pre-Biased Output.
VIN = 12VVOUT = 1.2VRLOAD = 0.3fSW = 400 kHz
VIN(5V/div)
VOUT(500 mV/div)
PG(5V/div)
Time (2 ms/div)
VIN(5V/div)
VOUT(500 mV/div
PG(5V/div)
VIN = 12VVOUT = 1.2VRLOAD = 0.6fSW = 400 kHz
Time (2 ms/div)
EN/DLY(2V/div
VOUT (500 mV/div)
PG(5V/div)
VIN = 12VVOUT = 1.2VROUT = 0.24fSW = 400 kHz
IOUT(2A/div)
Time (1 ms/div)
EN/DLY(2V/div
VOUT (500 mV/div)
PG(5V/div)
VIN = 12VVOUT = 1.2VROUT = 0.24fSW = 400 kHz
IOUT(2A/div)
Time (40 µs/div)
EN/DLY(2V/div
VOUT (500 mV/div)
PG(5V/div)
VIN = 12VVOUT = 1.2VVPRE-BIAS = 0.6VfSW = 400 kHz
Time (1 ms/div)
EN/DLY(2V/div
VOUT (500 mV/div)
PG(5V/div)
VIN = 12VVOUT = 1.2VVPRE-BIAS = 1.0VfSW = 400 kHz
Time (1 ms/div)
DS20005478A-page 10 2015 Microchip Technology Inc.
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MIC45404
Note: Unless otherwise indicated, VIN = 12V; CVDDA= 2.2 µF, TA =
+25°C.
FIGURE 2-24: Power-up into Short Circuit.
FIGURE 2-25: Enable into Short Circuit.
FIGURE 2-26: Output Current Limit (ILIM = 0V).
FIGURE 2-27: Output Current Limit (ILIM = High Z).
FIGURE 2-28: Hiccup Mode Short Circuit and Output Recovery.
FIGURE 2-29: Thermal Shutdown and Thermal Recovery.
VIN(5V/div)
VOUT (500 mV/div)
PG(5V/div)
IOUT(5A/div)
Time (1 ms/div)
EN/DLY(2V/div
VOUT (500 mV/div)
PG(5V/div)
IOUT(5A/div)
Time (1 ms/div)
VOUT (500 mV/div)
PG(5V/div)
VIN = 12VVOUT = 1.2VfSW = 400 kHzILIM = 0V
IOUT(2A/div)Time (1 ms/div)
VOUT (500 mV/div)
PG(5V/div)
VIN = 12VVOUT = 1.2VfSW = 400 kHzILIM = high Z
IOUT(2A/div)Time (1 ms/div)
VOUT (500 mV/div)
PG(5V/div)
IOUT(2A/div)
Time (20 ms/div)
IOUT(2A/div)
VOUT (500 mV/div)
PG(5V/div)
Time (200 ms/div)
2015 Microchip Technology Inc. DS20005478A-page 11
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MIC45404
Note: Unless otherwise indicated, VIN = 12V; CVDDA= 2.2 µF, TA =
+25°C.
FIGURE 2-30: Switching Waveforms (IOUT = 0A).
FIGURE 2-31: Switching Waveforms (IOUT = 5A).
FIGURE 2-32: Load Transient Response.
FIGURE 2-33: Line Transient Response.
VINAC-Coupled(20 mV/div)
VOUT AC-Coupled(10 mV/div)
SW (5V/div)
Time (1 µs/div)
VIN = 12VVOUT = 1.2VIOUT = 0AfSW = 400 kHz
VINAC-Coupled(100 mV/div)
VOUT AC-Coupled(10 mV/div)
SW (5V/div)
Time (1 µs/div)
VIN = 12VVOUT = 1.2VIOUT = 5AfSW = 400 kHz
IOUT(2A/div)
VOUT AC-Coupled(100 mV/div)
PG (5V/div)
VIN = 12VVOUT = 1.0VRLOAD = 1 to 0.3
Time (100 µs/div)
VIN(2V/div)
VOUT AC-Coupled(20 mV/div)
PG(5V/div)
Time (1 ms/div)
DS20005478A-page 12 2015 Microchip Technology Inc.
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MIC45404
3.0 PIN DESCRIPTIONThe descriptions of the pins are listed in
Table 3-1.
3.1 Output Sensing Pins (OUTSNS)Connect these pins directly to
the Buck Converteroutput voltage. These pins are the top side
terminal ofthe internal feedback divider.
3.2 Precision Enable/Turn-On Delay Input Pin (EN/DLY)
The EN/DLY pin is first compared against a 515 mVthreshold to
turn on the on-board LDO regulator. TheEN/DLY pin is then compared
against a 1.21V (typical)threshold to initiate output power
delivery. A 150 mVtypical hysteresis prevents chattering when
powerdelivery is started. A 2 µA (typical) current source pullsup
the EN/DLY pin. Turn-on delay can be achieved byconnecting a
capacitor from EN/DLY to ground, whileusing an open-drain output to
drive the EN/DLY pin.
3.3 MOSFET Drivers Internal Supply Pin (VDDP)
Internal supply rail for the MOSFET drivers, fed by theVDDA pin.
An internal resistor (10) between the VDDPand VDDA pins, and an
internal decoupling capacitorare provided in the module in order to
implement an RCfilter for switching noise suppression.
3.4 Internal Regulator Output Pin (VDDA)
Output of the internal linear regulator and internalsupply for
analog control. A 1 µF minimum ceramiccapacitor should be connected
from this pin to GND; a2.2 µF nominal value is recommended.
TABLE 3-1: PIN FUNCTION TABLEMIC45404 Symbol Pin Function
1, 54 OUTSNS Output Sensing Pin2 EN/DLY Precision Enable/Turn-On
Delay Input Pin 3 VDDP MOSFET Drivers Internal Supply Pin4 VDDA
Internal LDO Output and Analog Supply Pin
5, 6 GND_EXT Ground Extension Pins7, 8 VIN Input Voltage
Pins
9, 23, 24, 50, 51 GND Power Ground Pins11, 12, 13, 14, 15, 16,
17, 18,
19, 20, 21OUT Output Side Connection Pins
10, 22, 25, 40 KEEPOUT Depopulated Pin Positions26, 27, 28, 29,
30, 31, 32, 33,
34, 35, 36, 37, 38, 39LX Switch Node Pins
41, 42 BST Bootstrap Capacitor Pin43 PG Power Good Output Pin44
VOSET0 Output Voltage Selection Pins45 VOSET1
46, 47 NC Not Connected Pins48 ILIM Current Limit Selection
Pin49 FREQ Switching Frequency Selection Pin52 AGND Analog Ground
Pin 53 COMP Compensation Network Pin55 GND_EP Ground Exposed
Pad.
2015 Microchip Technology Inc. DS20005478A-page 13
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MIC45404
3.5 Ground Extension Pins
(GND_EXT)These pins are used for the bottom terminal
connectionof the internal VIN and VDDP decoupling capacitors.The
GND_EXT pins should be connected to the GNDnet, directly at the top
layer, using a wide copperconnection.
3.6 Input Voltage Pins (VIN)Input voltage for the Buck Converter
power stage andinput of the internal linear regulator. These pins
are thedrain terminal of the internal high-side N-channelMOSFET. A
10 µF (minimum) ceramic capacitor shouldbe connected from VIN to
GND, as close as possible tothe device.
3.7 Power Ground Pins (GND)Connect the output capacitors to GND
Pins 23 and 24,as close as possible to the module.
Connect the input capacitors to GND Pin 9, as close aspossible
to the module.
3.8 Output-Side Connection Pins (OUT)
Output side connection of the internal inductor. Theoutput
capacitors should be connected from this pingroup to GND (Pins 23
and 24), as close to the moduleas possible.
3.9 Switch Node Pins (LX)Switch Node: Drain (low-side MOSFET)
and source(high-side MOSFET) connection of the internal
powerN-channel FETs. The internal inductor switched sideand the
bootstrap capacitor are connected to LX.Leave this pin
floating.
3.10 Bootstrap Capacitor Pin (BST)Connection to the internal
bootstrap capacitor andhigh-side power MOSFET drive circuitry.
Leave this pinfloating.
3.11 Power Good Output Pin (PG)When the output voltage is within
92.5% of the nominalset point, this pin will go from logic low to
logic highthrough an external pull-up resistor. This pin is the
drainconnection of an internal N-channel FET.
3.12 Output Voltage Selection Pins (VOSET0 and VOSET1)
Three-state pin (low, high and High Z) for output volt-age
programming. Both VOSET0 and VOSET1 define9 logic values,
corresponding to nine output voltageselections.
3.13 Not Connected Pins (NC)These pins are not internally
connected. Leave themfloating.
3.14 Current Limit Pin (ILIM)This pin allows the selection of
the current limit state:low, high and High Z.
3.15 Switching Frequency Pin (FREQ)This pin allows the selection
of the frequency state: low,high and High Z.
3.16 Analog Ground Pin (AGND)This pin is a quiet ground for the
analog circuitry of theinternal regulator and a return terminal for
the externalcompensation network.
3.17 Compensation Network Pin (COMP)
Connect a compensation network from this pin toAGND.
3.18 GND Exposed PadConnect to ground plane with thermal
vias.
DS20005478A-page 14 2015 Microchip Technology Inc.
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MIC45404
4.0 FUNCTIONAL DESCRIPTIONThe MIC45404 is a pin-programmable, 5A
ValleyCurrent mode controlled power module, with an inputvoltage
range from 4.5V to 19V.
The MIC45404 requires a minimal amount of externalcomponents.
Only two supply decoupling capacitorsand a compensation network are
external. Theflexibility in designing the external
compensationallows the user to optimize the design across the
entireinput voltage and selectable output voltages range.
4.1 Theory of OperationValley Current mode control is a fixed
frequency, lead-ing-edge modulated Pulse-Width Modulation
(PWM)Current mode control. Differing from the Peak Currentmode, the
Valley Current mode clock marks the turn-offof the high-side
switch. Upon this instant, theMIC45404 low-side switch current
level is comparedagainst the reference current signal from the
erroramplifier. When the falling low-side switch current sig-nal
drops below the current reference signal, thehigh-side switch is
turned on. As a result, the inductorvalley current is regulated to
a level dictated by theoutput of the error amplifier.
The feedback loop includes an internal programmablereference and
output voltage sensing attenuator, thusremoving the need for
external feedback componentsand improving regulation accuracy.
Output voltage feed-back is achieved by connecting the OUTSNS pin
directlyto the output. The high-performance transconductanceerror
amplifier drives an external compensation networkat the COMP pin.
The COMP pin voltage represents thereference current signal. This
pin voltage is fed to theValley Current mode modulator, which also
adds slopecompensation to ensure current loop stability.
Internal inductor, power MOSFETs and internalbootstrap diode
complete the power train.
Overcurrent protection and thermal shutdown protectthe MIC45404
from Faults or abnormal operatingconditions.
4.2 Supply Rails (VIN, VDDA, VDDP) and Internal LDO
VIN pins represent the power train input. These pins arethe
drain connection of the internal high-side MOSFETand should be
bypassed to GND, at least with a X5R orX7R 10 µF ceramic capacitor,
placed as close aspossible to the module. Multiple capacitors
arerecommended.
An internal LDO provides a clean supply (5.1V typical)for the
analog circuits at the VDDA pin. The internal LDOis also powered
from VIN, as shown in the FunctionalDiagram. The internal LDO is
enabled when thevoltage at the EN/DLY pin exceeds about 0.51V,
andregulation takes place as soon as enough voltage hasbeen
established between the VIN and VDDA pins. Aninternal Undervoltage
Lockout (UVLO) circuit monitorsthe level of VDDA. The VDDA pin
needs external bypass-ing to GND by means of a 2.2 µF X5R or X7R
ceramiccapacitor, placed as close as possible to the module.
VDDP is the power supply rail for the gate drivers andbootstrap
circuit. This pin is bypassed to GND_EXT bymeans of an internal
high-frequency ceramic capacitor.For this reason, the GND_EXT pins
should be routedwith a low-inductance path to the GND net. An
internal10 resistor is provided between VDDA and VDDP,allowing the
implementation of a switching noise atten-uation RC filter with the
minimum amount of externalcomponents. It is possible, although
typically notnecessary, to lower the RC time constant by
connectingan external resistor between VDDA and VDDP.
If the input rail is within 4.5V to 5.5V, it is possible
tobypass the internal LDO by connecting VIN, VDDA andVDDP together.
Local decoupling of the VDDA pin is stillrecommended.
4.3 Pin-Strapping Programmability (VOSET0, VOSET1, FREQ,
ILIM)
The MIC45404 uses pin strapping to set the output volt-age
(VOSET0, VOSET1), switching frequency (FREQ)and current limit
(ILIM). No external passives are needed,therefore, the external
component count is minimized.Each pin is a three-state input
(connect to GND for LOWlogic level, connect to VDDA for HIGH logic
level or leaveunconnected for High Z). The logic level of the pins
isread and frozen in the internal configuration logicimmediately
after the VDDA rail comes up and becomesstabilized. After this
instant, any change of the input logiclevel on the pins will have
no effect until the VDDA poweris cycled again. The values
corresponding to eachparticular pin strapping configuration are
detailed inSection 5.0 “Application Information”.
2015 Microchip Technology Inc. DS20005478A-page 15
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MIC45404
4.4 Enable/Delay (EN/DLY)The EN/DLY pin is a dual threshold pin
that turns theinternal LDO on/off and starts/stops the power
deliveryto the output, as shown in Figure 4-1.
FIGURE 4-1: EN/DLY Pin Functionality.
The threshold for LDO enable is 515 mV (typical) witha
hysteresis of approximately 30 mV. This hysteresis isenough because
at the time of LDO activation, there isstill no switching
activity.
The threshold for power delivery is a precise 1.21V,±70 mV. A
150 mV typical hysteresis prevents chatteringdue to switching noise
and/or slow edges.
A 2 µA typical pull-up current, with ±1 µA accuracy, per-mits
the implementation of a start-up delay by means ofan external
capacitor. In this case, it is necessary to usean open-drain driver
to disable the MIC45404 whilemaintaining the start-up delay
function.
4.5 Power Good (PG)The PG pin is an open-drain output that
requires anexternal pull-up resistor to a pull-up voltage
(VPU_PG),lower than 5.5V, for being asserted to a logic HIGHlevel.
The PG pin is asserted with a typical delay of0.45 ms when the
output voltage (OUTSNS) reaches92.5% of its target regulation
voltage. This pin isdeasserted with a typical delay of 80 µs when
theoutput voltage falls below 90% of its target regulationvoltage.
The PG falling delay acts as a deglitch timeragainst very short
spikes. The PG output is alwaysimmediately deasserted when the
EN/DLY pin is belowthe power delivery enable threshold
(EN_R/EN_F).The pull-up resistor should be large enough to limit
thePG pin current to below 2 mA.
4.6 Inductor (LX, OUT) and Bootstrap (BST) Pins
The internal inductor is connected across the LX andOUT pins.
The high-side MOSFET driver circuit is pow-ered between BST and LX
by means of an internalcapacitor that is replenished from rail VDDP
during thelow-side MOSFET on time. The bootstrap diode
isinternal.
4.7 Output Sensing (OUTSNS) and Compensation (COMP) Pins
OUTSNS should be connected exactly to the desiredPoint-of-Load
(POL) regulation, avoiding parasiticresistive drops. The impedance
seen into the OUTSNSpin is high (tens of k or more, depending on
theselected output voltage value), therefore, its loadingeffect is
typically negligible. OUTSNS is also used bythe slope compensation
generator.
The COMP pin is the connection for the external com-pensation
network. COMP is driven by the output of thetransconductance error
amplifier. Care must be takento return the compensation network
ground directly toAGND.
4.8 Soft StartThe MIC45404 internal reference is ramped up at
a0.42 V/ms rate. Note that this is the internal referencesoft start
slew rate and that the actual slew rate seen atthe output should
take into account the internal dividerattenuation, as detailed in
the Section 5.0 “ApplicationInformation”.
4.9 Switching Frequency (FREQ)The MIC45404 features three
different selectableswitching frequencies (400 kHz, 565 kHz and790
kHz). Frequency selection is tied with a specificoutput voltage
selection, as described in Section 5.5“Permissible MIC45404
Settings Combinations”.
4.10 Pre-Biased Output Start-upThe MIC45404 is designed to
achieve safe start-up intoa pre-biased output without discharging
the outputcapacitors.
4.11 Thermal ShutdownThe MIC45404 has a thermal shutdown
protection thatprevents operation at excessive temperature.
Thethermal shutdown threshold is typically set at +160°C,with a
hysteresis of +25°C.
EN/DLY Enable PowerComparator
EN_I2 µA
AGNDEN_R1.21V
VIN
EnablePowerDelivery
150 mV
EN_LDO_R515 mV
Enable LDOComparator
DS20005478A-page 16 2015 Microchip Technology Inc.
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MIC45404
4.12 Overcurrent Protection (ILIM) and
Hiccup Mode Short-Circuit Protection
The MIC45404 features instantaneous cycle-by-cyclecurrent limit
with current sensing, both on the low-sideand high-side switches.
It also offers a Hiccup mode forprolonged overloads or
short-circuit conditions.
The low-side cycle-by-cycle protection detects the cur-rent
level of the inductor current during the low-sideMOSFET on time.
The high-side MOSFET turn-on isinhibited as long as the low-side
MOSFET current limit isabove the overcurrent threshold level. The
inductor cur-rent will continue decaying until the current falls
belowthe threshold, where the high-side MOSFET will beenabled
again, according to the duty cycle requirementfrom the PWM
modulator.
The low-side current limit has three different program-mable
levels (for 3A, 4A and 5A loads) in order to fitdifferent
application requirements. Since the low-sidecurrent limit acts on
the valley current, the DC outputcurrent level (IOUT), where the
low-side cycle-by-cyclecurrent limit is engaged, will be higher
than the currentlimit value by an amount equal to ILPP/2, where
ILPPis the peak-to-peak inductor ripple current.
The high-side current limit is approximately1.4-1.5 times
greater than the low-side current limit(typical values). The
high-side cycle-by-cycle currentlimit immediately truncates the
high-side on timewithout waiting for the off clocking event.
A Leading-Edge Blanking (LEB) timer (108 ns, typical)is provided
on the high-side cycle-by-cycle current limitto mask the switching
noise and to prevent falselytriggering the protection. The
high-side cycle-by-cyclecurrent limit action cannot take place
before the LEBtimer expires.
Hiccup mode protection reduces power dissipation inpermanent
short-circuit conditions. On each clockcycle, where a low-side
cycle-by-cycle current limitevent is detected, a 4-bit up/down
counter is incre-mented. On each clock cycle without a
concurrentlow-side current limit event, the counter is
decrementedor left at zero. The counter cannot wraparound
below‘0000’ and above ‘1111’. High-side current limit eventsdo not
increment the counter. Only detections fromlow-side current limit
events trigger the counter.
If the counter reaches ‘1111’ (or 15 events), the highand
low-side MOSFETs become tri-stated, and powerdelivery to the output
is inhibited for the duration ofthree times the soft start time.
This digital integrationmechanism provides immunity to momentary
overload-ing of the output. After the wait time, the
MIC45404retries entering operation and initiates a new soft
startsequence.
2015 Microchip Technology Inc. DS20005478A-page 17
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MIC45404
Figure 4-2 illustrates the Hiccup mode short-circuit pro-tection
logic flow. Note that Hiccup mode short-circuitprotection is active
at all times, including the soft startramp.
FIGURE 4-2: Hiccup Mode Short-Circuit Protection Logic.
START
CLEARLS OC EVENTS
COUNTER
CLOCK PULSE(MARKING HSTURN-OFF,
LS TURN-ON) IDLE LOOPIN NORMALOPERATION
LS OC EVENTDETECTED?
EVENTCOUNTER = 0
DECREMENTEVENT
COUNTER
EVENT COUNTERFULL?
INCREMENTEVENT
COUNTER
INITIATE HICCUPSEQUENCE
STOP SWITCHINGHS AND LS
CYCLE THREE TIMESINTERNAL SOFT START
CAPACITOR
CLEARLS OC EVENTS
COUNTERINITIATE SOFT STARTENABLE SWITCHING
YES
YES
YES
NO
NO
NO
DS20005478A-page 18 2015 Microchip Technology Inc.
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MIC45404
5.0 APPLICATION INFORMATION
5.1 Programming Start-up Delay and External UVLO
The EN/DLY pin allows programming an externalstart-up delay. In
this case, the driver for the EN/DLYpin should be an
open-drain/open-collector type, asshown in Figure 5-1.
FIGURE 5-1: Programmable Start-up Delay Function.
The start-up delay is the delay time from the off fallingedge to
the assertion of the enable power deliverysignal. It can be
calculated as shown in Equation 5-1:
EQUATION 5-1:
The EN/DLY pin can also be used to program a UVLOthreshold for
power delivery by means of an externalresistor divider, as
described in Figure 5-2.
FIGURE 5-2: Programmable External UVLO Function.
EN/DLY Enable PowerComparator
EN_I2 µA
AGND
EN_R1.21V
VIN
EnablePowerDelivery
150 mV
EN_LDO_R515 mV
Enable LDOComparator
CDLYOff
tSU_DLYEN_R CDLY
EN_I-----------------------------------=
Where:
EN_R = 1.21VEN_I = 2 µACDLY = Delay programming external
capacitor
EN/DLY Enable PowerComparator
R2
R1
EN_I2 µA
AGND
EN_R1.21V
VIN
EnablePowerDelivery
150 mV
EN_LDO_R515 mV
Enable LDOComparator
2015 Microchip Technology Inc. DS20005478A-page 19
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MIC45404
The programmed VIN UVLO threshold, VIN_RISE, isgiven by:
EQUATION 5-2:
To desensitize the VIN UVLO threshold against varia-tions of the
pull-up current, EN_I, it is recommended torun the R1 – R2 voltage
divider at a significantly highercurrent level than the EN_I
current.
The corresponding VIN UVLO hysteresis, VIN_HYS, iscalculated as
follows:
EQUATION 5-3:
Similar calculations also apply to the internal LDOactivation
threshold.
5.2 Setting the Switching FrequencyThe MIC45404 switching
frequency can beprogrammed using FREQ, as shown in Table 5-1.
The switching frequency setting is not arbitrary, but itneeds to
be adjusted according to the particular outputvoltage selection due
to peak-to-peak inductorripple requirements. This is illustrated in
Section 5.5“Permissible MIC45404 Settings Combinations”.
5.3 Setting the Output VoltageThe MIC45404 output voltage can be
programmed bysetting pins, VOSET0 and VOSET1, as shown inTable
5-2.
To achieve accurate output voltage regulation, theOUTSNS pin
(internal feedback divider top terminal)should be Kelvin-connected
as close as possible to thepoint of regulation top terminal. Since
both the internalreference and the internal feedback divider’s
bottomterminal refer to AGND, it is important to minimizevoltage
drops between the AGND and the point ofregulation return
terminal.
5.4 Setting the Current LimitThe MIC45404’s valley-mode current
limit on thelow-side MOSFET can be programmed by means ofILIM as
shown in Table 5-3.
Note that the programmed current limit values act
aspulse-by-pulse, current limit thresholds on the valleyinductor
current. If the inductor current has not decayedbelow the threshold
at the time the PWM requires a newon time, the high-side MOSFET
turn-on is either delayed,until the valley current recovers below
the threshold, orskipped. Each time the high-side MOSFET turn-on
isskipped, a 4-bit up-down counter is incremented. Whenthe counter
reaches the configuration ‘1111’, a hiccupsequence is invoked in
order to reduce power dissipationunder prolonged short-circuit
conditions.
The highest current limit setting (6.8A) is intended
tocomfortably accommodate a 5A application. Ensurethat the value of
the operating junction temperaturedoes not exceed the maximum
rating in high outputpower applications.
TABLE 5-1: SWITCHING FREQUENCY SETTINGS
FREQ Pin Setting Frequency
High Z (open) 400 kHz0 (GND) 565 kHz1 (VDDA) 790 kHz
VIN_RISE EN_R 1R2R1------+
EN_I R2–=
Where:
EN_R = 1.21VEN_I = 2 µA
R1 and R2 = External resistors
VIN_HYS 150 mV 1R2R1------+
=
TABLE 5-2: OUTPUT VOLTAGE SETTINGSVOSET1 VOSET0 Output
Voltage
0 (GND) 0 (GND) 3.3V0 (GND) 1 (VDDA) 2.5V (2.49V)1 (VDDA) 0
(GND) 1.8V1 (VDDA) 1 (VDDA) 1.5V0 (GND) High Z (open) 1.2V
High Z (open) 0 (GND) 1.0V1 (VDDA) High Z (open) 0.9V
High Z (open) 1 (VDDA) 0.8VHigh Z (open) High Z (open) 0.7V
TABLE 5-3: CURRENT LIMIT SETTINGS
ILIMValley Current Limit
(Typical Value)Rated Output
Current
0 (GND) 4.6 A 3A1 (VDDA) 6.2 A 4A
High Z (open) 6.8 A 5A
DS20005478A-page 20 2015 Microchip Technology Inc.
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MIC45404
5.5 Permissible MIC45404 Settings
CombinationsThe MIC45404 allowable settings are constrained
bythe values in Table 5-4.
5.6 Output Capacitor SelectionTwo main requirements determine
the size andcharacteristics of the output capacitor, CO:
• Steady-state ripple• Maximum voltage deviation during load
transient
For steady-state ripple calculation, both the ESR andthe
capacitive ripple contribute to the total ripple ampli-tude. The
MIC45404 utilizes a low loss inductor, whosenominal value is 1.2
µH. From the switching frequency,input voltage, output voltage
setting and load current,the peak-to-peak inductor current ripple
and the peakinductor current can be calculated as:
EQUATION 5-4:
EQUATION 5-5:
The capacitive ripple, Vr,C, and the ESR ripple,Vr,ESR, are
given by:
EQUATION 5-6:
EQUATION 5-7:
The total peak-to-peak output ripple is thenconservatively
estimated as:
EQUATION 5-8:
The output capacitor value and ESR should be chosensuch that VR
is within specifications. Capacitor toler-ance should be considered
for worst-case calculations.In case of ceramic output capacitors,
factor intoaccount the decrease of effective capacitance
versusapplied DC bias.
The worst-case load transient for output capacitor cal-culation
is an instantaneous 100% to 0% load releasewhen the inductor
current is at its peak value. In thiscase, all the energy stored in
the inductor is absorbedby the output capacitor, while the
converter stopsswitching and keeps the low-side FET on.
The peak output voltage overshoot (VO) happenswhen the inductor
current has decayed to zero. Thiscan be calculated with Equation
5-9:
EQUATION 5-9:
Equation 5-10 calculates the minimum outputcapacitance value
(CO(MIN)) needed to limit the outputovershoot below VO.
EQUATION 5-10:
The result from the minimum output capacitance valuefor load
transient is the most stringent requirementfound for capacitor
value in most applications. LowEquivalent Series Resistance (ESR)
ceramic outputcapacitors, with X5R or X7R temperature ratings,
arerecommended.
For low output voltage applications with demandingload transient
requirements, using a combination ofpolarized and ceramic output
capacitors may be themost convenient option for smallest solution
size.
TABLE 5-4: PERMISSIBLE MIC45404 SETTINGS COMBINATIONS
Output Voltage Frequency
3.3V 790 kHz2.5V (2.49V)
1.8V 565 kHz1.5V1.2V 400 kHz1.0V0.9V0.8V0.7V
IL_PP VO
1VOVIN--------–
fS L------------------
=
IL,PEAK IOIL_PP
2-----------------+=
VR,CIL_PP
8 f S CO---------------------------=
VR,ESR ESR IL_PP=
VR VR,C VR,ESR+
VO V2
OL
CO------- IL,PEAK
2+ VO–=
CO MIN L I 2L,PEAK
VO VO+ 2 V2O–
------------------------------------------------=
2015 Microchip Technology Inc. DS20005478A-page 21
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MIC45404
5.7 Input Capacitor SelectionTwo main requirements determine the
size andcharacteristics of the input capacitor:
• Steady-State Ripple• RMS Current
The Buck Converter input current is a pulse train withvery fast
rising and falling times, so low-ESR ceramiccapacitors are
recommended for input filtering becauseof their good high-frequency
characteristics.
By assuming an ideal input filter (which can be assimi-lated to
a DC input current feeding the filtered buckpower stage) and by
neglecting the contribution of theinput capacitor ESR to the input
ripple (which is typicallypossible for ceramic input capacitors),
the minimumcapacitance value, CIN(MIN), needed for a given
inputpeak-to-peak ripple voltage, Vr, IN, can be estimated asshown
in Equation 5-11:
EQUATION 5-11:
The RMS current, IIN,RMS, of the input capacitor isestimated as
in Equation 5-12:
EQUATION 5-12:
Note that, for a given output current, IO, worst-casevalues are
obtained at D = 0.5.
Multiple input capacitors can be used to reduce inputripple
amplitude and/or individual capacitor RMScurrent.
5.8 Compensation DesignAs a simple first-order approximation,
the Valley Currentmode controlled buck power stage can be modeled
as avoltage controlled current source, feeding the outputcapacitor
and load. The inductor current state variable isremoved and the
power stage transfer function fromCOMP to the inductor current is
modeled as a transcon-ductance (GmPS). The simplified model of the
controlloop is shown in Figure 5-3. The power stage
trans-conductance, GmPS, shows some dependence oncurrent levels and
it is also somewhat affected byprocess variations, therefore, some
design margin isrecommended against the typical value, GmPS =
12.5A/V(see Section 1.0 “Electrical Characteristics”).
FIGURE 5-3: Simplified Small Signal Model of the Voltage
Regulation Loop.This simplified approach disregards all issues
relatedto the inner current loop, like its stability and
bandwidth.This approximation is good enough for most
operatingscenarios, where the voltage loop bandwidth is notpushed
to aggressively high frequencies.
Based on the model shown in Figure 5-3, thecontrol-to-output
transfer function is:
EQUATION 5-13:
The MIC45404 module uses a transconductance(GmEA = 1.4 mA/V)
error amplifier. Frequency compen-sation is implemented with a
Type-II network (RC1, CC1and CC2) connected from the COMP to AGND.
Thecompensator transfer function consists of an integratorfor zero
DC voltage regulation error, a zero to boost thephase margin of the
overall loop gain around thecrossover frequency and an additional
pole that canbe used to cancel the output capacitor ESR zero, or
tofurther attenuate switching frequency ripple. In bothcases, the
additional pole makes the regulation loopless susceptible to
switching frequency noise. Theadditional pole is created by
capacitor CC2 (internallyprovided, CC2 value is 47 pF). Equation
5-14 details thecompensator transfer function, HC(S) (from OUTSNS
toCOMP).
CIN MIN IO D 1 D–
Vr,IN f S----------------------------------------=
Where:
D is the duty cycle at the given operating point.
IIN,RMS IO D 1 D– =
GmPSGm Error Amplifier
OUTSNS
COMP
R2
R1
REFDAC
VO Range CC2
CC1
RC1
CoRL
ESR
VoVIN
Vc
IL
GmEA
GCO S VO S VC S ------------- GmPS RL
1 s2 fZ-----------------+
1 s2 fP-----------------+
--------------------------------= =
Where fZ and fP = the frequencies associated withthe output
capacitor ESR zero and with the loadpole, respectively:
fZ1
2 CO ESR-------------------------------------=
fP1
2 CO ESR RL+
-------------------------------------------------------=
DS20005478A-page 22 2015 Microchip Technology Inc.
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MIC45404
EQUATION 5-14:
The overall voltage loop gain, TV(S), is the product ofthe
control-to-output and the compensator transferfunctions:
EQUATION 5-15:
The value of the attenuation ratio, R1/(R1 + R2),depends on the
output voltage selection and can beretrieved as illustrated in
Table 5-5:
The compensation design process is as follows:
1. Set the TV(s) loop gain crossover frequency, fXO,in the range
of fS/20 to fS/10. Lower values offXO allow a more predictable and
robust phasemargin. Higher values of fXO would involve addi-tional
considerations about the current loopbandwidth in order to achieve
a robust phasemargin. Taking a more conservative approach ishighly
recommended.
EQUATION 5-16:
2. Select RC1 to achieve the target crossoverfrequency, fXO, of
the overall voltage loop. Thistypically happens where the power
stagetransfer function, GCO(S), is rolling off at-20 dB/decade. The
compensator transfer func-tion, HC(S), is in the so-called midband
gainregion, where CC1 can be considered a DCblocking short circuit,
while CC2 can still beconsidered as an open circuit, as calculated
inEquation 5-17:
EQUATION 5-17:
3. Select capacitor CC1 to place the compensatorzero at the load
pole. The load pole movesaround with load variations, so to
calculate theload pole use as a load resistance RL, the
valuedetermined by the nominal output current, IO, ofthe
application, as shown in Equation 5-18 andEquation 5-19:
EQUATION 5-18:
EQUATION 5-19:
4. Knowing that an internal CC2 capacitor of 47 pFis provided
already, find out if any additionalcapacitance is needed to augment
the overallvalue of the capacitor, CC2.
The CC2 (total value) is intended for placing the com-pensator
pole at the frequency of the output capacitorESR zero and/or
achieve additional switchingripple/noise attenuation.
If the output capacitor is a polarized one, its ESR zerowill
typically occur at low enough frequencies to causethe loop gain to
flatten out and not roll off at a-20 dB/decade slope, around or
just after the crossoverfrequency, fXO. This causes undesirable
scarcecompensation design robustness and switching
noisesusceptibility. The compensator pole is then used tocancel the
output capacitor ESR zero and achieve awell-behaved roll-off of the
loop gain above thecrossover frequency.
If the output capacitors are only ceramic, then the ESRzeros
frequencies could be very high. In many cases,the frequencies could
even be above the switchingfrequency itself. Loop gain roll-off at
-20 dB/decade isensured well beyond the crossover frequency, but
evenin this case, it is good practice to still make use of
thecompensator pole to further attenuate switching noise,while
conserving phase margin at the crossoverfrequency.
TABLE 5-5: INTERNAL FEEDBACK DIVIDER ATTENUATION VALUES
VO Range R1/(R1 + R2)A
(A = 1 + R2/R1)
0.7V-1.2V 1 11.5V-1.8V 0.5 2
2.5V(2.49V)-3.3V 0.333 3
HC S R1
R1 R2+--------------------- GmEA1
S CC1 CC2+ --------------------------------------------–=
1 S RC1 CC1+
1 S RC1CC1 CC2CC1 CC2+---------------------------+
--------------------------------------------------------------------
TV S GCO S HC S =
fS20------ fXO
fS10------
RC1R1 R2+
R1--------------------- 2 CO fXO
GmEA GmPS------------------------------------=
RLVOIO-------=
CC1CO ESR RL+
RC1------------------------------------------=
2015 Microchip Technology Inc. DS20005478A-page 23
-
MIC45404
For example, setting the compensator pole at 5 fXO willlimit its
associated phase loss at the crossoverfrequency to about 11°.
Placement at even higherfrequencies, N × fXO (N > 5), will
reduce phase losseven further at the expense of less noise/ripple
attenu-ation at the switching frequency. Some attenuation ofthe
switching frequency noise/ripple is achieved aslong as N × fXO <
fS.
For the polarized output capacitor, compensator poleplacement at
the ESR zero frequency is achieved, asshown in Equation 5-20:
EQUATION 5-20:
For the ceramic output capacitor, compensator poleplacement at N
× fXO (N 5, N × fXO < fS) is achieved,as detailed in Equation
5-21:
EQUATION 5-21:
The MIC45404 already provides an internal CC2 capac-itor of 47
pF. Therefore, the external capacitance,CC2_EXT, that should be
added is given byEquation 5-22:
EQUATION 5-22:
If the result, CC2 – 47 pF, yields to zero or to a
negativenumber, no additional external capacitance is neededfor
CC2.
5.9 Output Voltage Soft Start RateThe MIC45404 features an
internal analog soft start,such that the output voltage can be
smoothly increasedto the target regulation voltage. The soft start
rate givenin Section 1.0 “Electrical Characteristics” is referredto
the error amplifier reference, and therefore, theeffective soft
start rate value, seen at the output of themodule, has to be scaled
according to the internal feed-back divider attenuation values
listed in Table 5-5. Tocalculate the effective output voltage soft
start slewrate, SS_SROUT, based on the particular output
voltagesetting and the reference soft start slew rate, SS_SR,use
the following formula:
EQUATION 5-23:
For the value of A, see the right column of Table 5-5.
CC21
RC1CO ESR------------------------ 1CC1
----------–-----------------------------------------=
CC21
2 RC1 N fXO1
CC1----------–
----------------------------------------------------------------=
CC2_EXT max CC2 47 pF, 0 pF– =
SS_SROUT A SS_SR=
Where:
A = Amplification
DS20005478A-page 24 2015 Microchip Technology Inc.
-
MIC45404
6.0 PACKAGING INFORMATION
2015 Microchip Technology Inc. DS20005478A-page 25
-
MIC45404
DS20005478A-page 26 2015 Microchip Technology Inc.
-
MIC45404
APPENDIX A: REVISION HISTORY
Revision A (December 2015)• Original release of this
document.
2015 Microchip Technology Inc. DS20005478A-page 27
-
MIC45404
NOTES:
DS20005478A-page 28 2015 Microchip Technology Inc.
-
MIC45404
PRODUCT IDENTIFICATION SYSTEMTo order or obtain information,
e.g., on pricing or delivery, refer to the factory or the listed
sales office.
PART NO.
Device
Device: MIC45404: Ultra-low profile, synchronous step-down
regulator module
Lead Finish: Y = Pb-Free with Industrial Temperature Grade
Package Code MP = Module Package, thickness ≥ 2.0 mm
Tape and Reel Option:
TR = Tape and Reel(1)
Examples:a) MIC45404YMP-TR: Pb-Free, 54 Lead
6 x 10 x 2 mm QFN Package, Tape and Reel.
Note 1: Tape and Reel identifier only appears in the catalog
part number description. This identi-fier is used for ordering
purposes and is not printed on the device package. Check with your
Microchip Sales Office for package availability with the Tape and
Reel option.
-XX(1)
Tape and ReelOption
X XX
Lead Finish Package Code
2015 Microchip Technology Inc. DS20005478A-page 29
-
MIC45404
NOTES:
DS20005478A-page 30 2015 Microchip Technology Inc.
-
Note the following details of the code protection feature on
Microchip devices:• Microchip products meet the specification
contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the
most secure families of its kind on the market today, when used in
the intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to
breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside
the operating specifications contained in Microchip’s Data Sheets.
Most likely, the person doing so is engaged in theft of
intellectual property.
• Microchip is willing to work with the customer who is
concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can
guarantee the security of their code. Code protection does not mean
that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are
committed to continuously improving the code protection features of
ourproducts. Attempts to break Microchip’s code protection feature
may be a violation of the Digital Millennium Copyright Act. If such
actsallow unauthorized access to your software or other copyrighted
work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding
deviceapplications and the like is provided only for your
convenienceand may be superseded by updates. It is your
responsibility toensure that your application meets with your
specifications.MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF
ANY KIND WHETHER EXPRESS ORIMPLIED, WRITTEN OR ORAL, STATUTORY
OROTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED
TO ITS CONDITION,QUALITY, PERFORMANCE, MERCHANTABILITY ORFITNESS
FOR PURPOSE. Microchip disclaims all liabilityarising from this
information and its use. Use of Microchipdevices in life support
and/or safety applications is entirely atthe buyer’s risk, and the
buyer agrees to defend, indemnify andhold harmless Microchip from
any and all damages, claims,suits, or expenses resulting from such
use. No licenses areconveyed, implicitly or otherwise, under any
Microchipintellectual property rights unless otherwise stated.
2015 Microchip Technology Inc.
QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV
== ISO/TS 16949 ==
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck,
MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32
logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are
registered trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial
Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet
logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM,
PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial
Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany
II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2015, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
ISBN: 978-1-5224-0125-4
Microchip received ISO/TS-16949:2009 certification for its
worldwide
DS20005478A-page 31
headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona; Gresham, Oregon and design centers in
California and India. The Company’s quality system processes and
procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code
hopping devices, Serial EEPROMs, microperipherals, nonvolatile
memory and analog products. In addition, Microchip’s quality system
for the design and manufacture of development systems is ISO
9001:2000 certified.
-
DS20005478A-page 32 2015 Microchip Technology Inc.
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19V 5A Ultra-Low Profile DC-to-DC Power
ModuleFeaturesApplicationsGeneral DescriptionTypical
ApplicationPackage TypesFunctional Diagram1.0 Electrical
CharacteristicsElectrical CharacteristicsTemperature
SpecificationsAbsolute Maximum Ratings†Operating Ratings
2.0 Typical Performance CurvesFIGURE 2-1: Operating Current (IQ)
vs. Input Voltage.FIGURE 2-2: VDDA Voltage vs. Input Voltage.FIGURE
2-3: Output Current Limit vs. Input Voltage.FIGURE 2-4: Enable
Threshold vs. Input Voltage.FIGURE 2-5: EN/DLY Pull-up Current vs.
Input Voltage.FIGURE 2-6: Operating Current (IQ) vs.
Temperature.FIGURE 2-7: EA Output Current vs. Temperature.FIGURE
2-8: EA Transconductance vs. Temperature.FIGURE 2-9: Efficiency vs.
Output Current (VIN = 12V).FIGURE 2-10: Efficiency vs. Output
Current (VIN = 5V).FIGURE 2-11: Output Voltage vs. Output Current
(VOUT = 0.9V).FIGURE 2-12: Output Voltage vs. Output Current (VOUT
= 1.0V).FIGURE 2-13: Output Voltage vs. Output Current (VOUT =
1.2V).FIGURE 2-14: Output Voltage vs. Output Current (VOUT =
1.5V).FIGURE 2-15: Output Voltage vs. Output Current (VOUT =
1.8V).FIGURE 2-16: Output Voltage vs. Output Current (VOUT =
2.5V).FIGURE 2-17: Output Voltage vs. Output Current (VOUT =
3.3V).FIGURE 2-18: VIN Turn-On.FIGURE 2-19: VIN Turn-Off.FIGURE
2-20: Enable Turn-On.FIGURE 2-21: Enable Turn-Off.FIGURE 2-22:
Enable Start-up w/Pre-Biased Output.FIGURE 2-23: Enable Start-up
w/Pre-Biased Output.FIGURE 2-24: Power-up into Short Circuit.FIGURE
2-25: Enable into Short Circuit.FIGURE 2-26: Output Current Limit
(ILIM = 0V).FIGURE 2-27: Output Current Limit (ILIM = High
Z).FIGURE 2-28: Hiccup Mode Short Circuit and Output
Recovery.FIGURE 2-29: Thermal Shutdown and Thermal Recovery.FIGURE
2-30: Switching Waveforms (IOUT = 0A).FIGURE 2-31: Switching
Waveforms (IOUT = 5A).FIGURE 2-32: Load Transient Response.FIGURE
2-33: Line Transient Response.
3.0 Pin DescriptionTABLE 3-1: Pin Function Table3.1 Output
Sensing Pins (OUTSNS)3.2 Precision Enable/Turn-On Delay Input Pin
(EN/DLY)3.3 MOSFET Drivers Internal Supply Pin (VDDP)3.4 Internal
Regulator Output Pin (VDDA)3.5 Ground Extension Pins (GND_EXT)3.6
Input Voltage Pins (VIN)3.7 Power Ground Pins (GND)3.8 Output-Side
Connection Pins (OUT)3.9 Switch Node Pins (LX)3.10 Bootstrap
Capacitor Pin (BST)3.11 Power Good Output Pin (PG)3.12 Output
Voltage Selection Pins (VOSET0 and VOSET1)3.13 Not Connected Pins
(NC)3.14 Current Limit Pin (ILIM)3.15 Switching Frequency Pin
(FREQ)3.16 Analog Ground Pin (AGND)3.17 Compensation Network Pin
(COMP)3.18 GND Exposed Pad
4.0 Functional Description4.1 Theory of Operation4.2 Supply
Rails (VIN, VDDA, VDDP) and Internal LDO4.3 Pin-Strapping
Programmability (VOSET0, VOSET1, FREQ, ILIM)4.4 Enable/Delay
(EN/DLY)FIGURE 4-1: EN/DLY Pin Functionality.
4.5 Power Good (PG)4.6 Inductor (LX, OUT) and Bootstrap (BST)
Pins4.7 Output Sensing (OUTSNS) and Compensation (COMP) Pins4.8
Soft Start4.9 Switching Frequency (FREQ)4.10 Pre-Biased Output
Start-up4.11 Thermal Shutdown4.12 Overcurrent Protection (ILIM) and
Hiccup Mode Short-Circuit ProtectionFIGURE 4-2: Hiccup Mode
Short-Circuit Protection Logic.
5.0 Application Information5.1 Programming Start-up Delay and
External UVLOFIGURE 5-1: Programmable Start-up Delay
Function.EQUATION 5-1:FIGURE 5-2: Programmable External UVLO
Function.EQUATION 5-2:EQUATION 5-3:
5.2 Setting the Switching FrequencyTABLE 5-1: Switching
Frequency Settings
5.3 Setting the Output VoltageTABLE 5-2: Output Voltage
Settings
5.4 Setting the Current LimitTABLE 5-3: Current Limit
Settings
5.5 Permissible MIC45404 Settings CombinationsTABLE 5-4:
Permissible MIC45404 Settings Combinations
5.6 Output Capacitor SelectionEQUATION 5-4:EQUATION 5-5:EQUATION
5-6:EQUATION 5-7:EQUATION 5-8:EQUATION 5-9:EQUATION 5-10:
5.7 Input Capacitor SelectionEQUATION 5-11:EQUATION 5-12:
5.8 Compensation DesignFIGURE 5-3: Simplified Small Signal Model
of the Voltage Regulation Loop.EQUATION 5-13:EQUATION 5-14:EQUATION
5-15:TABLE 5-5: Internal Feedback Divider Attenuation
ValuesEQUATION 5-16:EQUATION 5-17:EQUATION 5-18:EQUATION
5-19:EQUATION 5-20:EQUATION 5-21:EQUATION 5-22:
5.9 Output Voltage Soft Start RateEQUATION 5-23:
6.0 Packaging InformationAppendix A: Revision HistoryProduct
Identification SystemTrademarksWorldwide Sales and Service