02131 Embedded Systems 1 [email protected]Jan Madsen Informatics and Mathematical Modeling Technical University of Denmark Richard Petersens Plads, Building 321 DK2800 Lyngby, Denmark Mic-1 microprocessor design 02131 Embedded Systems 2 The Mic-1 architecture
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Mic-102131 Embedded Systems 1 [email protected] Jan Madsen Informatics and Mathematical Modeling Technical University of Denmark Richard Petersens Plads, Building 321
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?programmer does not need to know detailed information about the processor’s architecture?but, needs an architectural abstraction?two levels of programming:?Assembly-language programming, processor specific
?Atomic processor operations that the programmer may invoke?Describes the bit-configurations allowed in the IR
(Instruction Register)?each configuration forms an assembly instruction?a sequence of such configurations forms an assembly
program
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Instruction
Opcode field Operand field
Types of instructions:
Data-transferArithmetic/logicalBranch
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Data-transfer instructions
?Move data between registers?Move data between memory and registers?Move data between input/output channels and
registers
MOV: A = 47
2 byte ( 16 bit )
74 (Hex) 2F (Hex)
0 1 1 1 0 1 0 0 0 0 1 0 1 1 1 1
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Arithmetic/logical instructions
?Configure the ALU to carry out a particular function?Channel data from registers through the ALU?Channel data from the ALU back to a particular register
ADD: A = A + Rn
0 0 1 0 1 r r r 1 byte ( 8 bit )
ADD: A = A + R2 00101010 2A (Hex)
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Branch instructions
?Determines the address of the next instruction? Types of branches:
Unconditional jumps
Conditional jumps
Procedure call and return
Long jump: LJMP addr1602 XX XX
Jump if accumulator zero: JZ addr860 XX (relative address)
The microprogram for the Mic-1Label Operations Comments --------------------------------------------------------------------------------------------------------------------------------------------------------Main1 PC = PC + 1; fetch; goto (MBR) MBR holds opcode; get next byte; dispatch --------------------------------------------------------------------------------------------------------------------------------------------------------nop1 goto Main1 Do nothing --------------------------------------------------------------------------------------------------------------------------------------------------------iadd1 MAR = SP = SP - 1; rd Read in next-to-top word on stackiadd2 H = TOS H = top of stackiadd3 MDR = TOS = MDR + H; wr; goto Main1 Add top two words; write to top of stack --------------------------------------------------------------------------------------------------------------------------------------------------------isub1 MAR = SP = SP - 1; rd Read in next-to-top word on stackisub2 H = TOS H = top of stackisub3 MDR = TOS = MDR - H; wr; goto Main1 Do subtraction; write to top of stack --------------------------------------------------------------------------------------------------------------------------------------------------------iand1 MAR = SP = SP - 1; rd Read in next-to-top word on stackiand2 H = TOS H = top of stackiand3 MDR= TOS = MDR AND H; wr; goto Main1 Do AND; write to new top of stack --------------------------------------------------------------------------------------------------------------------------------------------------------ior1 MAR = SP = SP - 1; rd Read in next-to-top word on stackior2 H = TOS H = top of stackior3 MDR = TOS = MDR OR H; wr; goto Main1 Do OR; write to new top of stack --------------------------------------------------------------------------------------------------------------------------------------------------------dup1 MAR = SP = SP + 1 Increment SP and copy to MARdup2 MDR = TOS; wr; goto Main1 Write new stack word --------------------------------------------------------------------------------------------------------------------------------------------------------pop1 MAR = SP = SP - 1; rd Read in next-to-top word on stackpop2 Wait for new TOS to be read from memorypop3 TOS = MDR; goto Main1 Copy new word to TOS
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Microinstructions
? IJVM instruction: iadd? Add the top two words from
// No output to bus B, no input from bus C and ALU outputs a zerosfg idle {ALUsel = 0b00010000; Bsel = 9; Csel = 0b000000000;}
// The following are the actions necessary to compute GCD// read x, y - initially y is in LV and x in CPP// during iterations, y will stay in LV and x will be in H// LV is used as an auxillary register
// a1: move x (CPP) to Hsfg a1 { ALUsel = 0b00010100; Bsel = 6; Csel = 0b100000000; $display($cycle," ",$sfg);}
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Mic-1 controller// The following are the actions necessary to compute GCD// read x, y - initially y is in LV and x in CPP// during iterations, y will stay in LV and x will be in H// LV is used as an auxillary register
// a1: move x (CPP) to Hsfg a1 { ALUsel = 0b00010100; Bsel = 6; Csel = 0b100000000; $display($cycle," ",$sfg);}
// a5: H = LV - Hsfg a5 { ALUsel = 0b00111111; Bsel = 5; Csel = 0b100000000; $display($cycle," ",$sfg);}
// a6: H = -Hsfg a6 { ALUsel = 0b00111011; Bsel = 9; Csel = 0b100000000; $display($cycle," ",$sfg);}
// a7: out = Hsfg a7 { ALUsel = 0b00011000; Bsel = 9; Csel = 0b100000000; $display($cycle," ",$sfg);}
}
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Mic-1 controllerfsm ctr(mic1_ctr) {initial s0;state s1, s2, s3, s4, s5, s6;// The GCD program,// @s0 (rep,idle) -> s1; // we need an idle transition in order
// to get the registers initialized@s1 (rep,a1) -> s2;@s2 (rep,a2) -> s3;@s3 if (s_z) then (rep,idle) -> s6;
else (rep,a3) -> s4;@s4 if (s_n) then (rep,a5) -> s5;
? 32-bit, word-addressablememory port? Address: MAR register?Data (R/W): MDR register
? 8-bit, byte-addressablememory port? Address: PC register?Data (R): MBR register
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Memory structure
?Sequence of cells with consecutive addresses?Cell size, most commonly 8 bits = 1 byte ?Bytes are grouped into words?~ the size of which most instructions operate?Most commonly today, 32 bits or 4 bytes
0
1
2
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Memory structure
?How do we read the bytes of a word??Big endian?Little endian?Mic-1 uses little endian
0 1 2 3
3 2 1 0Big end
Little end
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Memory structure
?MDR = M[MAR]?M[2] -> ABCD
?MBR = M[PC]?M[2] -> ---C
3 2 1 00
1
27 6 5 4
11 10 9 8A B C D
S T U V
D C B A
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MBR register
?MBR holds 8 bits read from memory?When written on to the B bus (32 bits) there are
two options:?Unsigned?B[7:0] = MBR, B[23:8] = 0b000000000000000000000000
?Signed (sign extension)?B[7:0] = MBR, B[i] = MBR[7] for i = [23:8]
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IJVM memory model
? Constant Pool? Cannot be written by an IJVM program? Contains constants, strings and pointers? CPP register contains the address of the first word
? Local Variable Frame? Each invocation of a method results in an allocation
for storing variables during the lifetime of theinvocation
? LV register contains the address of the first location? Operand Stack? Allocated directly above the local variable frame? SP register
? Method Area? Contains the program ”text”? Treated as a byte array
?Using simulation directives? $display(”The value of a is ”, a);? $display(”The value of a is ”, $bin, a);? $display($cycle, ”The value of a is ”, $bin, a);
?Has to be used inside sfg’s?$display, like printf in C, is very effective
but may be difficult to manage!
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Debugging gezel designs
demux
mux
regA regB
ALU
Logger
log
$display ?
$display
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Debugging Gezel designsdp logger( in in_a : ns(32);in in_b : tc(32);in in_c, in_d : tc(12);in log : ns(1) // Debug information, activated only when log is on
){reg activate : ns(1);
sfg nop { activate = log; } // tells to report on next cyclesfg rep {
registers are updated at the end ofa cycle, so the test will be on the
old values!
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Gezel register update
?We can solve the problem of register update, by splitting the basic block into two states.?One state doing the calculation?One state doing the test based on results from