Mexico 3070 user group meeting 2012 test coverage john

3070 User Group

Meeting 2012

IMPROVING TEST

COVERAGE

Agilent Measurement System

Division

John Pendlebury

Applications Engineer

September 14, 2012

1

2

Agenda

1. Boundary Scan Test (3070 has full compliant, BSDL, Tricks and Treats)

2. CET for no access (example video memory device)

3. Device programming (u Processors, Automotive board devices, Serial prom, nand flash)

4. ISP inside the Control XTP Card

5. DLLs

2

Features of our i3070 over the decade

9/14/20123

i3070 Software Updates

Throughput Coverage Ease of Use

i30

70

S5

2012 Rel 8.30PLED Test Ext DLL

Windows 7

2011 Rel 8.20P60V Zener

N5747A Pwr Supp Unit

2010 Rel 8.10PDC test for big Caps

RP5700 PC100KHz & 200KHz for small Caps

CET on IC

2009 Rel 8.00P ASRU N "AS"Utility card Pwr Monitor

High Pwr Channels

TestPlan AnalyzerFlexible Pwr ChannelsFixture Pwr Supp

i30

70

2008 Rel 7.20P VTEP v2.0 CET VTEP enhanced guarding

2008 Rel 7.10P VTEP speed up 1149.6 Enhanced Log record

2007 Rel 7.00PIPG enhancedAuto Optimizer

VTEP v2.0 NPMSwitch btw Mux : UnmuxBrowser Pin locator

i30

70

S3

2006 Rel 6.00P XW4200 PC

New GUI FPY, Worst ProbeAutoDebugWinXP

2005 Rel 5.40P iYET iVTEP

2003 Rel 5.30PNAND/XOR Tree Pattern

VTEP

Coverage AnalystUser Fixture Component

ScanworksGUI Localization

2001 Rel 4.00P-5.20P 50% faster in sys diagISP suite

ControlXTP - SW5.0Auto Si nailsWindows NT

< 2001 < Rel 4.00Panel Test

Throughput MultiplierTestjet

Diagnostic Capability for Coverage Definition

Problem: If the ddr memory doesn‟t work…

A: 70% memory read/write test.

B: 100% boundary scan test. (if memory supports)

C: 90% VTEP test.

Which test method identifies the defects below?

-Memory module failure

-DIMM connector failure

-Trace failure between CPU and memory.

-CPU memory unit failure.

Must understand

Diagnose- ability behind Coverage

Definition

A

C

A,B,C

maybe A

100% always works ??

5

Defining test coverage varies from test Engineer to test engineer. Lets start with some basic degrees of test coverage:

1. No test coverage

2. Presence

3. Presence and orientation

4. Right part and orientated correctly

5. Right part and some of the pins are tested

6. Right part and all of the pins tested but not all of the part functions have been tested

7. All of the part‟s functions have been tested

8. Part has been functionally tested

9. Part has been tested at speed

March 3, 2010Page 5

Common Defects in Process Test

Presence Correctness Orientation

+ - - +

Live Alignment

OpenShort Quality

Not presence Wrong correct device If polarized,

it‟s revised or

rotated

Dead, Not working

(not a full functional

qualification)

Not centered,

With skews or

small rotations

unwanted continuity

to other nearby

connection points

malformation, excess or

inadequate solder, cold

solder voids, etc

lack of continuity

between the board

and device

connection

These consist of the most

comprehensive process test

coverage formula

PCOLA-SOQ

Component on the PCB

Solder Connection point of device to PCB

From Ken Parker “A New Process for Measuring and Displaying

Board Test Coverage”.2002

7

Some of the tools that the 3070 has to increase test coverage

• Automatic generation of test for unpowered analog.

• VTEP and IVTEP to include Drive Through

• Digital and Powered Analog test developed through test models

• Boundary-Scan (simple and advanced)

• Coverage Extend (combination of VTEP and Boundary-Scan)

• Silicon Nails (combination of digital test and Boundary-Scan).

• Agilent Bead Probe

• NPM

• Polarity Check

• Ability to program devices (EEPROM, Flash, ISP) with both static and

dynamic data.

• The ability to allow the test engineer to write tests to cover unique

situations (analog cluster, digital cluster, digital drive through)

• Coverage Analyst Report

• Test Access Consultant

January 24, 2007

Measurement Systems Division

Page 7

8

Do not need to understand the

Device Function (Core Logic)

Tester applies Data on inputs. Cells

capture data on inputs. Data

scanned out TDO for verification.

Scan data in TDI to Output cells.

Tester verifies data on outputs.

To Test the Connectivity of each IC pin

An International Standard Defined by IEEE,

As IEEE 1149.1 from 1990

What is Boundary Scan ?

Core

In_

1

In_

2

Out

_1

Out

_2

TDI TDO

Save test access when in Bscan chain.

9

Why IEEE 1149.1 ?

IEEE, approved 1149.1

In 1990

We Talk About IEEE 1149.1

In 2012What is IEEE1149.1?

Where is IEEE1149.1 used ?

What is the challenge ?

What is the solution?

?

10

The Industry Challenges for Process Test

Intel Testing Forum 2008 at Taipei :

Challenges: Smaller Size, HDI, High Speed Signal Trace

Results:

No Space for Test Access

Traditional Test Pad create distortion in high speed signal

* *

*

**: Picture from Intel Testing Forum 2008 Taipei

11

SOC IC

Functioning

IEEE 1500

approved

Memory IC

Functioning

IEEE P1581

Discussing

Boundary Scan History in IEEE

IC/PCB

connectivityModule/Sys

Interacting

In-System

Programmin

g1990

1991

1992

1993

1994

1995

1996

1996

1997

1998

1999

2000

2001

2002

2003

2004

2005

2006

2007

2008

IEEE 1149.1

approved (single-

end digital)

. . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . .

IEEE 1149.1

add BSDL

. . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .IEEE 1149.1

Revised. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . .

IEEE 1149.5

approved

IEEE 1149.4

approved

(analog signal). . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . IEEE 1532-2000

approved. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . .

IEEE 1149.1

Revised IEEE 1532-2002

approved. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . IEEE 1149.6

approved (AC-

differential )

. . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . .. .

IEEE 1149.7

Discussing

Test Standards Description Purpose/Target Device

Boundary-scan testing methods to

enable digital IO stuck-at fault

detection for IC interconnect defects.

Digital device with boundary-scan enabled IO pins and

supports the JTAG test port of 4 pins that is accessible to

probing.

Boundary-scan controlled mixed-signal

testing interface

Additional test pins (2 additional) to support analog AC/DC

measurements through enabled IO pins.

Boundary-scan extension to support

testing of “Advanced” IO pins.

Enables boundary-scan testing of high-speed differential (DC

or AC coupled) IO pins, especially SERDES pins.

In-system programming (ISP) through

boundary-scan interface

Allows concurrent programming of large memories (typically

non-volatile) within programmable logic devices.

Boundary-scan extensions to support

complex device initialization and post-

test pin quiescence.

IO interfaces and power management features in today‟s IC‟s

require more sophisticated initialization sequences to prepare

the device and PCAs for safe/reliable testing.

Boundary-scan extensions to support

vector-less open fault measurements.

Enable IO pins to selectively toggle digital state to enable AC-

coupled capacitive sensor (no direct electrical probe access) to

measure solder open defects.

I/O Loopback testing for devices that

commonly do not have 1149.1.

Enables boundary-scan IC‟s to validate interconnections to

attached memory devices with loopback test.

Boundary-scan extensions to support

efficient access to user-defined

registers and internal instrumentation.

Enables description and much more efficient access to IC

BIST and Embedded Measurement capabilities increasingly

designed into complex IC‟s.

Some NEW Proposal from iEEE

13

DFT for Boundary Scan Test

Rule #1 TCK Pull-Down, TMS Pull-Up

Rule #1.1: Pull-down R for TCK.

Connect TCK through 100 ohm resistor to Ground. For low voltage logic(<1.5volt), The Designer may use 50 ohm resistor.

Rule #1.2: Pull-Up R for TMS.

Connect TMS through 1.2Kohm pull up resistor to high.

Note1: The TDI, TDO, are also suggested to have proper pull-up resistor to Vcc, So to have a stable input and output signal. The Resistor could be 100 or 50ohm as TCK. Or other values, like several K ohms.

Note 2: If TRST# is used here, A high R ( like 1.2K or even higher ) to Vcc can be used here . Some ICs may use pull-down resistor. In that case, user needs to keep TRST# in high during bscan testing.

Note3 : User may reference the IC Design Document to see the exact resistor suggestion from the IC designer. Generally, the pull-Up resistor is recommended from many ICs. But some will require a pull-down R instead. Be sure to reference the design-guide document..

Note4: User can consider to change the value of pull-up/down resistor here, The value of resistors may impact the overall power consumption. Lower value resistor requires stronger external driver capability. Pay attention here when changing test platform.

Bscan

Cells

Core

Logic

TDI TDO

TMSTCK

TEST ACCESS

PORT

CONTROLLER

(TAP)

1.2K

Ohm

+Vcc

+Vcc

Test

Access

100 or 50

Ohm

TRST#

1.2K

Ohm

+Vcc

RR

14

DFT for Boundary Scan Test

Rule #2 Chain Boundary Scan Devices in Order

Rule #2.1: TDO connects to TDI in serial

Connect 1st Boundary IC’s TDO to 2nd Boundary IC’s TDI , 2nd IC’s TDO to 3rd IC’s TDI…etc.

Rule #2.2: TCK , TMS connects in parallel

Connect all TCK and TMS in parallel.

Note1: In some cases, when the board designer has more flexibilities in layout arrangement and if there is a new, unverified Boundary IC, We suggest to put this IC be end of the Bscan chain.

Note2: For any IC, It‟s good to keep TDI away from TDO to avoid possible “short” between TDI/TDO. Board designer may consider to keep a proper distance under the overall space consideration.

Note3: If more ICs in the chain, The TCK, TMS propagation may not be effective as in lesser-IC-chain. In that Case, User may consider to put Buffer Circuitry for TCK/TMS, To get a better TCK/TMS synchronization.

U1

U3

TDI TDOTCK TMS

U2

TDI TDOTCK TMS

TDI TDOTCK TMS

#2.1

TDO-TDI in

serial

#2.2

TCK-TMS

in parallel

15

DFT for Boundary Scan Test

Rule #3 Level Shifter When Different Logic Level

Rule #3.1: Test Access on EVERY TDI, TDO, TCK, TMS

Test Access on EVERY TDI, TDO, TCK, TMS. (and TRST if the IC has TRST pin)

This is a MUST request for debug-purpose.

If possible, Put one access in interconnect pins, This can help to understand the out-putting signal situation when debugging the interconnect test.

Rule #3.2 : Check IC’s Logic Level

Put Level Shifter between ICs, If the ICs operate in different logic level. Don’t forget to put the TAP(TDI, TDO, TMS, TCK) pins into Logic-level shifter

Note : When we have >3 ICs in the chain, We may consider to put jumpers in middle ICs TDI,TDO pins. This can help to bypass not-working Bscan IC, and still make the whole chain work.

If putting a jumper on the board is not allowed, The ICT engineer can put a GP relay or direct wiring inside the fixture to bypass the middle IC.

U1

U3

TDI TDOTCK TMS

U2

TDI TDOTCK TMS

TDI TDOTCK TMS

#3.1

Test Access

for TAP,

and One

access in

interconnect

pins

#3.2

Logic

Level

shifter

when ICs

in different

logic levels.

Level

shifter

16

DFT for Boundary Scan Test

Rule #4 Additional Access from BSDL

Rule #4.1: Special Access for

Compliance_Patterns from BSDL

file

Some ICs have special enabling

pins, These pins can be found in

BSDL file. Search

“Compliance_Patterns”. To see what

pins need to be triggered for

smoothly turn-on Bscan mode.

In this example, The nodes:

PWRGOOD, DPRSTPB,

Need Test Access for keeping “high”

Rule #4.2: Special requirements in

DESIGN_WARNING message

1149.1 allows IC to have special

notes in BSDL with

DESIGN_WARNING message, User

needs to check this message to see

whether there are special

17

DFT for Boundary Scan Test

Rule #5 Access for Disabling Surrounding Devices

Rule #5: Access for Disabling

Surrounding Device

Experience showed :Without

disabling the surrounding devices,

especially the CLK generator, the

Boundary IC sometimes, can not

function under Bscan mode. Or

functioning with

unstable/unpredictable errors.

Therefore, We recommend to

disable the surrounding devices,

especially the “Clock Generator”.

For the disable pin, the designer

need to put pull-up (or pull-down)

resistor and a test access on it.

Bscan IC

CLK Gen

TDI

TDO

TCK

TMSCLK

POWER_disable

Access here to Disable

CLK Gen

R

18

DFT for Boundary Scan Test

Rule #6 Bscan Access on Bottom-Side

Rule #6:Pull BScan Access on Bottom-

Side of the Board

Put the TDI, TDO, TCK, TMS,

TRST access on Bottom-Side of the

board, So that these pins will be

probed from bottom part of the

fixture.

Due to shorter signal path and not-

through transfer-pins, probing from

bottom part of the fixture will have a

better signal integrity, and more

accurate for the probe to hit the test

pad.

Experience showed: Probing TAP

pins from bottom side, will result in a

more stable Bscan Testing.

Some Bscan Validation “Connector”

need to be on top side, That will be a

exception.

TDI TDO TCK TMS TRST

Probe from Bottom Side

Not Probe from Upper Side

TAP access should be Test Pad, Do NOT thru Via hole,

Test Pad size should >30mils at least; with 100mils probe

19

VTEP Family Innovation

No Test Access

SolutionIC

(Sensitivity)

Connector

Signal Pin

(Sensitivity)

High Speed

Connector

GND Pin

YES

>20fF

YES

>20fF

1993 TestJET

YES

>5fF

YES

>5fF

2003 VTEP 5.3

YES

<5fF

YES

>5fF

2005 iVTEP 5.42

YES

<5fF

YES

>5fFYES2007

NPM

VTEP v2.0 7.0

YESYES

<5fF

YES

>5fFYES2008

Cover-ExtendVTEP v2.0 Powered 7.2

SW

VersionYear Innovation

20

MDA with TestJET

ICs:

Tested Pins: 482 Testable: 1201 Coverage:41%

Connectors:

Tested Pins: 260 Testable: 450 Coverage:58%

I1000 with VTEP(iVTEP)

ICs:

Tested Pins: 1168 Testable: 1201 Coverage:97%

Connectors:

Tested Pins: 445 Testable: 450 Coverage:98%

DDR2 :Vcc/GND covered

sATA :Vcc/GND covered

Note: Testable pins =Total pins –Vcc-GND- No Access- same nail pins

VTEP

Testjet

σ = 0.3

σ = 1.7

Coverage 2.36x better

TestJET vs VTEP

21

The Digital Way to Test

Device under test

Device is powered up

Digital

Driver

Digital Receiver

Vcc

0101

Function LibTree TestBscan Test

0

Good Power Up Sequence

Verified IC LIB/BSDL Minimized Noise Interference

22

Comparison Analog Way:

TestJET/VTEPDigital Way: Boundary

Scan

Coverage

Test Access

Required

Programming Time

Cost

IC Type

Noise Immunity

Test Time

Good Good

Moderate Fast

100% 100% for single IC <50%

for IC chain

Standard in Tester

USD1K more in fixture

Need License in Tester No

extra cost for fixture

No restriction in IC type IC must be 1149.1-capable

Moderate Moderate to Good

Auto Generation <1hour 1-2 day

Debug Effort Easy More Effort

False Call Rate Moderate, Adjustable Low

23

Boundary Scan

deviceConnector or

other device

TDITCK

TMS

TD0

VTEP

sensors

to ICT tester …

Test Access pins

NEW !! Combining Analog VTEP + Digital Bscan

Cover Extend Technology

Extend Bscan Coverage from

Bscan IC to Adjacent Non-Bscan Device

Remove Test Access

Increasing Test

Coverage at ICT

In-System Programmable

Device Solutions

25

What is ISP?

The term In-System Programming (ISP) refers to

programming of programmable devices after they are

soldered onto a PC board.

This includes both FLASH and Programmable Logic

Devices (PLDs) as well as other devices.

25

FLASH & PLD market growth

WOW !

Flash memory is now found in 70% of PCBA‟s built today.

0

0.5

1

1.5

2

2.5

3

3.5

0

2

4

6

8

10

12

14

16

18

20

2009 2010 2011 2012 2013 2014

Un

its (

Billio

ns)

Do

llars

(B

illio

ns)

PLD $ FLASH $ PLD Units FLASH Units

26

27

In-System Programming Profile

• Flash memory devices are used on more than 70% of PCBA‟s

manufactured today.

• Programmable Logic Devices (PLD, CPLD, SPLD, FPGA are

used on more than 40% of PCBAs manufactured today.

• Usage for both is growing rapidly.

• Logistics issues are driving manufacturer‟s to program these

devices after mounting onto PCBA‟s (In-System

Programming).• Rapid production turn-around (time-to-market).

• Reduced inventory.

• Facilitate engineering changes.

• Post manufacturing repair and reprogramming.

27

What ISP Devices Can We Address with i3070?

Type of Device Programmable on the i3070?FLASH YES.

EPROMs/PROMs YES. But requires extra voltages on the

board.

CPLDs YES.

FPGA (RAM based) YES, but why would you want to do this?

Configuration EEPROMS YES.

Serial EEPROMs YES.

PAL/GAL YES, but it depends on the device.

28

29

• Support of larger devices (>256Mbit)

• Much faster first run time than Flash70

• Faster mature run time than Flash70

• Much smaller object file size

• Much less testhead memory required

• No dependency between repeat loop count and segment size.

• Automatic repeat loop (go until end of data).

• Flag bad checksums on data records (S-record and Intel Hex)

• Summary information of data image compilation:

– The number of bytes programmed

– The number of bytes stripped (“FF stripping”)

– The total number of segments

– Compiler flags turned-on or off

– The Minimum and Maximum addresses used

Description of Flash ISP features

29

Example of Summary Information

30

31

Description of PLD ISP features

• Ability to program PLDs directly from:

– Serial Vector Format (SVF) file

– Standardized Test And Programming Language (STAPL) file

– Jam file

– Jam Byte Code (JBC) file

• No need to convert to PCF/VCL file(s).

• Much Faster compile time.

• Much less files to keep track of: VCL file plus data file.

• Single test programming - no resistors in the fixture.

• Print statements in Jam or STAPL files will output to BT-Basic window.

• We can now program “non-F” Altera parts.

31

Block Diagram showing Flash ISP Memory

Directory Ram

Sequence

Ram

Vector Ram

Vector Ram

Vector Ram

Sequence

Ram

MU

X

Data

Translation

Acceleration

i3070

Image DataItems in BLUE are found only in

Control XTP card.

32

33

How do we do it? FLASH

Flash Software paradigm:

• Pass address/data image file to testhead with programming algorithm information (we now have a Flash “Player”).

• Results in MUCH smaller object file and, as a result, less time required for first run time download.

• Changed method of downloading image and object files to testhead by bypassing the system card.

• New software structure allows for easier support of new data file formats and Flash data image manipulation.

• Two compiles happen “Behind the scenes” :

– Convert data format to i3070 image

– Create i3070 programming algorithm object file

33

VCL syntax - Example of Flash ISP

flash isp ! Instead of “flash”

assign Data_Bus to pins 4,3,2,1 ...

. . .

vector V1

set . . .

end vector

. . .

flash assignments

file “1Mx8.data” srecord

data My_Data to groups Data_Bus

address Addr to groups Addr_Bus

eod reuse

end flash assignments

. . .

unit

execute V1

segment hexadecimal “400”

repeat ! Automatic Loop

execute V2 drive data Addr

execute V2 drive data My_Data

execute Write

execute End_Cycle

homingloop

execute RY_Done exit if pass

end homingloop

next Addr

next My_Data

end repeat

end segment

end unit

34

35

Process to convert existing Flash70 test to new Flash ISP test

1. Enable the Flash ISP software in the config file (enable flash isp).

2. Make a backup copy of the original file!

3. Change „flash‟ keyword to „flash isp‟.

4. Change „data/end data‟ block to „flash assignments‟ block:

a. Change the „file‟ statement to new syntax.

b. Point to Data bus group with „data‟ statement.

c. Point to Address bus group with „address‟ statement.

d. Make sure the “end-of-data” action is defined.

As long as you do not have multiple different vectors trying to drive

address or data, you should now be done (see “Limitations” section).

35

36

Limitations - Flash ISP

• Address bus width limited to 32-bit (4G addresses)

• Data bus width limited to 128-bit if drive or receive data only or 64-bit if both drive and receive data (i.e., Data Polling).

• Cannot drive Address and Data on the same vector (example, execute V1 drive data Address drive data Data).

• Cannot have different vectors to drive address or data (e.g., execute V1 drive data Data, execute V2 drive data Data).

• Entire Flash image must reside in testhead memory.

• Cannot handle parameter passing (i.e., serial number, NIC, etc.).

• Only one “flash assignments” block per test. This means only one data file can be accessed.

36

37

Success Factors for Programming

1. Make sure you have proper testability:

• Full access for Flash and disable nodes

• Easy disable methods

2. Use Ground Plane in the fixture.

3. Specify TAP pins with “Critical” attribute in Board Consultant!

4. Make sure PLD programming data files were generated with Bscan

chain defined. You can download the programs to create the

SVF/Jam/STAPL files from the PLD vendor‟s web sites.

5. Remember, if you have an ECO to the data file for Flash ISP, you

must recompile with the new data file.

37

Agilent Restricted

March 2009

Questions and Answers

Page 38

39

40 Page 40

Typical Debug Problems on Boundary Scan

•Ground Bounce

•Bad BSDL data file

•Topology Errors (from CAD translation)

•Standard Digital disabling problems

From Mike Farrell

41 Page 41

Ground Bounce

• Cause: too many pins change state at once for the board and fixture‟s power & ground capability (Note: Use short wire fixtures with good grounding.)The board “ground” node spikes relative to tester ground which creates a signal spike at clock inputs.State machine jumps ahead due to unexpected spikes on clock input

• Break up into tests with fewer pins transitioning – Max Connect option

• Ground bounce suppression option

• Potential issue of noise on the board – Voltage regulators one source.

• Ground plane is a good choice for helping with this problem.

• Twisted pair wiring might be needed.

• Time for a scope on the TCK line.

Ground Bounce Debug

From Mike Farrell

42 Page 42

Potential Problems With BSDL Files

•The BSDL will not compile due to syntax issue(s)

•Wrong boundary-scan register length – number of cells in the chain.

•Wrong ID code value.

•Pin order for a section is wrong (reversed).

•The BSDL file does not match the actual silicon.

•The part is non complicate with the 1149 standard – may require special vectors or pins to allow the boundary-scan section to work

•The part has multiple boundary-scan chains internal to the part. Seeing more and more of this.

•Wrong cell type assigned to the associated pin.

•Instruction code is wrong.

•Wrong or older BSDL file is being used.

From Mike Farrell

43 Page 43

1149.6 – AC Signal Detection

- Coverage on AC-coupled differential signals- Compliant to the IEEE 1149.6 standard

- More designs are going hi-speed (> GHz) eg DDR3- Uses more of these type of architecture

Capacitors tested for presence

Traces and pins tested for connectivity

From IEEE Document “1149.6 IEEE Standard for Boundary Scan Testing of Advanced Digital Networks

From Mike Farrell

44

Benefits of Advance Boundary-Scan

•Quick and easy way to generate test model for complex device.•Use an industrial standard (1149).•Ability to break large devices into multiple tests to reduce test resource requirements.•Ability to chain number of devices together and test with a standard method.•When boundary-scan devices are chained, a method to help gain test coverage with reduced test access.•Programming ISP devices.•Potential to testing non boundary-scan devices with silicon nails.•Coverage Extend•Potential for running built in self test (BIST). •Will start seeing chips with built in measuring devices (embedded) that will be controlled by boundary-scan.•Potential for testing high speed lines with capacitance coupling (1149.6).

Page 44

From Mike Farrell