Merging Synthesis With Layout For Soc Design -- Research Status Jinian Bian and Hongxi Xue Dept. Of Computer Science and Technology, Tsinghua University,

Merging Synthesis With Layout Merging Synthesis With Layout For Soc DesignFor Soc Design

-- Research Status-- Research StatusJinian Bian and Hongxi Xue Jinian Bian and Hongxi Xue

Dept. Of Computer Science and Technology, Dept. Of Computer Science and Technology,

Tsinghua University, Beijing 100084Tsinghua University, Beijing 100084

2002.3.282002.3.28

Contents

The progress status of our work. Delay-driven algorithm for logic re-synthesis

after placement Interconnect driven high-level synthesis.

– Data path synthesis– Control synthesis

Progress Status of Our Work

System specification– IIR into HDM

Internal Intermediate Representation– C to VHDL :

– HDM (IIR) to CDFG

FFT.vhd PackageFFT.c

Progress Status of Our Work

Interconnect synthesis– Delay-driven post-layout re-synthesis – Interconnect driven high-level synthesis

» Data path synthesis combining with floor-planning

» Delay driven control synthesis

Progress Status of Our Work

HW/SW partitioning– Partition modeling– Partition algorithm

» Simulated annealing algorithm» Tabu algorithm» Search space smoothing algorithm

– Partition system

Interconnect Driven Synthesis

Background

– Interconnect wires play the dominating role for circuit performance and area instead of function units.

Interconnect Driven Synthesis

Traditional Flow

Our Approach

Hardware Spec.

High-Level Synthesis

Floor-planningRT-Level Synthesis

Logic Synthesis Global Placement

Re-Synthesis

Incremental PlacementDetail Placement

Routing

Delay-driven Post-layout Re-synthesis

Re-synthesis

Logic Synthesis

Placement

Detail Placement and Routing

Re-Synthesis+

Incremental Placement

Our System Flow

Delay Calculation

Using the method in the placement When get a new gate, allocate it to an

ideal position

Buffer Insertion

A

(a) Before buffer insertion

BC

BC

A

(b) After buffer insertion

Gate Resizing gate_resize() foreach gate g in the circuit{ if (g is non-critical) continue; if (g’s better alternative gate n not exist) continue; replace g with n; re-calculate the delay of the circuit; if (delay is not reduced) recover g; }

Alternative Wire

a

c

b

a

c

b

abaccacbacca

Local Logic Substitution

a g3

c g4

b y

Uses the model mapping method to search for the local alternative circuit

a g1

c g3

y b g2

Local Logic Substitution

a

b

c

d

cdcbabbacdba )()(

a

b

c

d

Local Logic Substitution

The critical path may be shorten,– eg: if the wires marked red are critical p

ath, in the alternative circuit, the path is shorten, but the non-critical path (follows input c) is lengthen

a

b

c

d

a

b

c

d

Experimental Results

Result Graph

0

20

40

60

80

100

120

1 2

orgre- synthesi sed

Conclusion

Our system begins with the circuit after the initial placement and performs local re-synthesis to reduce the delay.

A final netlist and placement are then generated after the incremental placement.

The result shows the system is a fine combination of synthesis and physical design. The future work may be replacing the greedy algorithm with the heuristic algorithm.

Interconnect Driven High-level Synthesis

Behavior Description

Entity example is

Port( a,b,cin: in bit; S,cout: out bin);

End example;

Architecture behavior of example is

Begin

If a=‘1’ and b=‘1’ and cin=‘1’ then s <= ‘1’;

Elsif ……

……

End;

BEHAVIORDESCRIPTION

VHDL

Behavior Synthesis

Data Path

Controller

CDFG

layoutlayout

HDM-IIR

Problems to Be Solved

How to get information of interconnection delay at higher level?

How to bind floor-planning with high-level synthesis together?

How to achieve an accurate result with limited time?

Our ApproachCDFG & Restriction

EstimateSteps & Resources

Make Grids Make CBL

Simulate Annealing

Result

Heuristic Algorithm SSS

Hardware Spec.From HW/SW

Representation of Scheduling and Binding Result Using a Two –Dimensional Table

Get a New Solution by Changing the Placement of the Table

Select one operation randomly, changes its column.

A B D

C

E

A B C

D

E

Select one operation randomly According to the step range of the operation

calculated by ASAP and ALAP algorithm, select a new row to place the operation randomly

Adjust the rows of the operations that violate the precedence constraints, finally, decide the columns of these operations .

A B D C E

A B D C E

Corner Block List

We use CBL(Corner Block List) to show the result of floorplan.

CBL is based-on non-slicing floorplan.

3

4

5 6

1

27

Example:Seq=(1234567)L=(010011)T=(10010010)

Example:Seq=(1234567)L=(010011)T=(10010010)

Corner Block List

The most important thing is – Any (S,L,T) is validate!!!

We can get new floorplan-solution by changing the (S,L,T) group.

Controller Synthesis

CDFG Data Path

FSM

State Simplification

State

Assignedplacement

State Assigned

Various-length state assigned algorithm

e.g. 10 states: 4-10 bits,

The optimal solution:

How many bits?

How to encode?

Conclusions

By binding and floor-planning into a single phase: We can obtain more accurate information of

interconnections in high-level synthesis. The floor-planning can benefit from the

information of scheduling and binding There are still much work to be done on how to

use the information to avoid randomness of the simulated annealing approach.

The Future Work

Combine HLS with the result of HW/SW. Use different algorithms instead of

simulated annealing algorithm.– Heuristic algorithms– Search space smoothing– Using re-timing technique

Thank You !!!