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MEMS Manufacturing Consortia
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MEMS Manufacturing Consortia - Adaptive optics

Feb 03, 2022

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Page 1: MEMS Manufacturing Consortia - Adaptive optics

MEMS Manufacturing Consortia

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Barriers

• Most Micro-Electro-Mechanical Systems(MEMS) applications are low to mid-volume• Few applications have sufficient volume tojustify process development costs & the largecapital investment and burn run rate fordedicated fabrication infrastructure• Lack of standards requires development ofnew design rules for each new application

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• Develop a broadly enablingoptical MEMS manufacturingprocess

• Multiple applications fabricatedtogether on the same wafer

• Common design rules

• Common modeling tools

• Foundry model

Objectives

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MEMS Processing

Bishnu Gogci, Sensors Product Division, Motorola

Tronics

NMRC

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• Manufacturability (bulk vs. surface micromachining)

Materials properties (E, ν) (bulk +, surface -)

Optical (λ/20, r, t) (bulk +, surface -)

Design Freedom (bulk -, surface +)

• Integration of light sources

Si good for micro-electro-mechanical

GaAs good for light emission

Process Challenges

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A bad day at MCNC

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• Implement a polysilicon surfacemicromachining process on top of a bulkmicromachined SOI wafer

• Use the single crystal silicon device layer ofthe SOI wafer for critical optical, electrical,and mechanical applications

• Use polysilicon layers for non-criticalapplications such as hinges and guides

• Use hybrid integration for active devices

Hybrid MEMS Process

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Hybrid MEMS Process

Bulk Micromachining Surface Micromachining

Hybrid Micromachining

SCS

Substrate

BOX

Poly1PSG 1

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Applications

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Overcoming the Barriers• Developed a broadlyenabling, flexible hybridMEMS fabrication process

• Shared development &fabrication costs over multipleapplications

• Common design rules &modeling tools

• Foundry model at a not-for-profit

Infotonics Technology Centerwww.infotonics.org

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MEMS Adaptive Optics

Goal• MEMS AO offers potential for mirror arrays with

thousands of independently controlled actuators at a cost ofless than $1k per device rather than $1k per channel

Barriers• MEMS are expensive in the development stage

– 11 different development efforts• Current MEMS AO solutions are unique

– Only mass production will be able to bring down cost– Reaching mass production volumes will require aggregating

individual demand volumes– Aggregating individual demand volumes will require a common,

broadly enabling fabrication process

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TronicsSOI MicromachiningCEA LETI

MCNC/MUMPs, SandiaSurface Micromachining MUMPs,SUMMiT IV

AFRL/USAF/AFIT

JPLMembrane Transfer TechnologyJPL

Delft UniversityBulk Silicon MicromachiningOKO Technologies

NASA/JPLSurface ElectroformingMEMS Optical

Sandia?Bulk Silicon MicromachiningIntellite

Stanford/CISSOI wafer bondingStanford Microphotonics Laboratory(SML)

FairchildSUMMiT V Surface MicromachiningProcess

MEMX

NJNCSurface MicromachiningLucent

UC Berkeley/BSACSurface Micromachining/SOI bondedmirrors

Iris AO

MEMSCAPSurface Micromachining/SOI bondedmirrors

Boston Micromachines

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Fields of Use• Astronomy• Terrestrial Imaging• Vision Science• Biomedical Imaging• Laser-Based Communications• Industrial Lasers• Target Recognition & Tracking• Spatial Light Modulators (Displays, Projectors, Telecom)• Microelectronics (Photolithography, XUV)

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Overcoming the Barriers

• MEMS are expensive in the development stage– Work together in a "pre-competitive" development

stage (process, yield, packaging, reliability)

• Current MEMS AO solutions are unique– Aggregate individual demand volumes using a broadly

enabling fabrication process

– Cooperate in generating value

– Compete in dividing it up in the different fields of use

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Back-Up Slides

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Flip-Chip Bonding for AO

• Eliminate need for sacrificial oxide to define gap• Flexible gap size enables long stroke (>15 µm)

• Eliminate sacrificial etch (interactions/selectivity) and etchrelease holes (diffraction)

• Single crystal mirrors, arbitrary mirror thickness

• Straightforward path to high-yield integratedmicroelectronics (mature CMOS process, known good die)

• Enables re-work of defective units, tiling for large arrays

• Can fabricate all applications in the same process at thesame foundry to increase volume and decrease cost

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Flip-Chip Bonding

Counter electrode wafer

SOI mirrorwafer

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Metallization

Counter electrode wafer

SOI mirrorwafer

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Solder Application

SOI mirrorwafer

Counter electrode wafer

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Flip Mirror Wafer

SOI mirrorwafer

Counter electrode wafer

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Bond

Counter electrode wafer

SOI mirrorwafer

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Remove Handle Wafer

Counter electrode wafer

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Remove Oxide

Counter electrode wafer

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Blanket Metallization

Counter electrode wafer

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Iris AO

• (A) Mirrors are attached to asacrificial handle

• (B) Mirrors are aligned andbonded to the controlcircuitry using flip chipbonding

• (C) The sacrificial handlematerial is removed and themirrors are released

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CMOS Integration

Janusz Bryzek, Anthony Flannery,and David Skurnik, TransparentOptical

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Self-Aligning

Self-Aligned Assembly of Microlens Arrays with Micromirrors,Adisorn Tuantranont, Victor M. Bright, Wenge Zhang,Jianglong Zhang, and Y.C. Lee, SOIE 1999

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Business is War and Peace

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The Value Net

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Complementors & Competitors:The Supply Side

A player is your complementor if it’s moreattractive for a supplier to provide resources toyou when it’s also supplying the other player thanwhen it’ supplying you alone

A player is your competitor if it’s less attractivefor a supplier to provide resources to you whenit’s also supplying the other player than when it’ssupplying you alone