MEMS Foundry Design Rules - Silicon Sensing

MEMS Foundry Design RulesTo be the leading provider of affordable, high performance, high integrity

MEMS inertial products and foundry services

February, 2019

Silicon Sensing is a Joint Venture between Collins Aerospace and Sumitomo Precision Products

13mm

Possible area for alignment mark

40mm

96mm

30mm

6 inch

5 inch

4 inch

Alignment marks must be placed with the rectangular areas

Alignment accuracy• Both side alignment +/- 5µm

• Top side accuracy +/- 5µm

Field size• The size of alignment marks must be

within the rectangular area

320um 320um

450um

8 inch

50mm

174mm

18mm

Black; for 4,5,6 inch

Red; for 8 inch

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１のアライメントマーク　　　　　　　　　　　　マーク間隔：最大100mm

　　　　　　　　　200

仮想線(点線)との隙間10　　文字の太さ15・1文字の大きさは■と同じくらい十字の太さ＝50、幅・高さ＝170

　　この幅は成り行きで良い

いずれも60

２→１３→１７→１Ｒ→１

・・・・・・・・・・・・・・・・

Example for alignment mark

Mark for 1st layer

Room : 10µm

Your optional size

Cross thickness : 50µm, Height : 170µmFigure bold : 15µm

Distance : 96µm

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Second layer

２のアライメントマーク　　　　　　　　　　　　100mmの間隔

3～6まで、位置違いの同じマーク

　　　　　　　　　200

十字の太さ＝55、幅・高さ＝180

この幅は1のアライメントマークに合わせる

・・・黒が続く・・・

Mark for 2nd layer

3rd to 6th : Same

mark at different

position

Distance : 96µm

Black

Cross thickness : 55µm, Height : 180µm

Same as 1st layer

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Subsequent layers (example hole-making patterns)

7のアライメントマーク　　　　　　　　　　　　100mmの間隔

　　　　　　　　　200



・・・黒が続く・・・Black

Same as 1st layer

Mark for 7th layer


Distance : 96µm

5


Back side alignment mark

Ｒのアライメントマーク　　　　　　　　　　　　100mmの間隔

　　　　　　　　　200



・・・黒が続く・・・Black

Same as 1st layer

Mark for R layer Distance : 96µm


Position is the same as 1st layer

6


Alignment mark for back side Deep RIE

８のアライメントマーク　　　　　　　　　　　　100mmの間隔

　　　　　　　　　200



・・・黒が続く・・・

Distance : 96µm

Black

Same as 1st layer

- In Strict Confidence

Mark for 8th layer


7


Minimum dimension

Process Pattern Minimum Note

Si Deep

RIE

Slit CD 2.0µm Maximum aspect ratio is 30 and larger

ratios need to be confirmed.

Slit CD on SOI active

layer

3.0µm Maximum aspect ratio is 30 and larger


Trench CD on SOI active

layer

3.0µm Maximum aspect ratio is 30 and larger


Hole Φ5.0µm Maximum aspect ratio is 30 and larger


Pillar Φ2.0µm Maximum aspect ratio is 30 and larger


Maximum aspect ratio 100 L/S condition needs to be confirmed.

Angle 88～92deg

Taper Approx.

75deg

Uniformity through the wafer depends on the pattern.

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Minimum dimension


PZT etching Top electrode on PZT 3.0µm

In the case of PZT thickness 3.0µm

PZT top edge – top

electrode

5.0µm

PZT bottom edge –

bottom electrode

3.0µm

SiO2 etching L/S 2.0µm

Hole Φ3.0µm

Metal

(Milling)

Line CD 3µm The metal pattern must be away from PZT

structure with 3x distance of PZT thickness if

the metal pattern is close to the PZT

structure.

9


Design rule using a stepper


Exposure

with Stepper

M1500 UTS

Shot size ・38mm×11.4mm

・30mm×15mm

・21mm×17.5mm

Without alignment mark

Alignment mark must be located in this area

when necessary.

L/S 1.0µm In the case of photoresist thickness 1.0µm

Wafer size 6 and 8 inch

Photomask 5”×5”×0.09” - Two reticle alignment mark is necessary on

the edge.

- Mirror-reversed image

10


Accuracy assurance rule


Thin metal

film

Uniformity

In-house：Al, Au, Cr, Ti, Pt

Subcontractor : others

+/-5%

Not guaranteed

Oxidation Uniformity for

thermal or

sputter

+/-5%

+/-5%

Max 3μm

Max 1μm

PZT Uniformity +/-5% Max 5um

Si Deep RIE Depth through the wafer

Slit

Pillar

+/-5%

+/-0.5µm

+/-0.5µm

Depends on recipe

+/-0.1 is possible.

+/-0.1 is possible.

Metal etching

(Milling)

Minimum metal line CD 3µm The metal pattern must be away

from PZT structure with 3x distance

of PZT thickness if the metal

pattern is closed to PZT structure.

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PZT electrode etching rule

Minimum 0.5µm SiO2 is necessary for Pt or Au

etching as insulation layer.

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Edge exclusion for SOI

5mm

5mm black pattern from the edge is necessary to etch both sides of SOI wafer for all photomasks.

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For all enquiries,contact [email protected]

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MEMS Foundry Design Rules - Silicon Sensing

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