1 Memory Hierarchy Memory Hierarchy Original slides from: Computer Architecture A Quantitative Approach Hennessy, Patterson Modified slides by YashwantMalaiya Colorado State University Review: Major Components of a Computer Review: Major Components of a Computer Processor Control Datapath Memory Devices Input Output Cache Main Memory Secondary Memory (Disk) Processor - Memory Performance Gap Processor - Memory Performance Gap 1 10 100 1000 10000 1980 1983 1986 1989 1992 1995 1998 2001 2004 Year Performance “Moore’s Law” µProc 55%/year (2X/1.5yr) DRAM 7%/year (2X/10yrs) Processor-Memory Performance Gap (grows 50%/year) The Memory Hierarchy Goal The Memory Hierarchy Goal Fact: Large memories are slow and fast memories are small How do we create a memory that gives the illusion of being large, cheap and fast (most of the time)? n With hierarchy n With parallelism Fact: Large memories are slow and fast memories are small How do we create a memory that gives the illusion of being large, cheap and fast (most of the time)? n With hierarchy n With parallelism
10
Embed
Memory Hierarchy - Colorado State Universitycs270/.Spring16/slides/... · 2016-04-17 · Fast: Exploiting Memory Hierarchy — 15 Cache Misses On cache hit, CPU proceeds normally
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
1
MemoryHierarchyMemory
Hierarchy
Original s lides from:Computer Architecture
A Quantitative Approach Hennessy, Patterson
Modified s lides by YashwantMalaiyaColorado State University
Review: Major Components of a ComputerReview: Major Components of a Computer
Processor
Control
Datapath
Memory
Devices
Input
Output
Cache
Main
Mem
ory
Secondary M
emory
(Disk)
Processor-Memory Performance GapProcessor-Memory Performance Gap
1
10
100
1000
10000
19801983
1986198919921995
199820012004
Year
Performance
“Moore’s Law”
µProc55%/year(2X/1.5yr)
DRAM7%/year(2X/10yrs)
Processor-MemoryPerformance Gap(grows 50%/year)
The Memory Hierarchy GoalThe Memory Hierarchy Goal
Fact: Large memories are slow and fast memories are small
How do we create a memory that gives the illusion of being large, cheap and fast (most of the time)?n With hierarchyn With parallelism
Fact: Large memories are slow and fast memories are small
How do we create a memory that gives the illusion of being large, cheap and fast (most of the time)?n With hierarchyn With parallelism
2
SecondLevel
Cache(SRAM)
A Typical Memory HierarchyA Typical Memory Hierarchy
Control
Datapath
SecondaryMemory(Disk)
On-Chip Components
RegFile
MainMemory(DRAM)
Data
Cache
InstrC
ache
ITLBD
TLB
Speed (%cycles): ½’s 1’s 10’s 100’s 10,000’s
Size (bytes): 100’s 10K’s M’s G’s T’s
Cost: highest lowest
q Take advantage of the principle of locality to present the user with as much memory as is available in the cheapest technology at the speed offered by the fastest technology
Larger blocks should reduce miss raten Due to spatial locality
But in a fixed-sized cachen Larger blocks ⇒ fewer of them
More competition ⇒ increased miss raten Larger blocks ⇒ pollution
Larger miss penaltyn Can override benefit of reduced miss raten Early restart and critical-word-first can help
Larger blocks should reduce miss raten Due to spatial locality
But in a fixed-sized cachen Larger blocks ⇒ fewer of them
More competition ⇒ increased miss raten Larger blocks ⇒ pollution
Larger miss penaltyn Can override benefit of reduced miss raten Early restart and critical-word-first can help
1414
Increasing Hit RateIncreasing Hit RateHit rate increases with cache size.Hit rate mildly depends on block size.Hit rate increases with cache size.Hit rate mildly depends on block size.
10%
5%
0%
Cache size = 4KB
16KB
64KB
16B 32B 64B 128B 256BBlock size
mis
s ra
te =
1 –
hit r
ate
100%
95%
90%
hit
rate
, h
Decreasingchances ofcovering large data locality
Decreasingchances ofgettingfragmenteddata
Chapter 5 — Large and Fast: Exploiting Memory
Hierarchy — 15
Chapter 5 — Large and Fast: Exploiting Memory
Hierarchy — 15
Cache MissesCache Misses
On cache hit, CPU proceeds normallyOn cache missn Stall the CPU pipelinen Fetch block from next level of hierarchyn Instruction cache miss
Restart instruction fetchn Data cache miss
Complete data access
On cache hit, CPU proceeds normallyOn cache missn Stall the CPU pipelinen Fetch block from next level of hierarchyn Instruction cache miss
Restart instruction fetchn Data cache miss
Complete data access
Static vs Dynamic RAMsStatic vs Dynamic RAMs
Chapter 5 — Large and Fast: Exploiting Memory
Hierarchy — 16
Chapter 5 — Large and Fast: Exploiting Memory
Hierarchy — 16
5
1717
Random Access Memory (RAM)Random Access Memory (RAM)
Memorycellarray
Addressdecoder
Read/writecircuits
Address bits
Data bits
1818
Six-Transistor SRAM CellSix-Transistor SRAM Cell
Bit line
Wordline
Bit line
bit bit
1919
Dynamic RAM (DRAM) CellDynamic RAM (DRAM) Cell
Word line
Bitline
“Single-transistor DRAM cell”Robert Dennard’s 1967 invevention
Chapter 5 — Large and Fast: Exploiting Memory
Hierarchy — 20
Chapter 5 — Large and Fast: Exploiting Memory
Hierarchy — 20
Advanced DRAM OrganizationAdvanced DRAM Organization
Bits in a DRAM are organized as a rectangular arrayn DRAM accesses an entire rown Burst mode: supply successive words from a row with
reduced latencyDouble data rate (DDR) DRAMn Transfer on rising and falling clock edges
Quad data rate (QDR) DRAMn Separate DDR inputs and outputs
Bits in a DRAM are organized as a rectangular arrayn DRAM accesses an entire rown Burst mode: supply successive words from a row with
reduced latencyDouble data rate (DDR) DRAMn Transfer on rising and falling clock edges
Quad data rate (QDR) DRAMn Separate DDR inputs and outputs
6
Chapter 5 — Large and Fast: Exploiting Memory
Hierarchy — 21
Chapter 5 — Large and Fast: Exploiting Memory
Hierarchy — 21
DRAM GenerationsDRAM Generations
0
50
100
150
200
250
300
'80 '83 '85 '89 '92 '96 '98 '00 '04 '07
TracTcac
Year Capacity $/GB
1980 64Kbit $1500000
1983 256Kbit $500000
1985 1Mbit $200000
1989 4Mbit $50000
1992 16Mbit $15000
1996 64Mbit $10000
1998 128Mbit $4000
2000 256Mbit $1000
2004 512Mbit $250
2007 1Gbit $50
Chapter 5 — Large and Fast: Exploiting Memory
Hierarchy — 22
Chapter 5 — Large and Fast: Exploiting Memory
Hierarchy — 22
Average Access TimeAverage Access Time
Hit time is also important for performanceAverage memory access time (AMAT)n AMAT = Hit time + Miss rate × Miss penalty
Examplen CPU with 1ns clock, hit time = 1 cycle, miss penalty =
20 cycles, I-cache miss rate = 5%n AMAT = 1 + 0.05 × 20 = 2ns
2 cycles per instruction
Hit time is also important for performanceAverage memory access time (AMAT)n AMAT = Hit time + Miss rate × Miss penalty
Examplen CPU with 1ns clock, hit time = 1 cycle, miss penalty =
20 cycles, I-cache miss rate = 5%n AMAT = 1 + 0.05 × 20 = 2ns
2 cycles per instruction
Chapter 5 — Large and Fast: Exploiting Memory
Hierarchy — 23
Chapter 5 — Large and Fast: Exploiting Memory
Hierarchy — 23
Performance SummaryPerformance Summary
When CPU performance increasedn Miss penalty becomes more significant
Can’t neglect cache behavior when evaluating system performance
When CPU performance increasedn Miss penalty becomes more significant
Can’t neglect cache behavior when evaluating system performance
Chapter 5 — Large and Fast: Exploiting Memory
Hierarchy — 24
Chapter 5 — Large and Fast: Exploiting Memory
Hierarchy — 24
Multilevel CachesMultilevel Caches
Primary cache attached to CPUn Small, but fast
Level-2 cache services misses from primary cachen Larger, slower, but still faster than main memory
Main memory services L-2 cache missesSome high-end systems include L-3 cache
Primary cache attached to CPUn Small, but fast
Level-2 cache services misses from primary cachen Larger, slower, but still faster than main memory
Main memory services L-2 cache missesSome high-end systems include L-3 cache
7
Chapter 5 — Large and Fast: Exploiting Memory
Hierarchy — 25
Chapter 5 — Large and Fast: Exploiting Memory
Hierarchy — 25
Interactions with Advanced CPUsInteractions with Advanced CPUs
Out-of-order CPUs can execute instructions during cache missn Pending store stays in load/store unitn Dependent instructions wait in reservation stations
Independent instructions continue
Effect of miss depends on program data flown Much harder to analysen Use system simulation
Out-of-order CPUs can execute instructions during cache missn Pending store stays in load/store unitn Dependent instructions wait in reservation stations
Independent instructions continue
Effect of miss depends on program data flown Much harder to analysen Use system simulation
Chapter 5 — Large and Fast: Exploiting Memory
Hierarchy — 26
Chapter 5 — Large and Fast: Exploiting Memory
Hierarchy — 26
Virtual MemoryVirtual Memory
Use main memory as a “cache” for secondary (disk) storagen Managed jointly by CPU hardware and the operating
system (OS)Programs share main memoryn Each gets a private virtual address space holding its
frequently used code and datan Protected from other programs
CPU and OS translate virtual addresses to physical addressesn VM “block” is called a pagen VM translation “miss” is called a page fault
Use main memory as a “cache” for secondary (disk) storagen Managed jointly by CPU hardware and the operating
system (OS)Programs share main memoryn Each gets a private virtual address space holding its
frequently used code and datan Protected from other programs
CPU and OS translate virtual addresses to physical addressesn VM “block” is called a pagen VM translation “miss” is called a page fault
§5.4 Virtual M
emory
Chapter 6 — Storage and Other I/O Topics — 27
Chapter 6 — Storage and Other I/O Topics — 27
Disk StorageDisk StorageNonvolatile, rotating magnetic storageNonvolatile, rotating magnetic storage
§6.3 D
isk Storage
Chapter 6 — Storage and Other I/O Topics — 28
Chapter 6 — Storage and Other I/O Topics — 28
Disk Sectors and AccessDisk Sectors and Access
Each sector recordsn Sector IDn Data (512 bytes, 4096 bytes proposed)n Error correcting code (ECC)
Used to hide defects and recording errorsn Synchronization fields and gaps
Access to a sector involvesn Queuing delay if other accesses are pendingn Seek: move the headsn Rotational latencyn Data transfern Controller overhead
Each sector recordsn Sector IDn Data (512 bytes, 4096 bytes proposed)n Error correcting code (ECC)
Used to hide defects and recording errorsn Synchronization fields and gaps
Access to a sector involvesn Queuing delay if other accesses are pendingn Seek: move the headsn Rotational latencyn Data transfern Controller overhead
8
Chapter 6 — Storage and Other I/O Topics — 29
Chapter 6 — Storage and Other I/O Topics — 29
Disk Access ExampleDisk Access Example
Givenn 512B sector, 15,000rpm, 4ms average seek time,
100MB/s transfer rate, 0.2ms controller overhead, idle disk
Average read timen 4ms seek time
+ ½ / (15,000/60) = 2ms rotational latency+ 512 / 100MB/s = 0.005ms transfer time+ 0.2ms controller delay= 6.2ms
If actual average seek time is 1msn Average read time = 3.2ms
Givenn 512B sector, 15,000rpm, 4ms average seek time,
100MB/s transfer rate, 0.2ms controller overhead, idle disk
Average read timen 4ms seek time
+ ½ / (15,000/60) = 2ms rotational latency+ 512 / 100MB/s = 0.005ms transfer time+ 0.2ms controller delay= 6.2ms
If actual average seek time is 1msn Average read time = 3.2ms
Chapter 6 — Storage and Other I/O Topics — 30
Chapter 6 — Storage and Other I/O Topics — 30
Disk Performance IssuesDisk Performance Issues
Manufacturers quote average seek timen Based on all possible seeksn Locality and OS scheduling lead to smaller actual
average seek timesSmart disk controller allocate physical sectors on diskn Present logical sector interface to hostn SCSI, ATA, SATA
Disk drives include cachesn Prefetch sectors in anticipation of accessn Avoid seek and rotational delay
Manufacturers quote average seek timen Based on all possible seeksn Locality and OS scheduling lead to smaller actual
average seek timesSmart disk controller allocate physical sectors on diskn Present logical sector interface to hostn SCSI, ATA, SATA
Disk drives include cachesn Prefetch sectors in anticipation of accessn Avoid seek and rotational delay
Chapter 6 — Storage and Other I/O Topics — 31
Chapter 6 — Storage and Other I/O Topics — 31
Flash StorageFlash Storage
Nonvolatile semiconductor storagen 100× – 1000× faster than diskn Smaller, lower power, more robustn But more $/GB (between disk and DRAM)
Nonvolatile semiconductor storagen 100× – 1000× faster than diskn Smaller, lower power, more robustn But more $/GB (between disk and DRAM)
§6.4 Flash Storage
Chapter 6 — Storage and Other I/O Topics — 32
Chapter 6 — Storage and Other I/O Topics — 32
Flash TypesFlash Types
NOR flash: bit cell like a NOR gaten Random read/write accessn Used for instruction memory in embedded systems
NAND flash: bit cell like a NAND gaten Denser (bits/area), but block-at-a-time accessn Cheaper per GBn Used for USB keys, media storage, …
Flash bits wears out after 1000’s of accessesn Not suitable for direct RAM or disk replacementn Wear leveling: remap data to less used blocks
NOR flash: bit cell like a NOR gaten Random read/write accessn Used for instruction memory in embedded systems
NAND flash: bit cell like a NAND gaten Denser (bits/area), but block-at-a-time accessn Cheaper per GBn Used for USB keys, media storage, …
Flash bits wears out after 1000’s of accessesn Not suitable for direct RAM or disk replacementn Wear leveling: remap data to less used blocks
9
3333
Virtual vs. Physical AddressVirtual vs. Physical AddressProcessor assumes a certain memory addressing scheme:n A block of data is called a virtual pagen An address is called virtual (or logical) address
Main memory may have a different addressing scheme:n Real memory address is called a physical address,
MMU translates virtual address to physical addressn Complete address translation table is large and must
therefore reside in main memoryn MMU contains TLB (translation lookaside buffer),
which is a small cache of the address translation table
Processor assumes a certain memory addressing scheme:n A block of data is called a virtual pagen An address is called virtual (or logical) address
Main memory may have a different addressing scheme:n Real memory address is called a physical address,
MMU translates virtual address to physical addressn Complete address translation table is large and must
therefore reside in main memoryn MMU contains TLB (translation lookaside buffer),
which is a small cache of the address translation tableChapter 5 — Large and
Fast: Exploiting Memory Hierarchy — 34
Chapter 5 — Large and Fast: Exploiting Memory
Hierarchy — 34
Page Fault PenaltyPage Fault Penalty
On page fault, the page must be fetched from diskn Takes millions of clock cyclesn Handled by OS code
Try to minimize page fault raten Smart replacement algorithms
On page fault, the page must be fetched from diskn Takes millions of clock cyclesn Handled by OS code
Try to minimize page fault raten Smart replacement algorithms
Chapter 5 — Large and Fast: Exploiting Memory
Hierarchy — 35
Chapter 5 — Large and Fast: Exploiting Memory
Hierarchy — 35
Memory ProtectionMemory Protection
Different tasks can share parts of their virtual address spacesn But need to protect against errant accessn Requires OS assistance
Hardware support for OS protectionn Privileged supervisor mode (aka kernel mode)n Privileged instructionsn Page tables and other state information only
accessible in supervisor moden System call exception (e.g., syscall in MIPS)
Different tasks can share parts of their virtual address spacesn But need to protect against errant accessn Requires OS assistance
Hardware support for OS protectionn Privileged supervisor mode (aka kernel mode)n Privileged instructionsn Page tables and other state information only
accessible in supervisor moden System call exception (e.g., syscall in MIPS)
Chapter 5 — Large and Fast: Exploiting Memory
Hierarchy — 36
Chapter 5 — Large and Fast: Exploiting Memory
Hierarchy — 36
The Memory HierarchyThe Memory Hierarchy
Common principles apply at all levels of the memory hierarchyn Based on notions of caching
At each level in the hierarchyn Block placementn Finding a blockn Replacement on a missn Write policy
Common principles apply at all levels of the memory hierarchyn Based on notions of caching
At each level in the hierarchyn Block placementn Finding a blockn Replacement on a missn Write policy
§5.5 A C
omm
on Framew
ork for Mem
ory Hierarchies
The BIG Picture
10
Chapter 5 — Large and Fast: Exploiting Memory
Hierarchy — 37
Chapter 5 — Large and Fast: Exploiting Memory
Hierarchy — 37
Virtual MachinesVirtual Machines
Host computer emulates guest operating system and machine resourcesn Improved isolation of multiple guestsn Avoids security and reliability problemsn Aids sharing of resources
Virtualization has some performance impactn Feasible with modern high-performance comptuers
Examplesn IBM VM/370 (1970s technology!)n VMWaren Microsoft Virtual PC
Host computer emulates guest operating system and machine resourcesn Improved isolation of multiple guestsn Avoids security and reliability problemsn Aids sharing of resources
Virtualization has some performance impactn Feasible with modern high-performance comptuers
Examplesn IBM VM/370 (1970s technology!)n VMWaren Microsoft Virtual PC