Memory 설계

논리회로설계실험

Memory Memory 설계설계

논리회로설계실험

Contents

Multiple drive Shifter Type declarations ROM(Read Only Memory) RAM(Random Access Memory) 실습내용

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Multiple driveMultiple drive

한 port 에 여러 개의 시그널 할당이 이루어 지는 경우 여러 개의 다른 신호가 할당되기 때문에 resolution function 에 따라 x

로 출력

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architecture Behavioral of multi_drive is signal reg : std_logic_vector( 1 downto 0 ); begin output <= reg; process( clk, rst_b ) begin if( rst_b = '0' ) then reg <= "00"; elsif( clk = '1' and clk'event ) then if( input = "00" ) then reg <= "11"; output <= reg; else reg <= "00"; output <= reg; end if; end if; end process;end architecture Behavioral;

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ShifterShifter

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architecture Behavioral of shifter issignal reg : std_logic_vector( 3 downto 0 );beginq <= reg;process( clk, reset )Begin if( reset = '0' ) then reg <= "0000"; elsif( clk = '1' and clk'event ) then if( enable = '0' ) then reg <= reg; else case( mode ) is when "00" => reg <= pi; when "01" => if( dir = '0' ) then reg( 2 downto 0 ) <= reg( 3 downto 1 ); reg( 3 ) <= reg( 0 );

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ShifterShifter

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else reg( 3 downto 1 ) <= reg ( 2 downto 0 ); reg( 0 ) <= reg( 3 ); end if;when "10" => if( dir = '0' ) then reg( 3 downto 0 ) <= '0' & reg( 3 downto 1 ); else reg( 3 downto 0 ) <= reg( 2 downto 0 ) & '0'; end if;when others => if( dir = '0' ) then reg( 2 downto 0 ) <= reg( 3 downto 1 ); else reg( 3 downto 0 ) <= reg( 2 downto 0 ) & '0'; end if;end case;end if;end if;end process;end architecture Behavioral;

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Type declarationsType declarations

Type declaration

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Type_declaration ::=

full_type_declaration

|incomplete_type_declaration

Full_type_declaration ::=

type identifier is type_definition;

Type_definition ::=

scalar_type_definition

|composite_type_definition

|access_type_definition

|file_type_definition

|protected_type_definition

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Type declarationsType declarations

Type declarations 예제

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Type integer_file is file of INTEGER;

Type rom_type is array(15 downto 0)

of std_logic_vector(3 downto 0);

Type state_type is (S0, S1, S2, S3);

Subtype natural1 is integer range 0 to 150;

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subtype

type Integer is range -2147483647 to 2147483647

subtype Natural is Integer range 0 to 지정범위 subtype Positive is Integer range 1 to 지정범위

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ROMROM

Read Only Memory 전원 공급이 끊겨도 저장되어 있는 데이터가 보존됨 일반적으로 저장되어 있는 데이터는 제조시 저장됨 EPROM, EEPROM, Flash Memory, Mask ROM etc..

ROM 예제 Clock 의 상승에지에서 동작 동기 enable 4bits address in 4bits data out

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ROMROM

Module

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entity rominfr is port( clk, en : in std_logic; addr : in std_logic_vector( 3 downto 0 ); data : out std_logic_vector( 3 downto 0 ) );end entity rominfr;

architecture Behavioral of rominfr is type rom_type is array(15 downto 0) of std_logic_vector(3 downto 0); constant ROM : rom_type := ( "0001", "0010", "0011", "0100", "0101", "0110", "0111", "1000" , "1001", "1010", "1011", "1100", "1101", "1110", "1111", "0000" );begin process( clk ) begin if( clk = '1' and clk'event ) then if( en = '1' ) then data <= ROM( conv_integer( addr ) ); end if; end if; end process;end architecture Behavioral;

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ROMROM

Simulation result

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RAMRAM

Random Access Memory 읽기와 쓰기가 가능함 전원 공급 차단시 저장되어 있는 데이터 손실 SRAM, DRAM etc..

RAM 예제 Clock 의 상승에지에서 동작 동기 enable 동기 write enable 4bits Read/write address 4bits Data input 4bits Data output

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4 4

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RAMRAM

진리표

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EN WE A DI CLK DO

L X X X ↑ X

H LRead

addressX ↑ Read

data

H HWrite

addressWrite data

↑ Write data

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RAMRAM

실습내용 Enable 을 가지는 single-port RAM 설계 앞 페이지의 RAM 예제를 충족시킬 것 (enable 이 write enable 보다 우선 ) 주어진 entity 및 testbench 를 사용할 것 Clock 주기 : 10 ns Testbench input 초기값 0 entity

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entity raminfr is

port( clk, en, we : in std_logic;

addr, di : in std_logic_vector( 3 downto 0 );

do : out std_logic_vector( 3 downto 0 ) );

end entity raminfr;

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RAMRAM

Testbench

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wait for 53 ns; addr <= "0000";di <= "1111“;we <= '1';wait for 10 ns; en <= '1';wait for 10 ns; addr <= "0001";di <= "1110";wait for 10 ns; addr <= "0010";di <= "1101";wait for 10 ns; addr <= "0011";di <= "1100";wait for 10 ns;

addr <= "0100";di <= "1011";wait for 10 ns; addr <= "1100";di <= "0011";wait for 10 ns;

addr <= "1111";di <= "0000";wait for 10 ns;

en <= '0';addr <= "1101";di <= "0010";wait for 10 ns;

we <= '0';wait for 10 ns;

addr <= "0010";wait for 10 ns;

en <= '1';wait for 10 ns;

addr <= "0100";wait for 10 ns;

addr <= "0011";wait for 10 ns;

addr <= "1101";wait for 10 ns;

report "Simulation end";wait;

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RAMRAM

Simulation result

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RAM 설계 참고

type ram_type is array (15 downto 0) of std_logic_vector( 3 downto 0);

signal ram : ram_type;

signal read_addr : std_logic_vector (3 downto 0);

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