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    MEMORY

    Memory is a cornerstone of the modern PC. The CPU processes memory that holds

    the program code and data thatand it is this intimate relationship between memory

    and the CPU that forms the basis of computer performance. With larger and faster

    CPUs constantly being introduced, and more complex software is developed to take

    advantage of the processing power. In turn, the more complex software demands

    larger amounts of faster memory. With the explosive growth of Windows (and more

    recently, Windows 95) the demands made on memory performance are more acute

    than ever. These demands have resulted in a proliferation of memory types that go far

    beyond the simple, traditional DRAM. Cache (SRAM), fast page-mode (FPM)

    memory, extended data output (EDO) memory, video memory (VRAM), synchronous

    DRAM (SDRAM), flash BIOS, and other exotic memory types (such as RAMBUS)

    now compete for the attention of PC technicians. These new forms of memory also

    present some new problems.

    Historical review

    Back in the 80s, PCs were equipped with RAM in quantities of 64 KB, 256 KB, 512

    KB and finally 1 MB. Think of a home computer like Commodore 64. It had 64 KB

    RAM, and it worked fine. Around 1990, advanced operating systems, like Windows ,

    appeared on the market, That started the RAM race. The PC needed more and more

    RAM. That worked fine with the 386 processor, which could address larger amount of

    RAM. The first Windows operated PCs could address 2 MB RAM, but 4 MB soonbecame the standard. The race has continued through the 90s, as RAM prices have

    dropped dramatically.

    Today. it would be foolish to consider less than 32 MB RAM in a PC. Many have

    much more. 128 MB is in no way too much for a "power user" with Windows 95/98,

    it is important with plenty of RAM. Click here to read about the swap file and RAM

    considerations. Windows 98 is a little better at handling memory, but still a lot af

    RAM is a good thing.

    Memory Organization

    All memory is basically an array organized as rows and columns. Each row is known

    as an addressone million or more addresses might be on a single memory IC. Thecolumns represent data bitsa typical high-density memory IC has 1 bit, but might

    have 2 or 4 bits, depending on the overall amount of memory required.

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    As you probably see in the intersection of each column and row is an individual

    memory bit (known as a cell). This is important because the number of components ina celland the way those components are fabricated onto the memory ICwill have

    a profound impact on memory performance. For example, a classic DRAM cell is a

    single MOS transistor, and static RAM (or SRAM) cells often pack several transistors

    and other components onto the IC die. Although you do not have to be an expert on

    IC design, you should realize that the internal fabrication of a memory IC has more todo with its performance than just the way it is soldered into your computer.

    MEMORY SIGNALS

    A memory IC communicates with the outside world through three sets of signals:

    address lines, data lines, and control lines. Address lines define which row of thememory array will be active. In actuality, the address is specified as a binary number,

    and conversion circuitry inside the memory IC translates the binary number into a

    specific row signal. Data lines pass binary values back and forth to the defined

    address. Control lines are used to operate the memory IC. A Read/Write (R/W) line

    defines whether data is being read from the specified address or written to it. A Chip

    Select (CS) signal makes a memory IC active or inactive (this ability to disconnect

    from a circuit is what allows a myriad of memory ICs to all share common ad-dress

    and data signals in the computer). Some memory types require additional signals,

    such as Row Address-Select (RAS) and Column Address-Select (CAS), for refresh

    operations. More exotic memory types might require additional control signals.

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    ADD-ON MEMORY DEVICES

    Memory has always pushed the envelope of IC design. This trend has given us

    tremendous amounts of memory in very small packages, but it also has kept memory

    relatively expensive. Manufacturers responded by providing a minimum amount of

    memory with the system, then selling more memory as an add-on optionthis keeps

    the cost of a basic machine down and increases profit through add-on sales. As a

    technician, you should understand the three basic types of add-on memory.

    Proprietary add-on modules

    Once the Intel i286 opened the door for more than 1MB of memory, PC makers

    scrambled to fill the void. However, the rush to more memory resulted in a

    proliferation of non-standard (and incompatible) memory modules. Each new

    motherboard came with a new add-on memory schemethis invariably led to a great

    deal of confusion among PC users and makers alike. You will likely find proprietary

    memory modules in 286 and early 386 systems.

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    SIMMs and DIMMs

    By the time 386 systems took hold in the PC industry, proprietary memory modules

    had been largely abandoned in favor of the Memory Module. A SIMM (Single In-

    line Memory Module) is light, small, and contains a relatively large block of memory,

    but perhaps the greatest advantage of a SIMM is standardization. Using a standard pin

    layout, a SIMM from one PC can be installed in any other PC. The 30-pin SIMM

    provides 8 data bits, and generally holds up to 4MB of RAM. The 30-pin SIMM

    proved its worth in 386 and early 486 systems, but fell short when providing more

    memory to later-model PCs. The 72-pin SIMM (Table 23-2) supplanted the 30-pin

    version by providing 32 data bits, and it could hold up to 32MB (or more). Table 23-3

    out-lines a variation of the standard 72-pin SIMM highlighting the use ofError-Correction Code (ECC) instead of parity.

    Here you see a couple of SIMM modules. On top is a 64-bit module. Next is a 32-bit

    module with a 72-pin connector. Below is an 8-bit module with a 30-pin connector:

    64 bitSDRAM:

    32 bitDRAM:

    and

    16 bit

    DRAM:

    DIMMs appear virtually identical to SIMMs, but they are larger. And where eachelectrical contact on the SIMM is tied together between the front and back, the DIMM

    keeps front and back contacts separateeffectively doubling the number of contacts

    available on the device. For example, if you look at a 72-pin SIMM, you will see 72

    electrical contacts on both sides of the device (144 contacts total)but these are tied

    together, so there are only 72 signals (even with 144 contacts). On the other hand, a

    DIMM keeps the front and back contacts electrically separate (and usually adds some

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    additional pins to keep SIMMs and DIMMs from accidentally being mixed. Today,

    virtually all DIMM versions provide 168 pins (84 pins on each side). DIMMs areappearing in high-end 64-bit data-bus PCs (such as Pentiums and PowerPC RISC

    workstations).

    As PCs move from 64 to 128 bits over the next few years, DIMMs will likely replace

    SIMMs as the preferred memory-expansion device.

    Finally, you might see SIMMs and DIMMs referred to as composite ornon-compositemodules. These terms are used infrequently to describe the technology level of thememory module. For example, a composite module uses older, lower-density

    memory; so more I.Cs are required to achieve the required storage capacity.

    Conversely, a non-composite module uses newer memory technology; so fewer ICsare needed to reach the same storage capacity. In other words, if you encounter a

    high-density SIMM with only a few ICs on it, chances are that the SIMM is non-

    composite.

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    Memory Organization

    The memory in your computer represents the result of evolution over several

    computer generations. Memory operation and handling is taken care of by your

    systems microprocessor. As CPUs improved, memory-handling capabilities have

    improved as well. Todays microprocessors, such as the Intel Pentium or Pentium Pro,

    are capable of addressing more than 4GB of system memorywell beyond the levels

    of contemporary software applications. Unfortunately, the early PCs were not nearly

    so powerful.

    CONVENTIONAL MEMORY

    Conventional memory is the traditional 640KB assigned to the DOS Memory Area.The original PCs used microprocessors that could only address 1MB of memory

    (called real-mode memory or base memory). Out of that 1MB, portions of thememory must be set aside for basic system functions. BIOS code, video memory,

    interrupt vectors, and BIOS data are only some of the areas that re-quire reserved

    memory. The remaining 640KB became available to load and run your application,

    which can be any combination of executable code and data. The original PC only

    provided 512KB for the DOS program area, but computer designers quickly learned

    that another 128KB could be added to the DOS area while still retaining enough

    memory for overhead functions, so 512KB became 640KB. Every IBM-compatible

    PC still provides a 640KB base memory range, and most DOS application programs

    continue to fit within that limit to ensure backward compatibility to older systems.

    However, the drawbacks to the 8088 CPU were soon apparent. More memory had toadded to the computer for its evolution to continue. Yet, memory had to be added in a

    way that did not interfere with the conventional memory area.

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    Conventional and Upper Memory in a PC

    EXTENDED MEMORY

    The 80286 introduced in IBMs PC/AT was envisioned to overcome the 640KB

    barrier by incorporating a protected mode of addressing. The 80286 can address up to

    16MB of memory in protected mode, and its successors (the 80386 and later) can

    handle 4GB of protected-mode memory. Today, virtually all computer systems

    provide several MB of extended memory. Besides an advanced microprocessor,

    another key element for extended memory is software.

    Memory-management software must be loaded in advance for the computer to access

    its extended memory. Microsofts DOS 5.0 provides an extended memory manager

    utility (HIMEM.SYS), but other off-the-shelf utilities are available as well.

    Unfortunately, DOS itself cannot use extended memory. You might fill the extended

    memory with data, but the executable code comprising the program remains limited to

    the original 640KB of base memory. Some programs written with DOS extenders can

    over-come the 640KB limit, but the additional code needed for the extenders can

    make such programs a bit clunky. A DOS extender is basically a software module

    containing its own memory-management code, which is compiled into the final

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    application program. The DOS extender loads a program in real-mode memory. After

    the program is loaded, it switches program control to the protected-mode memory.When the program in protected mode needs to execute a DOS (real mode) function,

    the DOS extender converts protected-mode addresses into real-mode addresses,

    copies any necessary program data from protected to real-mode locations, switches

    the CPU to real-mode addressing, and carries out the function. The DOS extender

    then copies any results (if necessary) back to protected-mode addresses, switches the

    system to protected-mode once again, and the program continues to run.

    This back-and-forth conversion overhead results in less-than-optimum performance,

    compared to strictly real-mode programs or true protected-mode programs. With

    multiple megabytes of extended memory typically available, it is possible (but un-

    likely) that any one program will utilize all of the extended memory. Multiple

    programs that use extended memory must not attempt to utilize the same memorylocations. If conflicts occur, a catastrophic system crash is almost inevitable. To

    prevent conflicts in ex-tended memory, memory-manager software can make use of

    three major industry standards: theExtended Memory Specification (XMS), the VirtualControl Program Inter-face (VCPI), or theDOS Protected-Mode Interface (DPMI).

    EXPANDED MEMORY

    Expanded memory is another popular technique used to overcome the traditional

    640KB limit of real-mode addressing. Expanded memory uses the same physical

    RAM chips, but differs from extended memory in the way that physical memory is

    used. Instead of trying to address physical memory locations outside of theconventional memory range, as extended memory does, expanded memory blocks are

    switched into the base memory range, where the CPU can access it in real mode. The

    original expanded memory specification (called the Lotus-Intel-Microsoft LIMor

    EMS specification) used 16KB banks of memory which were mapped into a 64KBrange of real-mode memory existing just above the video memory range. Thus, four

    blocks of expanded memory could be dealt with simultaneously in the real mode.

    Early implementations of expanded memory utilized special expansion boards that

    switched blocks of memory, but later CPUs that support memory mapping allowed

    expanded memory managers (EMMs or LIMs) to supply software-only solutions for

    i386, i486, and Pentium-based machines. EMS/LIM 4.0 is the latest version of the

    expanded memory standard, which handles up to 32MB of memory. An expandedmemory manager (such as the DOS utility EMM386.EXE) allows the extended

    memory sitting in your computer to emulate expanded memory. For most practical

    purposes, expanded memory is more useful than extended memory because its ability

    to map directly to the real mode allows support for program multi-tasking. To use

    expanded memory, programs must be written specifically to take advantage of the

    function calls and subroutines needed to switch memory blocks. Functions are

    completely specified in the LIM/EMS 4.0 standard.

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    UPPER MEMORY AREA (UMA)

    The upper 384KB of real-mode memory is not available to DOS because it is

    dedicated to handling memory requirements of the physical computer system. This is

    called theHigh DOS Memory Range orUpper Memory Area (UMA). However, eventhe most advanced PCs do not use the entire 384KB, so there is often a substantial

    amount of unused memory existing in your systems real-mode range. Late-model

    CPUs, such as the i386 and i486 can re-map extended memory into the range unused

    by your system. Because this found memory space is not contiguous with your

    640KB DOS space, DOS application programs cannot use the space, but small

    independent drivers and T.S.Rs can be loaded and run from this UMA. The

    advantage to using high DOS memory is that more of the 640KB DOS range remains

    available for your application program. Memory-management programs (such as the

    utilities found with DOS 5.0 and higher) are needed to locate and re-map thesememory blocks.

    HIGH MEMORY

    A peculiar anomaly occurs with CPUs that support extended memorythey can

    access one segment (about 64KB) of extended memory beyond the real-mode area.

    This capability arises because of the address line layout on late-model CPUs. As a

    result, the real-mode operation can access roughly 64KB above the 1MB limit. Like

    high DOS memory, this found 64KB is not contiguous with the normal 640KB

    DOS memory range, so DOS cannot use this high memory to load a DOS application, but device drivers and T.S.Rs can be placed in high memory. DOS 5.0 is

    intentionally designed so that its 40 to 50KB of code can be easily moved into this

    high memory area. With DOS loaded into high memory, an extra 40 to 50KB or so

    will be available within the 640KB DOS range.

    Memory Considerations

    Memory has become far more important than just a place to store bits for the

    microprocessor. It has proliferated and specialized to the point where it is difficult to

    keep track of all the memory options and architectures that are available.

    MEMORY SPEED AND WAIT STATES

    All memory is rated in terms of speedspecifically, access time. Access time is thedelay between the time data in memory is successfully addressed, to the point at

    which the data has been successfully delivered to the data bus. For PC memory,

    access time is measured in nanoseconds (ns), and current memory offers access times

    of 50 to 60 ns. 70 ns memory is extremely common .

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    A wait state orders the CPU to pause for one clock cycle to give memory additional

    time to operate. Typical PCs use one wait state, although very old systems might

    require two or three. The latest PC designs with high-end memory or aggressive

    caching might be able to operate with no (zero) wait states. As you might imagine, a

    wait state is basically a waste of time, so more wait states result in lower system

    performance. Zero wait states allow optimum system performance.

    There are three classic means of selecting wait states. First, the number of wait states

    might be fixed (common in old XT systems). Wait states might be selected with one

    or more jumpers on the motherboard (typical of i286 and early i386 systems). Currentsystems, such as i486 and Pentium computers, place the wait state control in the

    CMOS setup routine. You might have to look in an advanced settings area to find

    the entry. When optimizing a computer, you should be sure to set the minimum

    number of wait states.

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    DETERMINING MEMORY SPEEDIt is often necessary to check SIMMs or DIMMs for proper memory speed duringtroubleshooting, or when selecting replacement parts. Unfortunately, it can be very

    difficult to determine memory speed accurately based on part markings. Speeds are

    normally marked cryptically by adding a number to the end of the part number. For

    example, a part number ending in -6 often means 60 ns, a 7 is usually 70 ns, and a 8

    can be 80 ns. Still, the only way to be absolutely certain of the memory speed is to

    cross reference the memory part number with a manufacturers catalog, and read the

    speed from the catalogs description (i.e., 4M 32 50 ns EDO).

    PRESENCE DETECT (PD)

    Another feature of modern memory devices is a series of signals known as the

    Presence Detect lines. By setting the appropriate conditions of the PD signals, it ispossible for a computer to immediately recognize the characteristics of the installed

    memory devices, and configure itself accordingly. Presence detects lines typically

    specify three operating characteristics of memory: size (device layout) and speed.

    MEMORY TYPESFor a computer to work, the CPU must take program instructions and exchange data

    directly with memory. As a consequence, memory must keep pace with the CPU (or

    make the CPU wait for it to catch up). Now that processors are so incredibly fast (and

    getting faster), traditional memory architectures are being replaced by specialized

    memory devices that have been tailored to serve specific functions in the PC. Some of

    the memory designations are

    DRAM (Dynamic Random-Access Memory): This remains the mostrecognized and common form of computer memory. DRAM achieves a good

    mix of speed and density, while being relatively simple and inexpensive to

    produceonly a single transistor and capacitor is needed to hold a bit.

    Unfortunately, DRAM contents must be refreshed every few milliseconds or

    the contents of each bit location will decay. DRAM performance is also

    limited because of relatively long access times. Today, many video boards are

    using DRAM SIMMs to supply video memory.

    SRAM (Static Random-Access Memory) The SRAM is also a classic

    memory designit is even older than DRAM. SRAM does not requireregular refresh operations, and can be made to operate at access speeds that

    are much faster than DRAM. However, SRAM uses six transistors (or more)

    to hold a single bit. This reduces the density of SRAM and increases power

    demands (which is why SRAM was never adopted for general PC use in the

    first place). Still, the high speed of SRAM has earned it a place as the PCs

    L2 (or external) cache. Youll probably encounter three types of SRAM

    cache schemes: asynchronous, synchronous burst, and pipeline burst.

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    Asynchronous Static RAM (Async SRAMor ASRAM) This is the

    traditional form of L2 cache, introduced with i386 systems. Theres really

    nothing too special about AS-RAM, except that its contents can be accessed

    much faster (20 ns, 15 ns, or 12 ns) than DRAM. ASRAM does not have

    enough performance to be accessed synchronously, and has long since been

    replaced by better types of cache.

    Synchronous-Burst Static RAM (Sync SRAMor SBSRAM) This islargely regarded as the best type of L2 cache for intermediate-speed

    motherboards (~60 to 66MHz). With access times of 8.5 ns and 12 ns, the

    SBSRAM can provide synchronous bursts of cache information in 2-1-1-1

    cycles (i.e., 2 clock cycles for the first access, then 1 cycles per accessintime with the CPU clock). However, as motherboards pass 66MHz (i.e., 75

    and 83MHz designs), SBSRAM loses its advantage to Pipelined Burst

    SRAM.

    Pipelined-Burst Static RAM (PB SRAM) At 4.5 to 8 ns, this is the

    fastest form of high-performance cache now available for 75MHz+

    motherboards. PBSRAM requires an extra clock cycle for lead off, but

    then can sync with the motherboard clock (with timing such as 3-1-1-1)

    across a wide range of motherboard frequencies.

    VRAM (Video Random-Access Memory) DRAM has been the traditional

    choice for video memory, but the ever-increasing demand for fast videoinformation (i.e., high-resolution SVGA displays) requires a more efficient

    means of transferring data to and from video memory. Originally developed

    by Samsung Electronics, video RAM achieves speed improvements by using

    a dual data bus scheme. Ordinary RAM uses a single data bus data

    enters or leaves the RAM through a single set of signals. Video RAM

    provides an input data bus and an output data bus. This allows data to be

    read from video RAM at the same time new information is being written to

    it. You should realize that the advantages of VRAM will only be realized on

    high-end video systems

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    . FPM DRAM (Fast-Page Mode DRAM) This is a popular twist on

    conventional DRAM. Typical DRAM access is accomplished in a fashion

    similar to reading from a booka memory page is accessed first, then the

    contents of that page can be located. The problem is that every access

    requires the DRAM to re-locate the page. Fast-page mode operation

    overcomes this delay by allowing the CPU to access multiple pieces of data on

    the same page without having to re-locate the page every timeas long

    as the subsequent read or write cycle is on the previously located page, the

    FPDRAM can access the specific location on that page directly.

    EDRAM (Enhanced DRAM) This is another, lesser-known variation of the

    classic DRAM developed by Ramtron International and United Memories.First demonstrated in August 1994, the EDRAM eliminates an external cache

    by placing a small amount of static RAM (cache) into each EDRAM device

    itself. In essence, the cache is distributed within the system RAM; as more

    memory is added to the PC, more cache is effectively added as well. The

    internal construction of an EDRAM allows it to act like page-mode memory

    if a subsequent read requests data that is in the ED-RAMs cache (known as a

    hit), the data is made available in about 15 nsroughly equal to the speed of afair external cache. If the subsequent read requests data that is not in the cache

    (called a miss), the data is accessed from the DRAM portion of memory inabout 35 ns, which is still much faster than ordinary DRAM.

    EDO RAM (Extended Data Output RAM) EDO RAM is a relatively well-

    established variation to DRAM, which extends the time that output data is

    validthus the words . presence on the data bus is extended. This is

    accomplished by modifying the DRAMs output buffer, which prolongs the

    time where read data is valid. The data will remain valid until a motherboard

    signal is received to release it. This eases timing constraints on the memory

    and allows a 15 to 30% improvement in memory performance with little real

    increase in cost. Because a new external signal is needed to operate EDO

    RAM, the motherboard must use a chipset designed to accommodate EDO.

    Intels Triton chipset was one of the first to support EDO, although now most

    chipsets (and most current motherboards) currently support EDO. EDO RAMcan be used in non-EDO motherboards, but there will be no performance

    improvement.

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    BEDO (Burst Extended Data Output RAM) This powerful variation of EDORAM reads data in a burst, which means that after a valid address has been

    provided, the next three data addresses can be read in only one clock cycle

    each. The CPU can read BEDO data in a 5-1-1-1 pattern (5 clock cycles for

    the first address, then one clock cycle for the next three addresses. Although

    BEDO offers an advantage over EDO, it is only supported currently by the

    VIA chipsets: 580VP, 590VP, 680VP. Also, BEDO seems to have difficulty

    supporting motherboards over 66MHz.

    SDRAM (Synchronous or Synchronized DRAM) Typical memory can onlytransfer data during certain portions of a clock cycle. The SDRAM modifies

    memory operation so that outputs can be valid at any point in the clock cycle.

    By itself, this is not really significant, but SDRAM also provides a pipelineburst mode that allows a second access to begin before the current access is

    complete. This continuous memory access offers effective access speeds as

    fast as 10 ns, and can transfer data at up to 100MB/s. SDRAM is becoming

    quite popular on current motherboard designs, and is supported by the Intel

    VX chipset, and VIA 580VP, 590VP, and 680VP chipsets. Like BEDO,

    SDRAM can transfer data in a 5-1-1-1 pattern, but it can support motherboard

    speeds up to 100MHz, which is ideal for the 75MHz and 82MHz

    motherboards now becoming so vital for Pentium II systems.

    CDRAM (Cached DRAM) Like EDRAM, the CDRAM from Mitsubishi

    incorporates cache and DRAM on the same IC. This eliminates the need foran external (or L2) cache, and has the extra benefit of adding cache whenever

    RAM is added to the system. The difference is that CDRAM uses a set-

    associative cache approach that can be 15 to 20% more efficient than the

    EDRAM cache scheme. On the other hand, EDRAM appears to offer better

    overall performance.

    RDRAM (Rambus DRAM)Most of the memory alternatives so far have beenvariations of the same basic architecture. Rambus, Inc. (joint developers of

    EDRAM) has created a new memory architecture called theRambus Channel.

    CPU or specialized IC is used as the master device and the RD-RAMs are

    used as slave devices. Data is then sent back and forth across the Rambuschannel in 256-byte blocks. With a dual 250MHz clock, the Rambus Channel can

    transfer data based on the timing of both clocksthis results in data-transfer rates

    approaching 500MB/s (roughly equivalent to 2-ns access time). The problem with

    RDRAM is that a Rambus Channel would require an extensive re-design to the

    current PC memory architecturea move that most PC makers strenuously resist.

    As a result, you are most likely to see RDRAM in high-end, specialized

    computing systems. Still, as memory struggles to match the microprocessor, PC

    makers might yet embrace the Rambus approach for commercial systems.

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    WRAM (Windows RAM) Samsung Electronics has recently introducedWRAM as a new video-specific memory device. WRAM uses multiple-bit

    arrays connected with an extensive internal bus and high-speed registers that

    can transfer data almost continuously. Other specialized registers support

    attributes, such as foreground color, background color, write-block control

    bits, and true-byte masking. Samsung claims data-transfer rates of up to

    640MB/sabout 50% faster than VRAMyet WRAM devices are cheaper

    than their VRAM counterparts. It is likely that WRAM will receive some

    serious consideration in the next few years.TROUBLESHOOTING

    MEMORY TECHNIQUES

    The three most-popular architectures are: paged memory, interleaved memory, and

    memory caching.

    Paged memory : This approach basically divides system RAM into small groups (or

    pages) from 512 bytes to several KB long. Memory-management circuitry on the

    motherboard allows subsequent memory accesses on the same page to be

    accomplished with zero wait states. If the subsequent access occurs outside of the

    current page, one or more wait states might be added while the new page is

    found. This is identical in principle to fast-page mode DRAM. You will find page-

    mode architectures implemented on high-end i286, PS/2 (model 70 and 80), and manyi386 systems.

    Interleaved memory : This technique provides better performance than paged

    memory. Simply put, interleaved memory combines two banks of memory into one.

    The first portion is even, while the second portion is oddso memory contents

    are alternated between these two areas. This allows a memory access in the second

    portion to begin before the memory access in the first portion has finished. In effect,

    interleaving can double memory performance. The problem with interleaving is that

    you must provide twice the amount of memory as matched pairs. Most PCs that use

    interleaving will allow you to add memory one bank at a time, but interleaving will be

    disabled and system performance will suffer.

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    Memory caching : This is perhaps the most recognized form of memory-enhancement architecture . Cache is a small amount (anywhere from 8KB to 1MB) of

    very fast SRAM, which forms an interface between the CPU and ordinary DRAM.

    The SRAM typically operates on the order of 5 to 15 ns, which is fast enough to keep

    pace with a CPU using zero wait states. A cache-controller IC on the motherboard

    keeps track of frequently accessed memory locations (as well as predicted memory

    locations), and copies those contents into cache. When a CPU reads from memory, it

    checks the cache first. If the needed contents are present in cache (called a cache hit),

    the data is read at zero wait states. If the needed contents are not present in the cache

    (known as a cache miss), the data must be read directly from DRAM at a penalty of

    one or more wait states. A small quantity of very fast cache (called Tag RAM) acts as

    an index, recording the various locations of data stored in cache. A well-designed

    caching system can achieve a hit ratio of 95% or morein other words, memory canrun without wait states 95% of the time.

    Two levels of cache are in the contemporary PC. CPUs from the i486 onward have a

    small internal cache (known as L1 cache) and external cache (SRAM installed as

    DIPs or COAST modules on the motherboard) is referred to as L2 cache. The i386CPUs have no internal cache (although IBMs 386SLC offered 8KB of L1 cache).

    Most i486 CPUs provide an 8KB internal cache. Early Pentium processors were fitted

    with two 8KB internal cachesone for data and one for instructions. Todays

    Pentium II Slot 1 CPU incorporates 256 to 512KB of L2 cache into the processor

    cartridge itself.

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    Shadow memory : ROM devices (whether the BIOS ROM on your motherboard

    or a ROM IC on an expansion board) are frustratingly slow with access times oftenexceeding several hundred nanoseconds. ROM access then requires a large number of

    wait states, which slow down the systems performance. This problem is compounded

    because the routines stored in BIOS (especially the video BIOS ROM on the video

    board) are some of the most frequently accessed memory in your computer.

    Beginning with the i386-class computers, some designs used a memory technique

    called shadowing. ROM contents are loaded into an area of fast RAM during systeminitialization, then the computer maps the fast RAM into memory locations used by

    the ROM de-vices.

    Whenever ROM routines must be accessed during run time, information is taken from

    the shadowed ROM instead of the actual ROM IC. The ROM performance can be

    improved by at least 300%. Shadow memory is also useful for ROM devices that donot use the full available data bus width. For example, a 16-bit computer system

    might hold an expansion board that contains an 8-bit ROM IC. The system would

    have to access the ROM not once, but twice, to extract a single 16-bit word. If the

    computer is a 32-bit machine, that 8-bit ROM would have to be addressed four times

    to make a complete 32-bit word. You might imagine the hideous system delays that

    can be encountered. Loading the ROM to shadow memory in advance virtually

    eliminates such delays. Shadowing can usually be turned on or off through the

    systems CMOS Setup routines.

    PARITY ISSUES

    It is vital that data and program instructions remain error-free. Even one incorrect bit

    because of electrical noise or a component failure can crash the PC, corrupt drive

    information, cause video problems, or result in a myriad of other faults. PC designers

    approached the issue of memory integrity by using a technique known asparity.

    THE PARITY PRINCIPLE

    The basic idea behind parity is simpleeach byte written to memory is checked, and

    a 9th bit is added to the byte as a checking (or parity) bit. When a memory address

    is later read by the CPU, memory-checking circuitry on the motherboard will

    calculate the expected parity bit and compare it to the bit actually read from memory.

    In this fashion, the PC can continuously diagnose system memory by checking theintegrity of its data. If the read parity bit matches the expected parity bit, the data

    (and, indirectly, the RAM) is assumed to be valid, and the CPU can go on its way. If

    the read and expected parity bits do not match, the system registers an error and halts.

    Every byte is given a parity bit, so for a 32-bit PC, there will be 4 parity bits for every

    address. A 64- bit PC, has 8 parity bits, etc.

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    EVEN VS. ODD

    The two types of parity are even and odd. With even parity, the parity bit is set to 0 if

    an even number of 1s is already in the corresponding byte (keeping the number of 1s

    even). If an even number of 1s is not in the byte, the even parity bit will be 1 (making

    the number of 1s even). With odd parity, the parity bit is set to 0 if an odd number of

    1s is already in the corresponding byte (keeping the number of 1s odd). If an odd

    number of 1s is not in the byte, the odd parity bit will be 1 (making the number of 1s

    odd). Although even and odd parity work opposite of one another, both schemes serve

    exactly the same purpose and have the same probability of catching a bad bit. The

    memory device itself does not care at all about what type of parity is being usedit

    just needs to have the parity bits available. The use of parity (and the choice of even

    or odd) is left up to the motherboards memory-control circuit.

    THE PROBLEMS WITH PARITY

    Although parity has proven to be a simple and cost-effective means of continuously

    checking memory, there are two significant limitations. First, although parity can

    detect an error, it cannot correct the error because there is no way to tell which bit has

    gone bad. This is why a system simply halts when a parity error is detected. Second,

    parity is unable to detect multi-bit errors. For example, if a 1 accidentally becomes a 0

    and a 0 accidentally becomes a 1 within the same byte, parity conditions will still be

    satisfied. Fortunately, the probability of a multi-bit error in the same byte is extremely

    remote.

    ALTERNATIVE ERROR CORRECTION

    In the world of personal computing, parity is an ancient technique. Frankly, it could

    easily be replaced by more sophisticated techniques, such as Error-Correction Code(ECC) orECC. ECC (which is already being used in high-end PCs and file servers)uses a mathematical process in conjunction with the motherboards memory

    controller, and appends a number of ECC bits to the data bits. When data is read back

    from memory, the ECC memory controller checks the ECC data read back as well.

    ECC has two important advantages over parity. It can actually correct single-bit

    errors on-the-fly without the user ever knowing theres been a problem. In addition,

    ECC can successfully detect 2-bit, 3-bit, and 4-bit errors, which makes it an incredibly

    powerful error-detection tool. If a rare multi-bit error is detected, ECC is unable to

    correct it, but it will be reported and the system will halt.

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    RAM speeds

    RAM speed is measured in ns (nano seconds). The fewer ns, the faster is the RAM.Years ago, RAM came in 120, 100 and 80 ns. Today, we are talking about 60 ns and

    faster. It becomes complicated to describe the relationship between RAM speed and

    the ability of the system bus to utilize fast RAM. I will gloss over that. But here is a

    table, which illustrates RAM speed, relative to clock speed.

    Clock speed Time per clock tick

    20 MHz 50 ns

    25 MHz 40 ns

    33 MHz 30 ns

    50 MHz 20 ns

    66 MHz 15 ns

    100 MHz 10 ns

    133 MHz 6 ns

    Peak Bandwidth

    Here you see the maximal peak bandwidth of the three well-known RAM types. The

    figure illustrates the absolutely maximal transfer from RAM to the L2-cache - in

    peaks, not as continuously transferred.

    RAM type Max. peak bandwidth

    FPM 176 MB/sec

    EDO 264 MB/sec

    SD 528 MB/sec

    Pentium motherboard with SIMMs

    On the Pentium motherboard, the system bus is 64 bit wide. Therefore, the 32 bit

    SIMMs are installed in pairs. Since the standard motherboard only has two banks with

    a total of four SIMM sockets, RAM expansion possibilities are limited. NOTE: never

    use different speed RAM modules on the Pentium motherboard. All modules musthave the same speed. Here you see a few configurations on an old Pentium

    motherboard with four SIMM sockets:

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    Bank 1 Bank 2 Total RAM

    16 MB + 16 MB - 32 MB

    16 MB + 16 MB 32 MB + 32 MB 96 MB

    32 MB + 32 MB 32 Mb + 32 MB 128 MB

    Rambus RDRAM

    While the CPUs has become around 200 times faster in ten years, the RAM

    performance has only gone up 20 times. So we need new RAM types. But which?

    Many vendors decided to go for DDR RAM as described in. Where DDR RAM is adevelopment of the existing SDRAM technology, Intel chooses RDRAM, which

    represents a much more revolutionary change in RAM design.

    Intel and RDRAM without success

    Intel is committed to the Rambus RAM, which also is called RDRAM (Rambus

    Direct RAM), nDRAM, or RIMM (Rambus Inline Memory Modules). RDRAM is an

    advanced technology patented by a company, who sells the technology to other chip

    manufactures for a 2% in license. In 1997 Intel signed a contract that apparently

    commits them to support RDRAM only in all new chipset up to 2002. Originally

    AMD also expected to support the Rambus RAM for its Athlon processor. But havingseen all Intel's problems with the technology, AMD is not so keen on the Rambus

    anymore. However, RDRAM is already used in Sony PlayStation 2 and in

    Nintendo64 machines. In the Sony PlayStation 2 you find 32 MB of RDRAM

    delivering a bandwidth of 3.2 GB/sec. During 1999 and 2000, Rambus was not very

    successful. In fact, Intel has suffered a serious set-back due to their commitment to the

    Rambus design. The chip set i820 "Camino" became a little disaster. Intel failed to

    produce a reliable way to interface SDRAM to the 820 chipset. The MTH (Memory

    Translator Hub - which translated RDRAM bus to SDRAM modules) had some

    timing or noise issues that caused unreliable operation. Intel replaced CC820 boards

    with VC820 boards (with 128MB RDRAM included) as the CC820 use the MTH and

    SDRAM while the VC820 used RDRAM.

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    Intelligent Rambus design

    RDRAM is developed from the traditional DRAM, but the architecture is completely

    new. It has been streamed and optimized to yield new performance. The RAMBUS-

    design gives a more intelligent access to the RAM, meaning that units can "prefetch"

    data and this way free the CPU some work. The idea is that data is read in small

    packets at a very high clock speed. The RIMM modules are only 16 bit wide

    compared to the traditional 64 bit SDRAM DIMMs, but they work at a much higher

    clock frequency:

    The Rambus modules work on 2.5 volts, which internally is reduced down to 0.5 voltwhen possible. This helps to reduce heat and radio signals. The RIMMs hold

    controlling chips that turn off the power to sections not in use. They can also reduce

    the memory speed if thermal sensors report of overheating. The RIMM modules hold

    184 pins.

    The RDRAM chips have to be placed very close to the CPU to reduce radio noise.

    This indicates, that RIMM technology is rather sensitive.

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    Multichannel memory design

    You may bundle four channels to a 64 bit wide RAM bus giving 6.4 GB/sec

    DDR RAM

    A very interesting RAM type is the DDR RAM, which is expected to hit the market in

    2001. DDR stands here forDouble Data Rate. It is a technology that transmits data

    on both sides of a tact signal. This way the performance has been doubled; a 133

    MHz SDRAM chip can very easy become altered to a 266 MHz DDR chip:

    It should be pretty easy for the market to change for DDR RAM. The modules look

    like and operate quite similar to existing SDRAMs. We just need new chipsets to start

    the migration. However, the modules hold 16 pins more than SDRAM do, so they do

    not fit into the same sockets.

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    PC2100The Taiwanese company VIA, which produces chip sets and CPUs and who arefighting Intel, is fully supporting the DDR RAM strategy. Soon we shall see 266 MHz

    moduls (being "overclocked"133 MHz SDRAM modules).The 266 MHz modules

    reaches a 2.1 GB/sec bandwidth. Hence they are to be sold as PC2100 RAM.

    Other terms used are:

    DDR200 (200 MHz)

    DDR266 (266 MHz)

    DDR333 (333 MHz)

    VIA expects DDR to be used in all segments of the pc market. Intel, who is behind

    the Rambus technology, only expects to use DDR in large servers, where you find

    several Gigabytes of RAM installed, and where RAM price really matters.

    Evolutionary changes of designWhere RDRAM requires completely new production plants, DDR represents an

    evolutionary progress. The chip manufactures may re-use their SDRAM fabs for the

    production without many problems.

    Hence it seems quite natural and in tune with the previous changes in RAM

    technology that we use the DDR standard for a couple of years. Before Rambus (or

    something even better) enters the market.

    Comparing bandwidthBelow you see the theoretical bandwidths of different RAM types. However, SDRAMdoes not perform as good as the figures show. This is due to latencies; the CPU and

    other units cannot read the data at these speeds; they have to wait some clock circles

    in between each reading before the data transfers start. The same goes for DDR RAM.

    RAM type Theoretical max. bandwidth

    SDRAM 100 MHz 100 MHz X 64 bit= 800 MB/sec

    SDRAM 133 MHz 133 MHz X 64 bit= 1064 MB/sec

    DDRAM 200 MHz (PC1600) 2 X 100 MHz X 64 bit= 1600 MB/sec

    DDRAM 266 MHz (PC2100) 2 X 133 MHz X 64 bit= 2128 MB/sec

    DDRAM 366 MHz (PC2600) 2 X 166 MHz X 64 bit= 2656 MB/sec

    RDRAM 600 MHz 600 MHz X 16 bit= 1200 MB/sec

    RDRAM 700 MHz 700 MHz X 16 bit= 1400 MB/sec

    RDRAM 800 MHz 800 MHz X 16 bit= 1600 MB/sec