Meeting Verification Challenges

©Synopsys 2012 1

Meeting Verification Challenges

Luc Burgun

VP, Synopsys Emulation Division

Verification Group

November, 2012

©Synopsys 2012 2

What’s New:Synopsys Acquires EVE

• #1 worldwide HW/SW co-

emulation provider

– 450+ emulation systems shipped

– 60+ customers worldwide

• Complements and strengthens

Synopsys verification solution

– Market-leading emulation

performance, capacity, cost-per-gate

– Broadest library of transactor VIP

– Large team of emulation experts

– World-wide presence

• EVE is now part of Synopsys’

Verification Business Unit

– ~140 employees (60% R&D)

20+ billion gates

installed so far

October 4th, 2012

©Synopsys 2012 3

ZeBu Hardware Products Overview

ZeBu-Server– Latest generation of FPGA-based emulators

able to map very large designs

– Eminently scalable

– The new standard for Hardware / Software

Co-Verification

ZeBu-Blade2– Newest member of the ZeBu emulation family

– The first based on Xilinx Virtex6-LX760

FPGAs

– A paradigm shift in emulation, from the lab to

the desktop, for the entire design team

ZeBu-Blade2 Fast ASIC

Desktop Emulator

©Synopsys 2012 4

Silicon

Evolution of Emulation…“Emulation” = Acceleration + In-Circuit Emulation

• Emulation systems initially only did “In-Circuit Emulation”

• The market is moving more towards Transaction-Based Verification

• Emulators now do: Co-simulation, Transaction-Based Ver., STB, In-Circuit

Co-SimulationTransaction Based

Co-emulationIn-Circuit Emulation

Synthesizable Test

Bench Emulation

1989 1995 2000 2005

RTL RTL RTL

Simulator

TB RTL

Video

Ethernet

System

Models

USB

I2S

MIPI

©Synopsys 2012 5

Design Size by Technology Node-

Derived from ITRS Data

Confidential

0

200

400

600

800

1000

1200

1400

130 90 65 45 32 22

Hi vol MPU

Hi Perf MPU

Network

Cons. Stationary

Cons. Portable

M-gates

Tech Node, nm

Consumer

Portable

at 150M gates

©Synopsys 2012 6

ITRS Drivers, 2010 Update, Consumer

Portable Devices

No. of

Processors

©Synopsys 2012 7

Growth in SoC Consumer Stationary

Complexity – 75 Processors Is Coming!!

©Synopsys 2012 8

Pwr Consumption Going Off the Charts

©Synopsys 2012 9

Verification Process Challenge

• Scale in size

• Improve throughput

• Maintain or reduce absolute design and verification cost

on a per project basis

• Increase accessibility to more users

• Reduce the complexity of the traceability and debug

usage model

• Improve traceability and debug cycle time

• Make Power Mgmt and Power Estimation integral to

verification

©Synopsys 2012 10

System-Level Verification Requires

Merger of ESL Methodology & Hardware,

High Speed

Transaction-level

Application Debug

Platforms

Project Phases

HW-SW Co-verification

Methodologies

FAST SoC

HW-SW Co-verification

Model

©Synopsys 2012 11

Verification Environment Must Move to

System-Level

RTL

ESL

©Synopsys 2012 12

Transaction &

Frame/Packet View

zRun

Signal access

Memory accessSVA

Waveform generation

Comprehensive HW

Verification

ICE

Transactors

SW Debugger

ESL/SystemC

Integration with SW

Environments

RTL and SW Verification Need to Merge

into System-Level Verification

©Synopsys 2012 13

Need to Link Virtual Models with

Implementation Models in Hardware

ZeBu EmulatorZeBu Host PC

RTB

e-zTest AXI Master

SoC

BFMAPIAXI BUS

HDMI Display

HDMIInterfacee-zTest HDMI Sink

BFMAPI

TLM-2.0

UARTInterfacee-zTest UART

Memory

DSPCore

IPCore

BFMAPI

UART Terminal

Bu

ilt-

in IS

S

Co

nn

ecti

on

DS-5 Debugger

Cortex A9

Model

©Synopsys 2012 14

Ultimately Migrate to Full Cycle-Acurate

SoC in Accelerated ESL Verification

©Synopsys 2012 15

The Next Generations of Verification

• Test Benches generate real data processed through

transaction-based IP

• Capacity must scale with IC Technology Roadmap or it

will never keep up with design size growth at bleeding

edge

• Intelligent SW-HW cockpit-type views of the SoC activity

must evolve providing “insight-level” information

• All problems and their impacts must be deterministic --

repeatable and reproducible

• Power verification is integral to verification process