media.digikey.commedia.digikey.com/PDF/Data Sheets/Freescale Semi/M5407C3UM.pdf · LIMITED WARRANTY Matrix Design warrants this product against defects in material and workmanship

M5407C3UM/DRev. 1.1, 8/2000

M5407C3 User's Manual

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Freescale Semiconductor, Inc.

For More Information On This Product, Go to: www.freescale.com

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© Motorola Inc., 2000. All rights reserved.

DigitalDNA and Mfax are trademarks of Motorola, Inc.

IBM PC and IBM AT are registered trademark of IBM Corp.

I

2

C-Bus is a proprietary Philips Semiconductor interface bus

All other trademark names mentioned in this manual are the registered trade mark of respective owners

No part of this manual and the dBUG software provided in Flash ROM’s/EPROM’s may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise. Use of the program or any part thereof, for any purpose other than single end user by the purchaser is prohibited.

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

How to reach us:

USA/EUROPE/Locations Not Listed:

Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1–303–675–2140 or 1–800–441–2447

JAPAN:

Motorola Japan Ltd.; SPS, Technical Information Center, 3–20–1, Minami–Azabu. Minato–ku, Tokyo 106–8573 Japan. 81–3–3440–3569

ASIA/PACIFIC:

Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852–26668334

Technical Information Center:

1–800–521–6274

HOME PAGE:

http://www.motorola.com/semiconductors

Document Comments

: FAX (512) 895-2638, Attn: RISC Applications Engineering

World Wide Web Addresses

: http://www.motorola.com/PowerPChttp://www.motorola.com/NetCommhttp://www.motorola.com/ColdFire

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LIMITED WARRANTY

Matrix Design warrants this product against defects in material and workmanship fora period of sixty (60) days from the original date of purchase.

This warranty extendsto the original customer only and is in lieu of all other warrants, includingimplied warranties of merchantability and fitness.

In no event will the seller beliable for any incidental or consequential damages. During the warranty period,Matrix Design will replace, at no charge, components that fail, provided the productis returned (properly packed and shipped prepaid) to Matrix Design at address below.Dated proof of purchase (such as a copy of the invoice) must be enclosed with theshipment. We will return the shipment prepaid via UPS.

This warranty does not apply if, in the opinion of Matrix Design, the product has beendamaged by accident, misuse, neglect, misapplication, or as a result of service ormodification (other than specified in the manual) by others.

Please send the board and cables with a complete description of the problem to:

Matrix Design & Manufacturing, Inc.2914 Montopolis Drive #290

Austin, TX 78741Phone: (512) 385-9210

Fax: (512) 385-9224http://www.cadreiii.com

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WARNING

This board generates, uses, and can radiate radio frequency energy and, if not installedproperly, may cause interference to radio communications. As temporarily permittedby regulation, it has not been tested for compliance with the limits for class acomputing devices pursuant to Subpart J of Part 15 of FCC rules, which are designedto provide reasonable protection against such interference. Operation of this productin a residential area is likely to cause interference, in which case the user, at his/herown expense, will be required to correct the interference.

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CONTENTS

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Chapter 1 M5407C3 Board

1.1 General Hardware Description ........................................................................... 1-11.2 System Memory .................................................................................................. 1-41.3 Serial Communication Channels......................................................................... 1-41.4 Parallel I/O Ports................................................................................................. 1-41.5 Programmable Timer/Counter ............................................................................ 1-51.6 PCI Controller..................................................................................................... 1-51.7 On Board Ethernet .............................................................................................. 1-51.8 System Configuration ......................................................................................... 1-51.9 Installation And Setup......................................................................................... 1-71.9.1 Unpacking....................................................................................................... 1-71.9.2 Preparing the Board for Use ........................................................................... 1-71.9.3 Providing Power to the Board......................................................................... 1-81.9.4 Selecting Terminal Baud Rate ........................................................................ 1-81.9.5 The Terminal Character Format ..................................................................... 1-81.9.6 Connecting the Terminal ................................................................................ 1-81.9.7 Using a Personal Computer as a Terminal...................................................... 1-81.10 System Power-up and Initial Operation............................................................ 1-111.11 M5407C3 Jumper Setup ................................................................................... 1-111.12 Using The BDM Port ........................................................................................ 1-13

Chapter 2 Using the Monitor/Debug Firmware

2.1 What Is dBUG?................................................................................................... 2-12.2 Operational Procedure ........................................................................................ 2-32.2.1 System Power-up ............................................................................................ 2-32.2.2 System Initialization ....................................................................................... 2-42.2.2.1 Hard RESET Button. .................................................................................. 2-52.2.2.2 ABORT Button. .......................................................................................... 2-52.2.2.3 Software Reset Command. ......................................................................... 2-62.3 Command Line Usage......................................................................................... 2-62.4 Commands .......................................................................................................... 2-6

Contents vPRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Motorola Confidential Proprietary

For More Information On This Product,

Go to: www.freescale.com

CONTENTS


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2.5 TRAP #15 Functions ........................................................................................ 2-392.5.1 OUT_CHAR ................................................................................................. 2-392.5.2 IN_CHAR ..................................................................................................... 2-392.5.3 CHAR_PRESENT........................................................................................ 2-402.5.4 EXIT_TO_dBUG.......................................................................................... 2-40

Chapter 3 Hardware Description and Reconfiguration

3.1 The Processor and Support Logic ....................................................................... 3-13.1.1 Processor......................................................................................................... 3-13.1.2 Reset Logic ..................................................................................................... 3-13.1.3 HIZ Signal....................................................................................................... 3-23.1.4 Clock Circuitry ............................................................................................... 3-23.1.5 Watchdog Timer ............................................................................................. 3-23.1.6 Interrupt Sources............................................................................................. 3-23.1.7 Internal SRAM................................................................................................ 3-33.1.8 The MCF5407 Registers and Memory Map ................................................... 3-43.1.9 Reset Vector Mapping .................................................................................... 3-53.1.10 TA Generation ................................................................................................ 3-53.1.11 Wait State Generator....................................................................................... 3-63.1.12 SDRAM DIMM.............................................................................................. 3-63.1.13 Flash ROM...................................................................................................... 3-73.1.14 JP15 Jumper and User’s Program................................................................... 3-73.2 Serial Communication Channels......................................................................... 3-73.2.1 MCF5407 UARTs........................................................................................... 3-73.2.2 I2C Module ..................................................................................................... 3-83.3 Real-Time Clock................................................................................................. 3-83.4 Parallel I/O Port .................................................................................................. 3-83.5 On-Board Ethernet Logic.................................................................................... 3-83.6 Connectors and Expansion Bus ........................................................................ 3-113.6.1 Expansion Connectors - J1 and J2 ................................................................ 3-113.6.2 The Debug Connector J5 .............................................................................. 3-13

Appendix A Configuring dBUG for Network Downloads

Appendix B ColdFire to ISA, IRQ7 and Reset Logic Abel Code

Appendix C

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CONTENTS


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SDRAM MUX PAL Equation

Appendix D Evaluation Board BOM

Appendix E Schematics

Appendix F Errata

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ILLUSTRATIONS

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1-1 5407 Block Diagram..................................................................................................... 1-31-2 Minimum System Configuration .................................................................................. 1-61-3 Pin assignment for female P4 (Terminal) connector. ................................................... 1-91-4 Jumper Locations ........................................................................................................ 1-102-1 Flow Diagram of dBUG Operational Mode. ................................................................ 2-43-1 The J5 Connector pin assignment ............................................................................... 3-14

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ILLUSTRATIONS

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TABLES

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1-1 Power Supply Connections ........................................................................................... 1-81-2 Jumper Settings........................................................................................................... 1-111-3 Jumper Settings........................................................................................................... 1-131-4 Jumper Settings........................................................................................................... 1-132-1 dBUG Command Summary.......................................................................................... 2-73-1 The M5407C3 Memory Map........................................................................................ 3-53-2 J1 Connector Pin Assignment..................................................................................... 3-113-3 J2 Connector pin assignment ...................................................................................... 3-12D-1 MCF5407EVM_BOM ................................................................................................. D-1

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TABLES

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xii M5407C3 User’s ManualPRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE




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Chapter 1 M5407C3 BoardThe M5407C3 is a versatile single board computer based on MCF5407 ColdFire®Processor. It may be used as a powerful microprocessor based controller in a variety ofapplications. With the addition of a terminal, it serves as a complete microcomputer forreference, development/evaluation, training and educational use. The user need onlyconnect an RS-232 compatible terminal (or a personal computer with terminal emulationsoftware) and power supply to have a fully functional system.

Provisions have been made to connect this board to additional user supplied peripherals, viathe Microprocessor Expansion Bus connectors, to expand memory and I/O capabilities.Additional peripherals may require bus buffers to minimize additional bus loading.

Furthermore, provisions have been made in the PC-board to permit configuration of theboard in a way, which best suits, an application. Options available are: upgrade to512MBytes SDRAM, 512K SRAM, and commercially available slave PCI devices.

1.1 General Hardware DescriptionThe M5407C3 board provides the RAM, Flash ROM, on board NE2000 compatibleEthernet interface (10M bit/sec), RS232, and all the built-in I/O functions of the MCF5407for learning and evaluating the attributes of the microprocessor. The MCF5407 is a memberof the ColdFire® family of processors. It is a 32-bit processor with 32-bit of address busand 32 lines of data. The processor has eight 32-bit data registers, eight 32-bit addressregisters, a 32-bit program counter, and a 16-bit status register.

The MCF5407 has a System Integration Module referred to as the SIM. The moduleincorporates many of the functions needed for system design. These include programmablechip-select logic, System Protection logic, General purpose I/O, and Interrupt controllerlogic. The chip-select logic can select up to eight memory banks and peripherals in additionto two banks of DRAM’s. The chip-select logic also allows programmable number ofwait-states to allow the use of slower memory (refer to MCF5407 User's Manual byMotorola for detailed information about the SIM.). The M5407C3 uses four (CS[3:0]) ofthe eight chip selects to access the Flash ROM’s (CS0), PCI bridge chip (CS1), SRAM(CS2; which is not populated on board, may be added by the user) and the Ethernet (CS3).The DRAM controller is used to control one DIMM module (up to 512M of SDRAM), both-RAS lines and all four -CAS lines are used. All other functions of the SIM are available

Chapter 1. M5407C3 Board 1-1

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE


General Hardware Description

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to the user.

The M5407C3 will work with most PC100 SDRAM DIMMs with a few exceptions. TheMCF5407 supports up to two banks of SDRAM, but double-sided DIMMs require 4 bankselects to access all of the chips. Therefore when using double-sided DIMMs only half ofthe available memory will be accessible. Since DIMMs are manufactured primarily for usein PCs the DQM signals on some DIMMS are routed so that the SDRAM can only beaccessed correctly as a 64-bit port so the M5407C3 will not be able to access the SDRAMcorrectly.

1-2 M5407C3 User’s Manual



General Hardware Description

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Figure 1-1 shows the 5407 block diagram.

Figure 1-1. 5407 Block Diagram

ExternalAddress

Bus

(1) RS232

drivers

(1) DB-9Debug

Osc.

Davicom10 Mb/sec

RJ45 Connector

ExternalDataBus

Control Signals

addr[31:0]data[31:0] Control Signals

PCI slot

SDRAM

32bit 3.3V

Module

SDRAM

ExternalMux (PAL)

(1) RS232

drivers

ColdFire® MCF5407

Bus Clk Drv

26-pin debug connector

512KB SyncFSRAM32 bit 3.3V(not populated)

Flash16 bit1MB minimum

Osc.

PCI Interface

PAL

Expansion Connector#1

Expansion Connector#2

Osc.

EEPROM

(1) DB-9

Buffers

Osc.

Real TImeClock




System Memory

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1.2 System MemoryOne on board Flash ROM (U12) is used to store the M5407C3 dBUG debugger/monitorfirmware in the lower 128 KBytes. The AM29PL160C-XX device is 16Mbits (16 bit by 1MByte) giving a total of 2MBytes of Flash memory.

The PCI bridge chip provides the interface to the Universal 32-bit PCI on board connectorallowing the user to experiment and develop new applications to commercially availableslave PCI based peripherals products.

The MCF5407 has 4KBytes of internal SRAM organized as two independentlyconfigurable 2 Kbyte blocks. each block can be configured for either data or instructionspace.

There is one 168-pin DIMM socket for SDRAM. System ships with 1M x 8 Bank x 16-BitsSDRAM totaling 16M of volatile memory. Various SDRAM configurations are supported.

The internal caches of the MCF5407 are non-blocking. The data cache is 8 KByte, 4-wayset-associative with a 16-byte line size. The instruction cache is 16 KBytes, 4-wayset-associative with a 16-byte line size. The ROM Monitor currently does not utilize thecaches, but programs downloaded with the ROM Monitor can use the cache.

The M5407C3 evaluation board has a foot print for 512 KByte SRAM but is unpopulated.

1.3 Serial Communication ChannelsThe MCF5407 has 2 built-in UART’s (UART0 and UART1) with independent baud rategenerators. The signals of both channels are passed through external Driver/Receivers tomake the channel compatible with RS-232. An RS232 serial cable with DB9 connectors isincluded. UART0 (P4) is used by the debugger for the user to access with a terminal. Inaddition, the signals of both channels are available on the 120 pin expansion connector J2.UART0 channel is the “TERMINAL” channel used by the debugger for communicationwith external terminal/PC. The “TERMINAL’ baud rate defaults to 19200.

1.4 Parallel I/O PortsMCF5407 offers one 16-bit general-purpose parallel I/O port. Each pin can be individuallyprogrammed as input or output. The parallel port bits PP[7:0] are multiplexed withTT[1:0], TM[2:0], DREQ[1:0], and XTIP. The second set of parallel port bits PP[15:8] ismultiplexed with address bus bits A[31:24]. Both bytes of the parallel port are controlledby the Pin Assignment Register (PAR). The pins are programmable on a pin by pin basis.The setting of the multiplexed pins is determined by the configuration byte during reset.After reset, PP[7:0] are configured as parallel port output pins and the PP[15:8] areconfigured as A[31:24]. PP[7:4] are general purpose outputs and PP[3:0] are used by theROM Monitor to automatically configure the SDRAM address lines via the U27 mux.




Programmable Timer/Counter

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1.5 Programmable Timer/CounterThe MCF5407 has two built in general purpose timer/counters. These timers are availableto the user. The signals for each timer are available on the 120 pin expansion connector J2.

1.6 PCI ControllerThe MCF5407 connects to the PCI controller (U17) via the PCI host interface. The PCIcontroller is configured for master mode. U18 contains the arbitration logic for the PCI bus.This logic is such that the PCI controller (U17) defaults to allowing the 5407 busmastership. A PCI card wishing to arbitrate the bus away from the controller must usesignal REQ# to request the bus. U18 will then arbitrate the bus away from U17 and assertGNT# to the PCI card to show that the card has been granted the bus. Similarly thecontroller can arbitrate the bus back using signals /REQ and /GNT. By default the controllercurrently has priority over the card in the equations in U18, if the user wanted to alter thispriority they could do so by editing file "ISA5407.abl" available on the ColdFire website(www.mot.com/coldfire).

1.7 On Board EthernetThe M5407C3 has an on board Ethernet (NE2000 compatible controller) operating at 10Mbits/sec. The on board dBUG ROM monitor is programmed to allow a user to downloadfiles from a network to memory in different formats. The current compiler formatssupported are S-Record, COFF, ELF, or Image. Refer to Appenix A for details on how toconfigure.

1.8 System ConfigurationThe M5407C3 board requires only the following items for minimum system configuration:

• The M5407C3 board (provided).

• Power supply, 7V to 14V DC with minimum of 1.0 Amp.

• RS-232C compatible terminal or a PC with terminal emulation software.

• RS-232 Communication cable (provided).

Refer to Section 2.2.2, “System Initialization” for initial setup.




System Configuration

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Figure 1-2 displays minimum system configuration.

Figure 1-2. Minimum System Configuration

BDMConnector

+7.0 to +14VDCInput Power

dBUG>

RS-232 TerminalOr PC




Installation And Setup

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1.9 Installation And SetupThe following sections describe all the steps needed to prepare the board for operation.Please read the following sections carefully before using the board. When you arepreparing the board for the first time, be sure to check that all jumpers are in the defaultlocations. Default marking are on the board next to the individual jumpers and a masterjumper table is on the underside of the board. After the board is functional in its defaultmode, you may use the Ethernet by following the instructions provided in Appendix A.

1.9.1 Unpacking

Unpack the computer board from its shipping box. Save the box for storing or reshipping.Refer to the following list and verify that all the items are present. You should havereceived:

• M5407C3 Single Board Computer

• M5407C3 User's Manual, this documentation

• One RS-232 communication cable

• One debug wiggler cable

• Programmers Reference Manual

• A selection of Third Party Developer Tools and Literature

NOTE:Avoid touching the mos devices. Static discharge can and willdamage these devices.

Once you verified that all the items are present, remove the board from its protective jacket.Check the board for any visible damage. Ensure that there are no broken, damaged, ormissing parts. If you have not received all the items listed above or they are damaged,please contact Matrix Design immediately.

1.9.2 Preparing the Board for Use

The board as shipped is ready to be connected to a terminal and the power supply withoutany need for modification. However, follow the steps below to insure proper operation fromthe first time you apply the power. Figure 3 Jumper Table and Locations shows theplacement of the jumpers and the connectors, which you need to refer to in the followingsections. The steps to be taken are:

a) Connecting the power supply.

b) Connecting the terminal.





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1.9.3 Providing Power to the Board

The board accepts two means of power supply connections. Connector P6 is a 2.1mmpower jack and P3 lever actuated connector. The board accepts 7V to 14V DC at 1.5 Ampvia either one of the connectors.

1.9.4 Selecting Terminal Baud Rate

The serial channel of MCF5407 which is used for serial communication has a built in timerused by the dBUG ROM monitor to generate the baud rate used to communicate with aterminal.. It can be programmed to a number of baud rates. After the power-up or a manualRESET, the dBUG ROM monitor firmware configures the channel for 19200 baud. Afterthe dBUG ROM monitor is running, you may issue the SET command to choose any baudrate supported by the dBUG ROM monitor. Refer to Chapter 2 for the discussion of thiscommand.

1.9.5 The Terminal Character Format

The character format of the communication channel is fixed at the power-up or RESET.The character format is 8 bits per character, no parity, and one stop bit. You need to insurethat your terminal or PC is set to this format.

1.9.6 Connecting the Terminal

The board is now ready to be connected to a terminal. Use the RS-232 male/female DB-9serial cable to connect the PC to the M5407C3. The cable has a 9-pin female D-subterminal connector at one end and a 9-pin male D-sub connector at the other end. Connectthe 9-pin male connector to P4 connector on M5407C3. Connect the 9-pin femaleconnector to one of the available serial communication channels normally referred to asCOM1 (COM2, etc.) on the IBM PC’s or compatible. Depending on the kind of serialconnector on the back of your PC, the connector on your PC may be a male 25-pin or 9-pin.You may need to obtain a 9-pin-to-25-pin adapter to make the connection. If you need tobuild an adapter, refer to Figure 2 which shows the pin assignment for the 9-pin connectoron the board.

1.9.7 Using a Personal Computer as a Terminal

You may use your personal computer as a terminal provided you also have a terminalemulation software such as PROCOMM, KERMIT, QMODEM, Windows 95/98/2000

Table 1-1. Power Supply Connections

Contact Number Voltage

1 +7–14V DC

2 Ground





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Hyper Terminal or similar packages. Then connect as described in 1.9.6, “Connecting theTerminal.”

Once the connection to the PC is made, you are ready to power-up the PC and run theterminal emulation software. When you are in the terminal mode, you need to select thebaud rate and the character format for the channel. Most terminal emulation softwarepackages provide a command known as "Alt-p" (press the p key while pressing the Alt key)to choose the baud rate and character format. Make sure you select 8 bits, no parity, onestop bit, see section The Terminal Character Format. Then, select the baud rate as 19200.Now you are ready to apply power to the board.

Figur 1-3 shows pin assignments for female terminal connector.

Figure 1-3. Pin assignment for female P4 (Terminal) connector.

Pin assignments are as follows.

1. Data Carrier Detect, Output (shorted to pins 4 and 6).

2. Receive Data, Output from board (receive refers to terminal side).

3. Transmit Data, Input to board (transmit refers to terminal side).

4. Data Terminal Ready, input (shorted to pin 1 and 6).

5. Signal Ground.

6. Data Set Ready, Output (shorted to pins 1 and 4).

7. Request to Send, input.

8. Clear to send, output.

9. Not connected.

Figure 1-4 shows jumper locations.

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5





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Figure 1-4. Jumper Locations




System Power-up and Initial Operation

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1.10 System Power-up and Initial OperationNow that you have connected all the cables, you may apply power to the board. After poweris applied, the dBUG initializes the board then displays the power-up message on theterminal, which includes the amount of memory present.

Hard ResetDRAM Size: 32M

Copyright 1995-2000 Motorola, Inc. All Rights Reserved.ColdFire MCF5407 EVS Firmware v2e.1a.1a (Build XXX on XXX XX 20XX17:27:52)

Enter 'help' for help.

dBUG>

The board is now ready for operation under the control of the debugger as described inChapter 2. If you do not get the above response, perform the following checks:

1. Make sure that the power supply is properly configured for polarity, voltage level, and current capability (~1A) and is connected to the board.

2. Check that the terminal and board are set for the same character format and baud.

3. Press the RESET button to insure that the board has been initialized properly.

If dBUG does not come up try removing power from the board and then powering up theboard with the SDRAM DIMM removed. The LEDs (D1-D8) should flash indicating thatthere is a problem with the serial cable, terminal, or SDRAM jumpers.

If you still are not receiving the proper response, your board may have been damaged inshipping. Contact Matrix Design for further instructions.

1.11 M5407C3 Jumper SetupJumper settings are as follows:

Note ‘*’ is used to indicate that default setting.‘**’ is used to indicate mandatory setting for proper operation.

Table 1-2. Jumper Settings

Jumper Function

JP1 * ON LED D10 driven by TOUT0

OFF LED D10 NOT driven by TOUT0

JP2 * ON LED D9 driven by TOUT1

OFF LED D9 NOT driven by TOUT1

JP[5:3]/D[2:0]/DIV[2:0]

Ratio of CLKIN/PCLK

Valid CLKIN Frequency Ranges (MHz) forCLKIN/PCLK. NOTE: PSTCLK=1/2 PCLK




M5407C3 Jumper Setup

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On/On/x Reserved ---

On/Off/On Reserved ---

On/Off/Off *1/3 40.0–54.0/120.0–162 MHz

Off/On/On 1/4 25.0–40.5/100.0–162 MHz

Off/On/Off 1/5 25.0–32.4/125.0–162 MHz

Off/Off/On 1/6 25.0–27.0/150.0–162 MHz

Off/Off/Off Reserved ---

JP6/D[3]/BE[3:0] CONF

ON / 0 BE[3:0] is enabled as byte write enables only

* OFF / 1 BE[3:0] is enabled as byte enables for reads & write

JP7/D[4]/ADDR_CONF

ON / 0 PP[15:0], defaulted to inputs upon reset

* OFF / 1 ADDR[31:24]/TIP/DREQ[1:0]/TM[2:1]

JP9/D[6]/PS1 JP8/D[5]/PS0 Boot CS0 Port Size at Reset

ON / 0 ON / 0 32-bit Port

ON / 0 OFF / 1 8-bit Port

OFF / 1 ON / 0 16-bit Port

* OFF / 1 * OFF / 1 16-bit Port

JP10/D[7]/AA ON / 0 Boot CS0 Auto Acknowledge (AA) DISABLED

* OFF / 1 Boot CS AA Enabled with 15 wait states

JP11 * ON EVCC (+3.3V) Power to ColdFire MCF5407 I/O

JP12 ** ON IVCC (+1.8V) Power to ColdFire MCF5407 core

JP13 * ON Pull up enabled on !DREQ1 / PP[5]

JP14 * ON Pull up enabled on !DREQ0 / PP[6]

JP15 * 1-2 Boot ROM Monitor from Flash

2-3 Boot User Code from user Flash Space

JP16 * 1-2 Enable writes to PCI EEPROM1

2-3 Disable writes to PCI EEPROM1

JP17 * 1-2 +3.3 V to J5 Debug Header Pin 9

2-3 +1.8 V to J5 Debug Header Pin 9

JP18 ** 1-2 Default Clocking

2-3 Alternate Clocking

JP19 ** OFF Default Clocking

ON Alternate Clocking

JP20 ** 1-2 Default Core Power (+1.8V)

2-3 Alternate Core Power (+3.3V)

1 JP16 functionality is opposite that of the silkscreen. The table is correct.

Table 1-2. Jumper Settings (Continued)

Jumper Function




Using The BDM Port

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1.12 Using The BDM PortThe MCF5407 has a built in debug mechanism referred to as BDM (background debugmodule). The M5407C3 has the Motorola defined debug module connector, J5, to facilitatethis connection.


JP21 JP22 JP23 JP24 Function

* 1-2 * 1-2 * 1-2 * 1-2 Driven by PP[3:0]

2-3 2-3 2-3 2-3 8 col, 11 row

OFF 2-3 2-3 2-3 9 col, 11 row

2-3 OFF 2-3 2-3 10 col, 11 row

OFF OFF 2-3 2-3 8 col, 12 row

2-3 2-3 OFF 2-3 9 col, 12 row

OFF 2-3 OFF 2-3 10 col, 12 row

2-3 OFF OFF 2-3 11 col, 12 row

OFF OFF OFF 2-3 8 col, 13 row

2-3 2-3 2-3 OFF 9 col, 13 row

OFF 2-3 2-3 OFF 10 col, 13 row

2-3 OFF 2-3 OFF 11 col, 13 row


Jumper Function

JP251

1 The settings for JP25 and JP29 differ from those given on the back of the silkscreen. The settings listed in this table are correct.

*ON Enable serial clock SCL to PCI EEPROM

JP26 * 1-2 +3.3 V to J5 Debug Header Pin 25

2-3 +1.8 V to J5 Debug Header Pin 25

JP27 * 1-2 ColdFire CS1 used on PCI !SELECT

2-3 ColdFire !A31 used on PCI !SELECT

JP28 * 1-2 ColdFire Normal/BDM Mode

2-3 ColdFire Normal/JTAG Mode

JP291 *ON Enable serial data SDA to PCI EEPROM

JP30 * 1-2 STROBE signal on PCI controller tied to GND

2-3 STROBE signal on PCI controller tied to !TS




Using The BDM Port

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In order to use the BDM, simply connect the 26-pin connector at the end of the BDMwiggler cable provided Motorola from P&E Microcomputer Systems to the J5 connector.No special setting is needed. Refer to the ColdFire® User's Manual BDM Section foradditional instructions.

NOTE:BDM functionality and use is supported via third partydeveloper software and hardware tools.




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Chapter 2 Using the Monitor/Debug FirmwareThe M5407C3 single board computer has a resident firmware package that provides aself-contained programming and operating environment. The firmware, named dBUG,provides the user with monitor/debug interface, inline assembler and disassembly, programdownload, register and memory manipulation, and I/O control functions. This Chapter is ahow-to-use description of the dBUG package, including the user interface and commandstructure.

2.1 What Is dBUG?dBUG is a traditional ROM monitor/debugger that offers a comfortable and intuitivecommand line interface that can be used to download and execute code. It contains all theprimary features needed in a debugger to create a useful debugging environment.

dBUG is a resident firmware package for the ColdFire® family single board computers.The firmware (stored in one 1Mx16 Flash ROM device) provides a self-containedprogramming and operating environment. dBUG interacts with the user throughpre-defined commands that are entered via the terminal. These commands are defined inSection 2.4, “Commands.”

The user interface to dBUG is the command line. A number of features have beenimplemented to achieve an easy and intuitive command line interface.

dBUG assumes that an 80x24 character dumb-terminal is utilized to connect to thedebugger. For serial communications, dBUG requires eight data bits, no parity, and onestop bit, 8N1. The default baud rate is 19200 but can be changed after the power-up.

The command line prompt is “dBUG> “. Any dBUG command may be entered from thisprompt. dBUG does not allow command lines to exceed 80 characters. Wherever possible,dBUG displays data in 80 columns or less. dBUG echoes each character as it is typed,eliminating the need for any “local echo” on the terminal side.

In general, dBUG is not case sensitive. Commands may be entered either in upper or lowercase, depending upon the user’s equipment and preference. Only symbol names requirethat the exact case be used.

Chapter 2. Using the Monitor/Debug Firmware 2-1



What Is dBUG?

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Most commands can be recognized by using an abbreviated name. For instance, entering“h” is the same as entering “help”. Thus, it is not necessary to type the entire commandname.

The commands DI, GO, MD, STEP and TRACE are used repeatedly when debugging.dBUG recognizes this and allows for repeated execution of these commands with minimaltyping. After a command is entered, simply press <RETURN> or <ENTER> to invoke thecommand again. The command is executed as if no command line parameters wereprovided.

An additional function called the "TRAP 15 handler" allows the user program to utilizevarious routines within dBUG. The TRAP 15 handler is discussed at the end of this chapter.

The operational mode of dBUG is demonstrated in Figure 2-1. After the systeminitialization, the board waits for a command-line input from the user terminal. When aproper command is entered, the operation continues in one of the two basic modes. If thecommand causes execution of the user program, the dBUG firmware may or may not bere-entered, depending on the discretion of the user. For the alternate case, the commandwill be executed under control of the dBUG firmware, and after command completion, thesystem returns to command entry mode.

During command execution, additional user input may be required depending on thecommand function.

For commands that accept an optional <width> to modify the memory access size, the validvalues are:

• B8-bit (byte) access

• W16-bit (word) access

• L32-bit (long) access

When no <width> option is provided, the default width is .W, 16-bit.

The core ColdFire® register set is maintained by dBUG. These are listed below:

• A0-A7

• D0-D7

• PC

• SR

All control registers on ColdFire® are not readable by the supervisor-programming model,and thus not accessible via dBUG. User code may change these registers, but caution mustbe exercised as changes may render dBUG inoperable.

A reference to “SP” (stack pointer) actually refers to general purpose address registerseven, “A7."




Operational Procedure

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2.2 Operational ProcedureSystem power-up and initial operation are described in detail in Chapter 1. This informationis repeated here for convenience and to prevent possible damage.

2.2.1 System Power-up• Be sure the power supply is connected properly prior to power-up.

• Make sure the terminal is connected to TERMINAL (P4) connector.

• Turn power on to the board.





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Figur 2-1shows the dUBG operational mode.

Figure 2-1. Flow Diagram of dBUG Operational Mode.

2.2.2 System Initialization

The act of powering up the board will initialize the system. The processor is reset anddBUG is invoked.

dBUG performs the following configurations of internal resources during the initialization.





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The instruction cache is invalidated and disabled. The Vector Base Register, VBR, pointsto the Flash. However, a copy of the exception table is made at address $00000000 inSDRAM. To take over an exception vector, the user places the address of the exceptionhandler in the appropriate vector in the vector table located at 0x00000000, and then pointsthe VBR to 0x00000000.

The Software Watchdog Timer is disabled and internal timers are placed in a stop condition.Interrupt controller registers initialized with unique interrupt level/priority pairs. Pleaserefer to the dBUG source files on theColdFire website (www.motorola.com/coldfire) for thecomplete initialization code sequence.

After initialization, the terminal will display:

Hard ResetDRAM Size: 32M

Copyright 1995-2000 Motorola, Inc. All Rights Reserved.ColdFire MCF5407 EVS Firmware v2e.1a.1a (Build XXX on XXX XX 20XX17:27:52)

Enter 'help' for help.

dBUG>

If you did not get this response check the setup. Refer to Section 1.10 System Power-Upand Initial Operation. Note the date ‘xxx 199x xx:xx:xx’ may vary in different revisions.

Other means can be used to re-initialize the M5407C3 Computer Board firmware. Thesemeans are discussed in the following paragraphs.

2.2.2.1 Hard RESET Button.

Hard RESET (S1) is the button. Depressing this button causes all processes to terminate,resets the MCF5407 processor and board logic and restarts the dBUG firmware. Pressingthe RESET button would be the appropriate action if all else fails.

2.2.2.2 ABORT Button.

ABORT (S2) is the button located next to RESET button. The abort function causes aninterrupt of the present processing (a level 7 interrupt on MCF5407) and gives control tothe dBUG firmware. This action differs from RESET in that no processor register ormemory contents are changed, the processor and peripherals are not reset, and dBUG is notrestarted. Also, in response to depressing the ABORT button, the contents of the MCF5407core internal registers are displayed.

The abort function is most appropriate when software is being debugged. The user caninterrupt the processor without destroying the present state of the system. This isaccomplished by forcing a non-maskable interrupt that will call a dBUG routine that willsave the current state of the registers to shadow registers in the monitor for display to theuser. The user will be returned to the ROM monitor prompt after exception handling.




Command Line Usage

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2.2.2.3 Software Reset Command.

dBUG does have a command that causes the dBUG to restart as if a hardware reset wasinvoked. The command is "RESET".

2.3 Command Line UsageThe user interface to dBUG is the command line. A number of features have beenimplemented to achieve an easy and intuitive command line interface.

dBUG assumes that an 80x24 ASCII character dumb terminal is used to connect to thedebugger. For serial communications, dBUG requires eight data bits, no parity, and one stopbit (8N1). The baud rate default is19200 bps — a speed commonly available fromworkstations, personal computers and dedicated terminals.

The command line prompt is: dBUG>

Any dBUG command may be entered from this prompt. dBUG does not allow commandlines to exceed 80 characters. Wherever possible, dBUG displays data in 80 columns orless. dBUG echoes each character as it is typed, eliminating the need for any local echo onthe terminal side.

The <Backspace> and <Delete> keys are recognized as rub-out keys for correctingtypographical mistakes.

Command lines may be recalled using the <Control> U, <Control> D and <Control> R keysequences. <Control> U and <Control> D cycle up and down through previous commandlines. <Control> R recalls and executes the last command line.

In general, dBUG is not case-sensitive. Commands may be entered either in uppercase orlowercase, depending upon the user’s equipment and preference. Only symbol namesrequire that the exact case be used.

Most commands can be recognized by using an abbreviated name. For instance, entering his the same as entering help. Thus it is not necessary to type the entire command name.

The commands DI, GO, MD, STEP and TRACE are used repeatedly when debugging.dBUG recognizes this and allows for repeated execution of these commands with minimaltyping. After a command is entered, press the <Return> or <Enter> key to invoke thecommand again. The command is executed as if no command line parameters wereprovided.

2.4 CommandsThis section lists the commands that are available with all versions of dBUG. Some boardor CPU combinations may use additional commands not listed below.




Commands

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Table 2-1. dBUG Command SummaryMNEMONIC SYNTAX DESCRIPTION

ASM asm <<addr> stmt> AssembleBC bc addr1 addr2 length Block CompareBF bf <width> begin end data <inc> Block FillBM bm begin end dest Block MoveBR br addr <-r> <-c count> <-t trigger> BreakpointBS bs <width> begin end data Block SearchDC dc value Data ConvertDI di<addr> DisassembleDL dl <offset> Download SerialDN dn <-c> <-e> <-i> <-s <-o offset>> <filename> Download NetworkGO go <addr> ExecuteGT gt addr Execute ToHELP help <command> HelpIRD ird <module.register> Internal Register DisplayIRM irm module.register data Internal Register ModifyLR lr<width> addr Loop ReadLW lw<width> addr data Loop WriteMD md<width> <begin> <end> Memory DisplayMM mm<width> addr <data> Memory ModifyMMAP mmap Memory Map DisplayRD rd <reg> Register DisplayRM rm reg data Register ModifyRESET reset ResetSD sd Stack DumpSET set <option value> Set ConfigurationsSHOW show <option> Show ConfigurationsSTEP step Step (Over)SYMBOL symbol <symb> <-a symb value> <-r symb> <-C|l|s>Symbol ManagementTRACE trace <num> Trace (Into)UPDBUG updbug Update dBUGUPUSER upuser <bytes> Update User FlashVERSION version Show Version




Commands

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ASM AssemblerUsage: ASM <<addr> stmt>

The ASM command is a primitive assembler. The <stmt> is assembled and the resultingcode placed at <addr>. This command has an interactive and non-interactive mode ofoperation.

The value for address <addr> may be an absolute address specified as a hexadecimal value,or a symbol name. The value for stmt must be valid assembler mnemonics for the CPU.

For the interactive mode, the user enters the command and the optional <addr>. If theaddress is not specified, then the last address is used. The memory contents at the addressare disassembled, and the user prompted for the new assembly. If valid, the new assemblyis placed into memory, and the address incremented accordingly. If the assembly is notvalid, then memory is not modified, and an error message produced. In either case, memoryis disassembled and the process repeats.

The user may press the <Enter> or <Return> key to accept the current memory contentsand skip to the next instruction, or a enter period to quit the interactive mode.

In the non-interactive mode, the user specifies the address and the assembly statement onthe command line. The statement is the assembled, and if valid, placed into memory,otherwise an error message is produced.

Examples:

To place a NOP instruction at address 0x00010000, the command is:

asm 10000 nop

To interactively assembly memory at address 0x00400000, the command is:

asm 400000




Commands

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BC Block CompareUsage: BC addr1 addr2 length

The BC command compares two contiguous blocks of memory on a byte by byte basis. Thefirst block starts at address addr1 and the second starts at address addr2, both of lengthbytes.

If the blocks are not identical, the address of the first mismatch is displayed. The value foraddresses addr1 and addr2 may be an absolute address specified as a hexadecimal value ora symbol name. The value for length may be a symbol name or a number convertedaccording to the user defined radix (hexadecimal by default).

Example:

To verify that the data starting at 0x20000 and ending at 0x30000 is identical to the datastarting at 0x80000, the command is:

bc 20000 80000 10000




Commands

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BF Block FillUsage: BF<width> begin end data <inc>

The BF command fills a contiguous block of memory starting at address begin, stopping ataddress end, with the value data. <Width> modifies the size of the data that is written. If no<width> is specified, the default of word sized data is used.

The value for addresses begin and end may be an absolute address specified as ahexadecimal value, or a symbol name. The value for data may be a symbol name, or anumber converted according to the user-defined radix, normally hexadecimal.

The optional value <inc> can be used to increment (or decrement) the data value during thefill.

This command first aligns the starting address for the data access size, and then incrementsthe address accordingly during the operation. Thus, for the duration of the operation, thiscommand performs properly-aligned memory accesses.

Examples:

To fill a memory block starting at 0x00020000 and ending at 0x00040000 with the value0x1234, the command is:

bf 20000 40000 1234

To fill a block of memory starting at 0x00020000 and ending at 0x0004000 with a bytevalue of 0xAB, the command is:

bf.b 20000 40000 AB

To zero out the BSS section of the target code (defined by the symbols bss_start andbss_end), the command is:

bf bss_start bss_end 0

To fill a block of memory starting at 0x00020000 and ending at 0x00040000 with data thatincrements by 2 for each <width>, the command is:

bf 20000 40000 0 2




Commands

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BM Block MoveUsage: BM begin end dest

The BM command moves a contiguous block of memory starting at address begin andstopping at address end to the new address dest. The BM command copies memory as aseries of bytes, and does not alter the original block.

The values for addresses begin, end, and dest may be absolute addresses specified ashexadecimal values, or symbol names. If the destination address overlaps the block definedby begin and end, an error message is produced and the command exits.

Examples:

To copy a block of memory starting at 0x00040000 and ending at 0x00080000 to thelocation 0x00200000, the command is:

bm 40000 80000 200000

To copy the target code’s data section (defined by the symbols data_start and data_end) to0x00200000, the command is:

bm data_start data_end 200000

NOTE:Refer to “upuser” command for copying code/data into Flashmemory.




Commands

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BR BreakpointsUsage: BR addr <-r> <-c count> <-t trigger>

The BR command inserts or removes breakpoints at address addr. The value for addr maybe an absolute address specified as a hexadecimal value, or a symbol name. Count andtrigger are numbers converted according to the user-defined radix, normally hexadecimal.

If no argument is provided to the BR command, a listing of all defined breakpoints isdisplayed.

The -r option to the BR command removes a breakpoint defined at address addr. If noaddress is specified in conjunction with the -r option, then all breakpoints are removed.

Each time a breakpoint is encountered during the execution of target code, its count valueis incremented by one. By default, the initial count value for a breakpoint is zero, but the -coption allows setting the initial count for the breakpoint.

Each time a breakpoint is encountered during the execution of target code, the count valueis compared against the trigger value. If the count value is equal to or greater than the triggervalue, a breakpoint is encountered and control returned to dBUG. By default, the initialtrigger value for a breakpoint is one, but the -t option allows setting the initial trigger forthe breakpoint.

If no address is specified in conjunction with the -c or -t options, then all breakpoints areinitialized to the values specified by the -c or -t option.

Examples:

To set a breakpoint at the C function main() (symbol _main; see “symbol” command), thecommand is:

br _main

When the target code is executed and the processor reaches main(), control will be returnedto dBUG.

To set a breakpoint at the C function bench() and set its trigger value to 3, the command is:

br _bench -t 3

When the target code is executed, the processor must attempt to execute the functionbench() a third time before returning control back to dBUG.

To remove all breakpoints, the command is:

br -r




Commands

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BS Block SearchUsage: BS<width> begin end data

The BS command searches a contiguous block of memory starting at address begin,stopping at address end, for the value data. <Width> modifies the size of the data that iscompared during the search. If no <width> is specified, the default of word sized data isused.

The values for addresses begin and end may be absolute addresses specified as hexadecimalvalues, or symbol names. The value for data may be a symbol name or a number convertedaccording to the user-defined radix, normally hexadecimal.


Examples:

To search for the 16-bit value 0x1234 in the memory block starting at 0x00040000 andending at 0x00080000:

bs40000 80000 1234

This reads the 16-bit word located at 0x00040000 and compares it against the 16-bit value0x1234. If no match is found, then the address is incremented to 0x00040002 and the next16-bit value is read and compared.

To search for the 32-bit value 0xABCD in the memory block starting at 0x00040000 andending at 0x00080000:

bs.l40000 80000 ABCD

This reads the 32-bit word located at 0x00040000 and compares it against the 32-bit value0x0000ABCD. If no match is found, then the address is incremented to 0x00040004 andthe next 32-bit value is read and compared.




Commands

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DC Data ConversionUsage: DC data

The DC command displays the hexadecimal or decimal value data in hexadecimal, binary,and decimal notation.

The value for data may be a symbol name or an absolute value. If an absolute value passedinto the DC command is prefixed by ‘0x’, then data is interpreted as a hexadecimal value.Otherwise data is interpreted as a decimal value.

All values are treated as 32-bit quantities.

Examples:

To display the decimal and binary equivalent of 0x1234, the command is:

dc 0x1234

To display the hexadecimal and binary equivalent of 1234, the command is:

dc 1234




Commands

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DI DisassembleUsage: DI <addr>

The DI command disassembles target code pointed to by addr. The value for addr may bean absolute address specified as a hexadecimal value, or a symbol name.

Wherever possible, the disassembler will use information from the symbol table to producea more meaningful disassembly. This is especially useful for branch target addresses andsubroutine calls.

The DI command attempts to track the address of the last disassembled opcode. If noaddress is provided to the DI command, then the DI command uses the address of the lastopcode that was disassembled.

The DI command is repeatable.

Examples:

To disassemble code that starts at 0x00040000, the command is:

di 40000

To disassemble code of the C function main(), the command is:

di _main




Commands

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DL Download ConsoleUsage: DL <offset>

The DL command performs an S-record download of data obtained from the console,typically a serial port. The value for offset is converted according to the user-defined radix,normally hexadecimal. Please reference the ColdFire Microprocessor FamilyProgrammer’s Reference Manual for details on the S-Record format.

If offset is provided, then the destination address of each S-record is adjusted by offset.

The DL command checks the destination download address for validity. If the destinationis an address outside the defined user space, then an error message is displayed anddownloading aborted.

If the S-record file contains the entry point address, then the program counter is set to reflectthis address.

Examples:

To download an S-record file through the serial port, the command is:

dl

To download an S-record file through the serial port, and add an offset to the destinationaddress of 0x40, the command is:

dl 0x40




Commands

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DN Download NetworkUsage: DN <-c> <-e> <-i> <-s> <-o offset> <filename>

The DN command downloads code from the network. The DN command handle files whichare either S-record, COFF, ELF or Image formats. The DN command uses Trivial FileTransfer Protocol (TFTP) to transfer files from a network host.

In general, the type of file to be downloaded and the name of the file must be specified tothe DN command. The -c option indicates a COFF download, the -e option indicates anELF download, the -i option indicates an Image download, and the -s indicates an S-recorddownload. The -o option works only in conjunction with the -s option to indicate anoptional offset for S-record download. The filename is passed directly to the TFTP serverand therefore must be a valid filename on the server.

If neither of the -c, -e, -i, -s or filename options are specified, then a default filename andfiletype will be used. Default filename and filetype parameters are manipulated using theSET and SHOW commands.

The DN command checks the destination download address for validity. If the destinationis an address outside the defined user space, then an error message is displayed anddownloading aborted.

For ELF and COFF files which contain symbolic debug information, the symbol tables areextracted from the file during download and used by dBUG. Only global symbols are keptin dBUG. The dBUG symbol table is not cleared prior to downloading, so it is the user’sresponsibility to clear the symbol table as necessary prior to downloading.

If an entry point address is specified in the S-record, COFF or ELF file, the program counteris set accordingly.

Examples:

To download an S-record file with the name “srec.out”, the command is:

dn -s srec.out

To download a COFF file with the name “coff.out”, the command is:

dn -c coff.out

To download a file using the default filetype with the name “bench.out”, the command is:

dn bench.out

To download a file using the default filename and filetype, the command is:

dn




Commands

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GO ExecuteUsage: GO <addr>

The GO command executes target code starting at address addr. The value for addr may bean absolute address specified as a hexadecimal value, or a symbol name.

If no argument is provided, the GO command begins executing instructions at the currentprogram counter.

When the GO command is executed, all user-defined breakpoints are inserted into the targetcode, and the context is switched to the target program. Control is only regained when thetarget code encounters a breakpoint, illegal instruction, trap #15 exception, or otherexception which causes control to be handed back to dBUG.

The GO command is repeatable.

Examples:

To execute code at the current program counter, the command is:

go

To execute code at the C function main(), the command is:

go _main

To execute code at the address 0x00040000, the command is:

go 40000




Commands

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GT Execute ToUsage: GT addr

The GT command inserts a temporary breakpoint at addr and then executes target codestarting at the current program counter. The value for addr may be an absolute addressspecified as a hexadecimal value, or a symbol name.

When the GT command is executed, all breakpoints are inserted into the target code, andthe context is switched to the target program. Control is only regained when the target codeencounters a breakpoint, illegal instruction, or other exception which causes control to behanded back to dBUG.

Examples:

To execute code up to the C function bench(), the command is:

gt _bench




Commands

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IRD Internal Register DisplayUsage: IRD <module.register>

This command displays the internal registers of different modules inside the MCF5407. Inthe command line, module refers to the module name where the register is located andregister refers to the specific register to display.

The registers are organized according to the module to which they belong. The availablemodules on the MCF5407 are CS, DMA0, DMA1, DMA2, DMA3, DRAMC, PP, MBUS,SIM, TIMER1, TIMER2, UART0 and UART1. Refer to the MCF5407 user’s manual formore information on these modules and the registers they contain.

Example:

ird sim.rsr




Commands

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IRM Internal Register ModifyUsage: IRM module.register data

This command modifies the contents of the internal registers of different modules inside theMCF5407. In the command line, module refers to the module name where the register islocated and register refers to the specific register to modify. The data parameter specifiesthe new value to be written into the register.

The registers are organized according to the module to which they belong. The availablemodules on the MCF5407 are CS, DMA0, DMA1, DMA2, DMA3, DRAMC, PP, MBUS,SIM, TIMER1, TIMER2, UART0 and UART1. Refer to the MCF5407 user’s manual formore information on these modules and the registers they contain.

Example:

To modify the TMR register of the first Timer module to the value 0x0021, the command is:

irm timer1.tmr 0021




Commands

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HELP HelpUsage: HELP <command>

The HELP command displays a brief syntax of the commands available within dBUG. Inaddition, the address of where user code may start is given. If command is provided, thena brief listing of the syntax of the specified command is displayed.

Examples:

To obtain a listing of all the commands available within dBUG, the command is:

help

To obtain help on the breakpoint command, the command is:

help br




Commands

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LR Loop ReadUsage: LR<width> addr

The LR command continually reads the data at addr until a key is pressed. The optional<width> specifies the size of the data to be read. If no <width> is specified, the commanddefaults to reading word sized data.

Example:

To continually read the longword data from address 0x20000, the command is:

lr.l 20000




Commands

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LW Loop WriteUsage: LW<width> addr data

The LW command continually writes data to addr. The optional width specifies the size ofthe access to memory. The default access size is a word.

Examples:

To continually write the longword data 0x12345678 to address 0x20000, the command is:

lw.l 20000 12345678

Note that the following command writes 0x78 into memory:

lw.b 20000 12345678




Commands

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MD Memory DisplayUsage: MD<width> <begin> <end>

The MD command displays a contiguous block of memory starting at address begin andstopping at address end. The values for addresses begin and end may be absolute addressesspecified as hexadecimal values, or symbol names. Width modifies the size of the data thatis displayed. If no <width> is specified, the default of word sized data is used.

Memory display starts at the address begin. If no beginning address is provided, the MDcommand uses the last address that was displayed. If no ending address is provided, thenMD will display memory up to an address that is 128 beyond the starting address.


Examples:

To display memory at address 0x00400000, the command is:

md 400000

To display memory in the data section (defined by the symbols data_start and data_end),the command is:

md data_start

To display a range of bytes from 0x00040000 to 0x00050000, the command is:

md.b 40000 50000

To display a range of 32-bit values starting at 0x00040000 and ending at 0x00050000:

md.l 40000 50000




Commands

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MM Memory ModifyUsage: MM<width> addr <data>

The MM command modifies memory at the address addr. The value for addr may be anabsolute address specified as a hexadecimal value, or a symbol name. Width specifies thesize of the data that is modified. If no <width> is specified, the default of word sized datais used. The value for data may be a symbol name, or a number converted according to theuser-defined radix, normally hexadecimal.

If a value for data is provided, then the MM command immediately sets the contents of addrto data. If no value for data is provided, then the MM command enters into a loop. The loopobtains a value for data, sets the contents of the current address to data, increments theaddress according to the data size, and repeats. The loop terminates when an invalid entryfor the data value is entered, i.e., a period.


Examples:

To set the byte at location 0x00010000 to be 0xFF, the command is:

mm.b 10000 FF

To interactively modify memory beginning at 0x00010000, the command is:

mm 10000




Commands

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MMAP Memory Map DisplayUsage: mmap

This command displays the memory map information for the M5407C3 evaluation board.The information displayed includes the type of memory, the start and end address of thememory, and the port size of the memory. The display also includes information on how theChip-selects are used on the board.

Here is an example of the output from this command:

Type Start End Port Size

---------------------------------------------------

SDRAM 0x00000000 0x00FFFFFF 32-bit

Vector Table 0x00000000 0x000003FF 32-bit

USER SPACE 0x00020000 0x00FFFFFF 32-bit

MBAR 0x10000000 0x100003FF 32-bit

Internal SRAM0 0x20000000 0x200007FF 32-bit

Internal SRAM1 0x20000800 0x20000FFF 32-bit

External SRAM 0x30000000 0x3007FFFF 32-bit

Ethernet IO 0x40000300 0x400FFFFF 16-bit

Flash 0x7FE00000 0x7FFFFFFF 16-bit

PCI 0xFFFF0000 0xFFFF3FFF 32-bit

Chip Selects

----------------

CS0 Flash

CS1 PCI

CS2 Ext SRAM

CS3 Ethernet

CS4 not in use

CS5 not in use

CS6 not in use

CS7 not in use




Commands

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RD Register DisplayUsage: RD <reg>

The RD command displays the register set of the target. If no argument for reg is provided,then all registers are displayed. Otherwise, the value for reg is displayed.

dBUG preserves the registers by storing a copy of the register set in a buffer. The RDcommand displays register values from the register buffer.

Examples:

To display all the registers and their values, the command is:

rd

To display only the program counter:

rd pc

Here is an example of the output from this command:

PC: 00000000 SR: 2000 [t.Sm.000...xnzvc]

An: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 01000000

Dn: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000




Commands

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RM Register ModifyUsage: RM reg data

The RM command modifies the contents of the register reg to data. The value for reg isthe name of the register, and the value for data may be a symbol name, or it is convertedaccording to the user-defined radix, normally hexadecimal.

dBUG preserves the registers by storing a copy of the register set in a buffer. The RMcommand updates the copy of the register in the buffer. The actual value will not be writtento the register until target code is executed.

Examples:

To change register D0 on MC68000 and ColdFire to contain the value 0x1234, thecommand is:

rm D0 1234




Commands

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RESET Reset the Board and dBUGUsage: RESET

The RESET command resets the board and dBUG to their initial power-on states.

The RESET command executes the same sequence of code that occurs at power-on. If theRESET command fails to reset the board adequately, cycle the power or press the resetbutton.

Examples:

To reset the board and clear the dBUG data structures, the command is:

reset




Commands

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SET Set ConfigurationsUsage: SET <option value>

The SET command allows the setting of user-configurable options within dBUG. With noarguments, SET displays the options and values available. The SHOW command displaysthe settings in the appropriate format. The standard set of options is listed below.

• baud - This is the baud rate for the first serial port on the board. All communications between dBUG and the user occur using either 9600 or 19200 bps, eight data bits, no parity, and one stop bit, 8N1.

• base - This is the default radix for use in converting a number from its ASCII text representation to the internal quantity used by dBUG. The default is hexadecimal (base 16), and other choices are binary (base 2), octal (base 8), and decimal (base 10).

• client - This is the network Internet Protocol (IP) address of the board. For network communications, the client IP is required to be set to a unique value, usually assigned by your local network administrator.

• server - This is the network IP address of the machine which contains files accessible via TFTP. Your local network administrator will have this information and can assist in properly configuring a TFTP server if one does not exist.

• gateway - This is the network IP address of the gateway for your local subnetwork. If the client IP address and server IP address are not on the same subnetwork, then this option must be properly set. Your local network administrator will have this information.

• netmask - This is the network address mask to determine if use of a gateway is required. This field must be properly set. Your local network administrator will have this information.

• filename - This is the default filename to be used for network download if no name is provided to the DN command.

• filetype - This is the default file type to be used for network download if no type is provided to the DN command. Valid values are: “srecord”, “coff”, and “elf”.

• mac - This is the ethernet Media Access Control (MAC) address (a.k.a hardware address) for the evaluation board. This should be set to a unique value, and the most significant nibble should always be even.

Examples:

To set the baud rate of the board to be 19200, the command is:

set baud 19200

NOTE:See the SHOW command for a display containing the correctformatting of these options.




Commands

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SHOW Show ConfigurationsUsage: SHOW <option>

The SHOW command displays the settings of the user-configurable options within dBUG.When no option is provided, SHOW displays all options and values.

Examples:

To display all options and settings, the command is:

show

To display the current baud rate of the board, the command is:

show baud

Here is an example of the output from a show command:

dBUG> show

base: 16

baud: 19200

server: 192.0.0.1

client: 192.0.0.2

gateway: 0.0.0.0

netmask: 255.255.255.0

filename: test.srec

filetype: S-Record

mac: 00:CF:54:07:C3:01




Commands

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STEP Step OverUsage: STEP

The STEP command can be used to “step over” a subroutine call, rather than tracing everyinstruction in the subroutine. The ST command sets a temporary breakpoint one instructionbeyond the current program counter and then executes the target code.

The STEP command can be used to “step over” BSR and JSR instructions.

The STEP command will work for other instructions as well, but note that if the STEPcommand is used with an instruction that will not return, i.e. BRA, then the temporarybreakpoint may never be encountered and dBUG may never regain control.

Examples:

To pass over a subroutine call, the command is:

step




Commands

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SYMBOL Symbol Name ManagementUsage: SYMBOL <symb> <-a symb value> <-r symb> <-c|l|s>

The SYMBOL command adds or removes symbol names from the symbol table. If only asymbol name is provided to the SYMBOL command, then the symbol table is searched fora match on the symbol name and its information displayed.

The -a option adds a symbol name and its value into the symbol table. The -r optionremoves a symbol name from the table.

The -c option clears the entire symbol table, the -l option lists the contents of the symboltable, and the -s option displays usage information for the symbol table.

Symbol names contained in the symbol table are truncated to 31 characters. Any symboltable lookups, either by the SYMBOL command or by the disassembler, will only use thefirst 31 characters. Symbol names are case-sensitive.

Symbols can also be added to the symbol table via in-line assembly labels and ethernetdownloads of ELF formatted files.

Examples:

To define the symbol “main” to have the value 0x00040000, the command is:

symbol -a main 40000

To remove the symbol “junk” from the table, the command is:

symbol -r junk

To see how full the symbol table is, the command is:

symbol -s

To display the symbol table, the command is:

symbol -l




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TRACE Trace IntoUsage: TRACE <num>

The TRACE command allows single-instruction execution. If num is provided, then numinstructions are executed before control is handed back to dBUG. The value for num is adecimal number.

The TRACE command sets bits in the processors’ supervisor registers to achievesingle-instruction execution, and the target code executed. Control returns to dBUG after asingle-instruction execution of the target code.

This command is repeatable.

Examples:

To trace one instruction at the program counter, the command is:

tr

To trace 20 instructions from the program counter, the command is:

tr 20




Commands

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UPDBUG Update dBUGUsage: updbug

The updbug command is used to update the dBUG image in Flash. When updates to theM5407C3 dBUG are available, the updated image is downloaded to address 0x00020000.The new image is placed into Flash using the UPDBUG command. The user is promptedfor verification before performing the operation. Use this command with extreme caution,as any error can render dBUG useless!




Commands

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UPUSER Update User FlashUsage: UPUSER <bytes>

The UPUSER command places user code and data into space allocated for the user in Flash.The optional parameter bytes specifies the number of bytes to copy into the user portion ofFlash.If the bytes parameter is omitted, then this command writes to the entire user space.There are seven sectors of 256K each available as user space. Users access this memorystarting at address 0xFFE40000.

Examples:

To program all 7 sectors of user Flash, the command is:

upuser

To program only 1000 bytes into user Flash, the command is:

upuser 1000




Commands

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VERSION Display dBUG VersionUsage: VERSION

The VERSION command displays the version information for dBUG. The dBUG version,build number and build date are all given.

The version number is separated by a decimal, for example, “v 2b.1c.1a”.

The version date is the day and time at which the entire dBUG monitor was compiled andbuilt.

Examples:

To display the version of the dBUG monitor, the command is:

version

In this example, v 2b . 1c . 1a{ { {

dBUG commonmajor and minor revision

CPU major and minor revision

board majorand minor revision




TRAP #15 Functions

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2.5 TRAP #15 FunctionsAn additional utility within the dBUG firmware is a function called the TRAP 15 handler.This function can be called by the user program to utilize various routines within the dBUG,to perform a special task, and to return control to the dBUG. This section describes theTRAP 15 handler and how it is used.

There are four TRAP #15 functions. These are: OUT_CHAR, IN_CHAR,CHAR_PRESENT, and EXIT_TO_dBUG.

2.5.1 OUT_CHAR

This function ( function code 0x0013) sends a character, which is in lower 8 bits of D1, toterminal.

Assembly example:

/* assume d1 contains the character */

move.l #$0013,d0 Selects the function

TRAP #15 The character in d1 is sent to terminal

C example:void board_out_char (int ch){

/* If your C compiler produces a LINK/UNLK pair for this routine, * then use the following code which takes this into account*/

#if l/* LINK a6,#0 -- produced by C compiler */asm (“ move.l8(a6),d1”); /* put ‘ch’into d1 */asm (“ move.l#0x0013,d0”); /* select the function */asm (“ trap#15”); /* make the call *//* UNLK a6 -- produced by C compiler */

#else/* If C compiler does not produce a LINK/UNLK pair, the use * the following code.*/ asm (“ move.l4(sp),d1”); /* put ‘ch’into d1 */asm (“ move.l#0x0013,d0”); /* select the function */asm (“ trap#15”); /* make the call */

#endif}

2.5.2 IN_CHAR

This function (function code 0x0010) returns an input character (from terminal) to thecaller. The returned character is in D1.




TRAP #15 Functions

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Assembly example:

move.l #$0010,d0 Select the function

trap #15 Make the call, the input character is in d1.

C example:

int board_in_char (void)

{

asm (“ move.l#0x0010,d0”); /* select the function */

asm (“ trap#15”); /* make the call */

asm (“ move.ld1,d0”); /* put the character in d0 */

}

2.5.3 CHAR_PRESENT

This function (function code 0x0014) checks if an input character is present to receive. Avalue of zero is returned in D0 when no character is present. A non-zero value in D0 meansa character is present.

Assembly example:


trap #15 Make the call, d0 contains the response (yes/no).

C example:

int board_char_present (void)

{


asm (“ trap#15”); /* make the call */

}

2.5.4 EXIT_TO_dBUG

This function (function code 0x0000) transfers the control back to the dBUG, byterminating the user code. The register context are preserved.

Assembly example:


trap #15 Make the call, exit to dBUG.

C example:

void board_exit_to_dbug (void)

{





TRAP #15 Functions

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asm (“ trap#15”); /* exit and transfer to dBUG */

}




TRAP #15 Functions

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Chapter 3 Hardware Description and ReconfigurationThis chapter provides a functional description of the M5407C3 board hardware. With thedescription given here and the schematic diagram in Appendix E, the user can gain a goodunderstanding of the board's design. In this manual, an active low signal is indicated by a"-" preceding the signal name in this text and a bar over the signal name in the schematics.

3.1 The Processor and Support LogicThis part of the Chapter discusses the CPU and general supporting logic on the M5407C3board.

3.1.1 Processor

The microprocessor used in the M5407C3 is the highly integrated Motorola ColdFire® MCF5407,32-bit processor. The MCF5407 implements a ColdFire version 4 core with 16 KByte instructioncache and 8 KByte of data cache, two UART channels, two Timers, 4 KBytes of SRAM, MotorolaM-Bus Module supporting the I2C, two-byte wide parallel I/O port, and the supporting integratedsystem logic. All the registers of the core processor are 32 bits wide except for the Status Register(SR) which is 16 bits wide. This processor communicates with external devices over a 32-bit widedata bus, D0-D31 with support for 8 and 16-bit ports. This chip can address 4 GBytes of memoryspace using internal chip-select logic. All the processor's signals are available through theexpansion connectors (J1 and J2). Refer to section 3.6 for pin assignment.

The MCF5407 has an IEEE JTAG-compatible port and BDM port used with third partytools. The board is configured to boot up in the normal/BDM mode of operation. Thesesignals are available at port J5. The processor also has the logic to generate up to eight (8)chip selects, -CS0 to -CS7, and support for 2 banks of ADRAM (not on evaluation board)or 2 banks of SDRAM (on evaluation board).

3.1.2 Reset Logic

The reset logic provides system initialization. The reset occurs during power-on or theassertion of the signal -RSTI which causes total system reset. The reset is also triggered bythe reset switch (S1) and resets the entire processor.

Chapter 3. Hardware Description and Reconfiguration 3-1



The Processor and Support Logic

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U19 is used to produce active low power-on RESET signal which feeds into theispLSI2032. The reset switch is fed into U19 which generates U18's input for reset. TheU18 device generates the system reset (-CF_RSTI) and Ethernet RESET (ETH_RST)signals.

dBUG performs the following configurations of internal resources during the initialization.The instruction cache is invalidated and disabled. The Vector Base Register, VBR, pointsto the Flash. A copy of the exception table is made at address $00000000 in the SDRAM.

The Software Watchdog Timer is disabled, Bus Monitor enabled, and internal timers areplaced in a stop condition. Interrupt controller registers are initialized with unique interruptlevel/priority pairs. PP[7:0] are configured as paralell port output pins and PP[15:8] areconfigured as A[31:24]. PP[7:4] are general purpose outputs and PP[3:0] are used by theROM monitor to automaticaly configure the SDRAM address lines via the U27 mux.

3.1.3 HIZ Signal

The assertion of the -HIZ signal forces all output drivers to a high-impedance state. The-HIZ signal is actively driven by the ispLSI2032V-100LJ (U18). -HIZ is only driven low(asserted) during reset. This Signal is available on the 120 pin expansion connector J1. Thissignal should not be driven by the user.

3.1.4 Clock Circuitry

The M5407C3 uses a 50MHZ oscillator (U21) to provide the clock to CLKIN pin of theprocessor. In addition to U21, there also exist a 20MHz oscillator (U10) which feeds intothe Ethernet chip, a PCI bus master 33MHZ oscillator (U30) and a 32.768 KHZ crystal(Y1) for the real-time clock. The CLKIN drives the clock buffer chip (U24). The bufferedCLKIN drives the 5407 and the ispLSI2032 for Ethernet timing (1/6 bus clock), SRAM(U13), and SDRAM (U26).

3.1.5 Watchdog Timer

The duration of the Watchdog is selected by BMT0-1 bits in System Protection Register.The dBUG initializes this register with the value 00, which provides for 1024 system clocktime-out but dBUG does NOT enable it.

3.1.6 Interrupt Sources

The ColdFire® family of processors can receive interrupts for seven levels of interruptpriorities. When the processor receives an interrupt which has higher priority than thecurrent interrupt mask (in status register), it will perform an interrupt acknowledge cycle atthe end of the current instruction cycle. This interrupt acknowledge cycle indicates to thesource of the interrupt that the request is being acknowledged and the device should providethe proper vector number to indicate where the service routine for this interrupt level is





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located. If the source of interrupt is not capable of providing a vector, its interrupt shouldbe set up as autovector interrupt which directs the processor to a predefined entry into theexception table (refer to the MCF5407 User's Manual).

The processor goes to an exception routine via the exception table. This table is in the Flashand the VBR points to it. However, a copy of this table is made in the RAM starting at$00000000. To set an exception vector, the user places the address of the exception handlerin the appropriate vector in the vector table located at $00000000, and then points the VBRto $00000000.

The MCF5407 has four external interrupt request lines. You can program the externalinterrupt request pins to level 1, 3, 5, and 7 or levels 2, 4, 6, and 7. The M5407C3 configuresthese lines as level 1, 3, 5, and 7. There are also six internal interrupt requests from Timer0,Timer1, Software watchdog timer, UART0, UART1, and MBUS. Each interrupt source,external and internal, can be programmed for any priority level. In case of similar prioritylevel, a second relative priority between 0 to 3 will be assigned.

However, the software watchdog is programmed for Level 7, priority 2 and uninitializedvector. The UART0 is programmed for Level 3, priority 2 and autovector. The UART1 isprogrammed for Level 3, priority 1 and autovector. The M-Bus is at Level 3, priority 0 andautovector. The Timers are at Level 5 with Timer0 with priority 3 and Timer1 with priority2 and both for autovector.

NOTE:No interrupt sources should have the same level and priority asanother. Programming two interrupt sources with the samelevel and priority can result in undefined operation.

The M5407C3 uses -IRQ7 to support the ABORT function using the ABORT switch S2.This switch is used to force a non-maskable interrupt (level 7, priority 3) if the user'sprogram execution should be aborted without issuing a RESET (refer to Chapter 2 for moreinformation on ABORT). Since the ABORT switch is not capable of generating a vector inresponse to level seven interrupt acknowledge from the processor, the debugger programsthis request for autovector mode.

The -IRQ1 line of the MCF5407 is connected to the PCI connector J3 pin A6 signal INTA#.

The -IRQ5 line of the MCF5407 is connected to the PCI controller (U17) pin 12 signal-IRQ_OUT.

Refer to MCF5407 User’s Manual for more information about the interrupt controller.

3.1.7 Internal SRAM

The MCF5407 has 4KBtyes of internal memory configured as two 2 KByte blocks(RAMBAR0 and RAMBAR1) which may independently be programmed as data orinstruction memory. This memory is mapped to 0x20000000 and 0x20000800 respectively,





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configured as data space but is not used by dBUG except during system initialization. Aftersystem initialization is complete it is available to the user. The memory is relocatable toany 2 KByte boundary.

If one or both of the internal SRAMs will be used to store instructions, then the RAMBARshould initially be set up for data. While the SRAM is programmed as data the code can beloaded into the SRAM. After the code has been moved reprogram the RAMBAR so that theSRAM is defined as instruction. Now the code stored in the SRAM can execute.

3.1.8 The MCF5407 Registers and Memory Map

The memory and I/O resources of the M5407C3 are divided into three groups, MCF5407Internal, External resources, and the ethernet controller. All the I/O registers are memorymapped.

The MCF5407 has built in logic and up to eight chip-select pins (-CS0 to -CS7) which areused to enable external memory and I/O devices. In addition there are two -RAS lines forDRAM’s. There are registers to specify the address range, type of access, and the methodof -TA generation for each chip-select and -RAS pins. These registers are programmed bydBUG to map the external memory and I/O devices.

The M5407C3 uses chip-select zero (-CS0) to enable the Flash ROM (refer to Section 3.3.)The M5407C3 uses -RAS1, -RAS2, -CAS0, -CAS1, -CAS2, and -CAS3 to enable theSDRAM DIMM module (refer to Section 3.2), -CS2 for SRAM (not populated), -CS3 forEthernet Bus I/O space, and -CS1 for the PCI bridge chip.

The chip select mechanism of the MCF5407 allows the memory mapping to be definedbased on the memory space desired (User/Supervisor, Program/Data spaces).

All the MCF5407 internal registers, configuration registers, parallel I/O port registers,UART registers and system control registers are mapped by MBAR register at any 1 KByteboundary. It is mapped to 0x10000000 by dBUG. For complete map of these registers referto the MCF5407 User's Manual.

The M5407C3 board can have up to 512 MBytes of SDRAM installed. The first 16 MBytesof memory space are reserved for this memory. Refer to Section 3.2 for a discussion ofRAM. The dBUG is programmed in one Am29PL160C-XX Flash ROM which occupies 2MBytes of the address space. The first 256 KBytes are used by ROM Monitor and theremainder is left for user use. Refer to section 3.3.

dBUG maps all the I/O space of the Ethernet bus to the MCF5407 memory at address$40000000. Refer to section 3.6





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Table 3-1 shows the M5407C3 memory maps.

All the unused area of the memory map is available to the user.

3.1.9 Reset Vector Mapping

After reset, the processor attempts to get the initial stack pointer and initial program countervalues from locations $000000-$000007 (the first eight bytes of memory space). Thisrequires the board to have a nonvolatile memory device in this range with properinformation. However, in some systems, it is preferred to have RAM starting at address$00000000. In MCF5407, the -CS0 responds to any accesses after reset until the CSMR0is written. Since -CS0 (the global chip select) is connected to Flash ROM, the Flash ROMappears at address $00000000 which provides the initial stack pointer and program counter(the first 8 bytes of the Flash ROM). The initialization routine programs the chip-selectlogic, locates the Flash ROM to start at $7FE00000 and the configures the rest of theinternal and external peripherals.

3.1.10 TA Generation

The processor starts a bus cycle by asserting -TS with other control signals. The processorthen waits for an acknowledgment (-TA) either from within (Auto acknowledge mode) orby the externally addressed device before it can complete the bus cycle. -TA is used not onlyto indicate the completion of the bus cycle, it also allows devices with different access timesto communicate with the processor properly (i.e. asynchronously). The MCF5407, as partof the chip-select logic, has a built in mechanism to generate -TA for all external deviceswhich do not have the capability to generate -TA on their own. The Flash ROM and SRAMcan not generate -TA. The chip-select logic is programmed by the ROM Monitor to

Table 3-1. The M5407C3 Memory Map

Address Range Signal and Device Memory Access Time

$00000000-$00020000 SDRAM space for dBug ROM monitor use refer to manufacturer spec

$00020000-$00FFFFFF SDRAM space refer to manufacturer spec

$10000000-$100003FF System Integration Module (SIM) registers internal access

$20000000-$200007FF SRAM0 internal access (1 clock)

$20000800-$20000FFF SRAM1 internal access (1 clock)

$30000000-$300003FF1

1 Not installed. SRAM footprint accepts Motorola’s MCM69F737TQ chip and any other SRAM with the same electrical specifications and package.

-CS2, External SRAM 2-1-1-1

$40000000-$400FFFFF -CS3, 1M Ethernet Bus Area external TA from PLD (U18)

$7FE00000-$7FFFFFFF -CS0, 2M Flash ROM 8-7-7-7

$FFFF0000-$FFFFFFFF -CS1, PCI Bridge Chip external TA from PCI (U17)





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generate -TA internally after a preprogrammed number of wait states. In order to supportfuture expansion of the board, the -TA input of the processor is also connected to theProcessor Expansion Bus, J2. This allows the expansion boards to assert this line toindicate their -TA to the processor. On the expansion boards, however, this signal shouldbe generated through an open collector buffer with no pull-up resistor; a pull-up resistor isincluded on the board. All the -TA’s from the expansion boards should be connected to thisline.

3.1.11 Wait State Generator

The Flash ROM and SDRAM DIMM on the board may require some adjustments on thecycle time of the processor to make them compatible with processor speed. To extend theCPU bus cycles for the slower devices, the chip-select logic of the MCF5407 can beprogrammed to generate an internal -TA after a given number of wait states. Refer toSections 3.1.12 and 3.1.13 for information about the wait state requirements of SDRAMand Flash ROM respectively.

3.1.12 SDRAM DIMM

The M5407C3 has one 168-pin DIMM socket (U26) for a SDRAM DIMM. The M5407C3will work with most PC100 SDRAM DIMMs with a few exceptions. The 5407 supports upto two banks of SDRAM, but double-sided DIMMs require 4 bank selects to access all ofthe chips. Therefore when using double-sided DIMMs only half of the available memorywill be accessible. Since DIMMs are manufactured primarily for use in PCs some DIMMshave the DQM (byte enables) and RAS (bank selects) routed so that the DIMM cannot beaccessed as a 32-bit port.

In order to support SDRAM DIMMs with different configurations the M5407C3 uses ahelper mux (U27) to configure the address line connections to the DIMM socket. See theConnecting the MCF5307 to 168-Pin Unbuffered SDRAM DIMMs application note on thecoldfire website (www.motorola.com/coldfire) for more information. JP21-JP24 are usedto configure the inputs to the helper mux. When dBUG comes up it will read the SDRAMconfiguration information from the EEPROM on the DIMM and drive the properconfiguration data for the helper mux on PP[0:3].

If you are using a third party debugger or want to use PP[0:3] then the jumpers JP21-JP24should be moved to the correct settings for the particular DIMM you are using. There are acouple of ways to determine which settings should be used. First, the jumper settings fordifferent combinations of row and column addresses are listed in the jumper tablesilkscreen on the back of the board. The settings can also be determined by allowing theboard to boot up under dBUG control. Since dBUG drives the configuration data on PP[0:3]the data will be seen on the LEDs (D1-D4). If the LED is on then the corresponding jumpershould be OFF, and if the LED is off then the jumper should be in position 2-3.




Serial Communication Channels

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3.1.13 Flash ROM

There is one 2 MByte Flash ROM on the M5407C3, U12.

The board is shipped with one Am29PL160C, 2 MByte Flash ROM. The first 256K of theFlash contains ROM Monitor firmware. The remaining memory is available to the user.

The MCF5407 chip-select logic can be programmed to generate the -TA for -CS0 signalafter a certain number of wait states (i.e. auto acknowledge mode). dBUG programs thisparameter to six wait-states.

3.1.14 JP15 Jumper and User’s Program

This jumper allows users to test code from the boot without having to overwrite the ROMMonitor.

When the jumper is set between pins 1 and 2, the behavior is normal. When the jumper isset between pins 2 and 3, the board boots from the second half of Flash (0x7FF00000).

Procedure:

1. Compile and link as though the code was to be placed at the base of the flash, but setup so that it will download to the SDRAM starting at address 0xE0000. The user should refer to the compiler for this, since it will depend upon the compiler used.

2. Set up the jumper (JP15) for Normal operation, pin1 connected to pin 2.

3. Download to SDRAM (If using serial or ethernet, start ROM Monitor first. If using BDM via wiggler, download first, then start ROM Monitor by pointing PC to 0x7fe00400 and run.)

4. In ROM Monitor, run 'upuser' command.

5. Move jumper (JP15) to pin 2 connected to pin 3 and push the reset button (S1). User code should be running.

3.2 Serial Communication ChannelsThe M5407C3 offers a number of serial communications. They are discussed in thissection.

3.2.1 MCF5407 UARTs

The MCF5407 has two built in UARTs, each with its own software programmable baud rategenerators; one channel is the ROM Monitor to Terminal output and the other is availableto the user. The ROM Monitor programs the interrupt level for UART0 to Level 3, priority2 and autovector mode of operation. The interrupt level for UART1 is programmed toLevel 3, priority 1 and autovector mode of operation. The signals of these channels areavailable on expansion connector J2. The signals of UART0 and UART1 are also passed




Real-Time Clock

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through the RS-232 driver/receiver and are available on DB-9 connectors P4 and P5. Referto the MCF5407 User’s Manual for programming and the register map.

3.2.2 I2C Module

The MCF5407 has a built in I2C module which allows interchip bus interface for a number of I/Odevices. It is compatible with industry-standard I2C Bus. The M5407C3 uses this to access theSDRAM eeprom parameters. The two I2C signals are SDA and SCL which are available on the J2expansion connector and J6 (this connector is unpopulated, see BOM in Appendix XXX for partnumber). These signals are open-collector signals. However, they have pull-up resistors on theM5407C3. These signals are connected to the SDRAM DIMM module I2C interface but not usedby the debugger. The interrupt control register for I2C is set for Level 3, priority 0 and autovector.Please note the MCF5407 I2C module is only 3.3V tolerant. Level shifters should be used if 5Vdevices are being interfaced to the MCF5407 I2C.

3.3 Real-Time ClockThe M41T11M is a real-time clock incorporating 64 bytes of low power static RAM and abuilt-in 32.768KHz oscillator, driven from an external crystal. The first 8 bytes of RAM areused to provide the clock/calendar storage, which are configured in BCD format. Theremaining 56 bytes of RAM is available for use as battery backed storage - if the batterysite on the M5407C3 is populated. Addresses and data are transferred via the I2C

bus to the M41T11M within which an address register is incremented after each read orwrite of data. The device is year 2000 compliant and has automatic leap year compensation.There are counters within the device for seconds, minutes, hours, day, date, month, year andcentury.

3.4 Parallel I/O PortThe MCF5407 has one 16-bit parallel port. All the pins have dual functions. They can beconfigured as I/O or their alternate function via the Pin Assignment register. dBug programsthe parllel port pins as follows:

P[3:0] connects to the SDRAM mux control and LEDs.P[7:4] connects to LEDs and are available to the user during dBUG.P[15:8] are configured as A[31:24].

3.5 On-Board Ethernet LogicThe M5407C3 includes the necessary logic, drivers, and the NE2000 compatible Ethernetchip to allow 10M bit transfer rate on a network. The Ethernet-space addresses are locatedstarting at 0x40000000.

The interface base address is 0x300 and uses IRQ3. However, the Ethernet base address in




On-Board Ethernet Logic

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our system as mentioned earlier is 0x40000000. Which brings the address of chip to0x40000300. Note that all registers should be addressed as WORD accesses (even thoughthe registers are bytes). Note that the even address registers are addressed as they are (nochange), the read word will have the byte of the data in the lower byte of the word.

For odd addressed bytes, the address is mapped to 0x400083xx-1. Note that odd-bytes areaddressed as even addresses but increased by 0x8000. Still the read byte will be in thelower byte of the read word

Below is an example of the data structure used to define the registers. For more informationon the Davicom DM9008 visit the Davicom website (www.davicom8.com).

typedef struct{

NATURAL16CR;union{

struct{

/* Even registers */NATURAL16 CLDA1;/* CLDA1 (rd) PSTOP (wr) */NATURAL16 TSR; /* TSR (rd) TPSR (wr) */NATURAL16 FIFO; /* FIFO (rd) TBCR1 (wr) */NATURAL16 CRDA0;/* CRDA0 (rd) RSAR0 (wr) */NATURAL16 RBCR0;/* Remote Byte Count 0 (wr) */NATURAL16 RSR; /* RSR (rd) RCR (wr) */NATURAL16 CNTR1;/* CNTR1 (rd) DCR (wr) */

NATURAL16 DATAPORT;

NATURAL16 reserved[(0x10000-0x0012)/2];

/* Odd registers */NATURAL16 CLDA0;/* CLDA0 (rd) PSTART (wr) */NATURAL16 BNRY; /* Boundary pointer (rd wr) */NATURAL16 NCR; /* NCR (rd) TBCR0 (wr) */NATURAL16 ISR; /* Interrupt Status Register (rd wr) */NATURAL16 CRDA1;/* CRDA1 (rd) RSAR1 (wr) */NATURAL16 RBCR1;/* Remote Byte Count 1 (wr) */NATURAL16 CNTR0;/* CNTR0 (rd) TCR (wr) */NATURAL16 CNTR2;/* CNTR2 (rd) IMR (wr) */

} page0;struct{

/* Even registers */NATURAL16 PAR1; /* Physical Address Byte 1 */NATURAL16 PAR3; /* Physical Address Byte 3 */NATURAL16 PAR5; /* Physical Address Byte 5 */NATURAL16 MAR0; /* Multicast Address Byte 0 */NATURAL16 MAR2; /* Multicast Address Byte 2 */




On-Board Ethernet Logic

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NATURAL16 MAR4; /* Multicast Address Byte 4 */NATURAL16 MAR6; /* Multicast Address Byte 6 */


/* Odd registers */NATURAL16 PAR0; /* Physical Address Byte 0 */NATURAL16 PAR2; /* Physical Address Byte 2 */NATURAL16 PAR4; /* Physical Address Byte 4 */NATURAL16 CURR; /* Current Page Register (rd wr) */NATURAL16 MAR1; /* Multicast Address Byte 1 */NATURAL16 MAR3; /* Multicast Address Byte 3 */NATURAL16 MAR5; /* Multicast Address Byte 5 */NATURAL16 MAR7; /* Multicast Address Byte 7 */

} page1;struct{

/* Even registers */NATURAL16 PSTOP;/* PSTOP (rd) CLDA1 (wr) */NATURAL16 TPSR; /* Transmit Page Start Address (rd) */NATURAL16 ACU; /* Address Counter Upper */NATURAL16 reserved0;NATURAL16 reserved2;NATURAL16 RCR; /* Receive Configuration Register (rd) */NATURAL16 DCR; /* Data Configuration Register (rd) */


/* Odd registers */NATURAL16 PSTART;/* PSTART (rd) CLDA0 (wr) */NATURAL16 RNPP; /* Remote Next Packet Pointer */NATURAL16 LNPP; /* Local Next Packet Pointer */NATURAL16 ACL; /* Address Counter Lower */NATURAL16 reserved1;NATURAL16 reserved3;NATURAL16 TCR; /* Transmit Configuration Register (rd) */NATURAL16 IMR; /* Interrupt Mask Register (rd) */

} page2;} regs;

} NS8390;

The main purpose for this setup is to allow the use of Ethernet card (NE2000 compatible)to facilitate network download, refer to chapter 2 for network download command (DN).The dBUG driver is 100% NE2000 compatible.

The Ethernet Bus interrupt request line is connected via the 2032V PLD to IRQ3.

The on board ROM MONITOR is programmed to allow a user to download files from anetwork to memory in different formats. The current compiler formats supported areS-Record, COFF, ELF, or Image.




Connectors and Expansion Bus

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3.6 Connectors and Expansion BusThere are 2 expansion connectors on the M5407C3 (J1 and J2) which are used to connectthe board to external I/O devices and/or expansion boards.

3.6.1 Expansion Connectors - J1 and J2

Table 3-2 shows pin assignments for the J1 connector.

Table 3-2. J1 Connector Pin Assignment

Pin Signal Pin Signal Pin Signal Pin Signal

1 1.8V 2 1.8V 61 D20 62 A15

3 1.8V 4 GND 63 D21 64 A16

5 D0 6 -HIZ 65 D22 66 GND

7 D1 8 -BKPT_TMS 67 GND 68 A17

9 GND 10 DSDI_TDI 69 D23 70 A18

11 D2 12 1.8V 71 D24 72 A19

13 D3 14 DSDO_TDO 73 D25 74 3.3V

15 3.3V 16 TCK 75 3.3V 76 A20

17 D4 18 DSCLK_TRST 77 D26 78 A21

19 D5 20 GND 79 D27 80 A22

21 GND 22 A0 81 D28 82 GND

23 D6 24 A1 83 GND 84 A23

25 D7 26 3.3V 85 D29 86 A24

27 3.3.V 28 A2 87 D30 88 A25

29 D8 30 A3 89 D31 90 3.3V

31 D9 32 A4 91 3.3V 92 A26

33 D10 34 GND 93 SIZ0 94 A27

35 GND 36 A5 95 SIZ1 96 A28

37 D11 38 A6 97 GND 98 GND

39 D12 40 A7 99 -OE 100 A29

41 D13 42 3.3V 101 -CS0 102 A30

43 3.3V 44 A8 103 -CS1 104 A31

45 D14 46 A9 105 3.3V 106 1.8V

47 D15 48 A10 107 GND 108 GND

49 D16 50 GND 109 GND 110 GND





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Table 3-3 shows the pin assignments of the J2 connector.

51 GND 52 A11 111 1.8V 112 1.8V

53 D17 54 A12 113 5V 114 5V

55 D18 56 A13 115 5V 116 5V

57 D19 58 3.3V 117 GND 118 GND

59 3.3V 60 A14 119 GND 120 GND

Table 3-3. J2 Connector pin assignment


1 1.8V 2 1.8V 61 TIN1 62 GND

5 -CS2 6 PP0 63 -R_RAS0/SO0 64 GND

3 GND 4 GND 65 -R_RAS1/S02 66 MTMOD1

7 -CS3 8 PP1 67 GND 68 MTMOD0

9 -CS4 10 3.3V 69 -R_CAS0/DQM0

70 1.8V

11 1.8V 12 PP2 71 -R_CAS1/DQM1

72 CLKIN

13 -CS5 14 PP3 73 -R_CAS2/DQM2

74 GND

15 -CS6 16 PP4 75 3.3V 76 -RSTO

17 -CS7 18 GND 77 -R_CAS3/DQM3

78 1.8V

19 GND 20 PP5 79 -RDRAMW 80 BCLKO

21 -AS 22 PP6 81 -R_SRAS 82 GND

23 R/-W 24 PP7 83 GND 84 EDGESEL

25 -TA 26 1.8V 85 -R_SCAS 86 3.3V

27 3.3V 28 PSTDDATA7 87 R_SCKE 88 TXD0

29 -TS 30 PSTDDATA6 89 -BWE0 90 RXD0

31 -CF_RSTI* 32 GND 91 3.3V 92 -RTS0

33 -IRQ7 34 PSTDDATA5 93 -BWE1 94 -CTS0

35 GND 36 PSTDDATA4 95 -BWE2 96 GND

37 -IRQ5 38 3.3V 97 -BWE3 98 TXD1

39 -IRQ3 40 PSTDDATA3 99 GND 100 RXD1

Table 3-2. J1 Connector Pin Assignment (Continued)






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* -CFRSTI and -CS_FPCIBD are board specific control signals, NOT processor signals. See the schematics and PLD equations in the appendix.

3.6.2 The Debug Connector J5

The MCF5407 does have background Debug Port, Real-Time Trace Support, andReal-Time Debug Support. The necessary signals are available at connector J5. Figure 3-1shows the J5 Connector pin assignment shows the pin assignment.

41 -IRQ1 42 PSTDDATA2 101 SCL 102 -RTS1

43 1.8V 44 GND 103 SDA 104 -CTS1

45 -BR 46 PSTDDATA1 105 GND 106 1.8V

47 -BD 48 PSTDDATA0 107 1.8V 108 1.8V

49 -BG 50 1.8V 109 3.3V 110 3.3V

51 GND 52 PSTCLK 111 -A31 112 -CS_FPCIBD*

53 TOUT1 54 GND 113 5V 114 5V

55 TOUT0 56 MTMOD3 115 5V 116 5V

57 TIN0 58 MTMOD2 117 GND 118 GND

59 3.3V 60 1.8V 119 GND 120 GND

Table 3-3. J2 Connector pin assignment (Continued)






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Figure 3-1. The J5 Connector pin assignment

1

35

7

9

11

13

15

17

19

21

23

25

2

46

8

10

12

14

16

18

20

22

24

26

-BKPT

DSCLK

DEVELOPER RESERVED

DSI

DSO

PSTDDATA7

PSTDDATA5

PSTDDATA3

PSTDDATA1

GND

MOTOROLA RESERVED

PST_CLK

-TA

GND

GND

-RST_IN

GND

PSTDDATA6

PSTDDATA4

PSTDDATA2

PSTDDATA0

MOTOROLA RESERVED

GND

CORE VOLTAGE

DEVELOPER RESERVED

I/O PAD VOLTAGE




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Appendix AConfiguring dBUG for Network DownloadsThe dBUG module has the ability to perform downloads over an Ethernet network usingthe Trivial File Transfer Protocol, TFTP. Prior to using this feature, several parameters arerequired for network downloads to occur. The information that is required and the steps forconfiguring dBUG are described below.

A.1 Required Network ParametersFor performing network downloads, dBUG needs 6 parameters; 4 are network-related, and2 are download-related. The parameters are listed below, with the dBUG designationfollowing in parenthesis.

All computers connected to an Ethernet network running the IP protocol need 3network-specific parameters. These parameters are:

Internet Protocol, IP, address for the computer (client IP),IP address of the Gateway for non-local traffic (gateway IP), andNetwork netmask for flagging traffic as local or non-local (netmask).

In addition, the dBUG network download command requires the following threeparameters:

IP address of the TFTP server (server IP),Name of the file to download (filename),Type of the file to download (filetype of S-record, COFF, ELF, or Image).

Your local system administrator can assign a unique IP address for the board, and alsoprovide you the IP addresses of the gateway, netmask, and TFTP server. Fill out the linesbelow with this information.

Client IP:___.___.___.___(IP address of the board)Server IP:___.___.___.___(IP address of the TFTP server)Gateway:___.___.___.___(IP address of the gateway)Netmask:___.___.___.___(Network netmask)

Appendix A. Configuring dBUG for Network Downloads A-1



Configuring dBUG Network Parameters

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A.2 Configuring dBUG Network ParametersOnce the network parameters have been obtained, the Rom Monitor must be configured.The following commands are used to configure the network parameters.

set client <client IP>set server <server IP>set gateway <gateway IP>set netmask <netmask>set mac <addr>

For example, the TFTP server is named ‘santafe’ and has IP address 123.45.67.1. Theboard is assigned the IP address of 123.45.68.15. The gateway IP address is 123.45.68.250,and the netmask is 255.255.255.0. The commands to dBUG are:

set client 123.45.68.15set server 123.45.67.1set gateway 123.45.68.250set netmask 255.255.255.0set mac 00:CF:54:07:03:01

The last step is to inform dBUG of the name and type of the file to download. Prior togiving the name of the file, keep in mind the following.

Most, if not all, TFTP servers will only permit access to files starting at a particularsub-directory. (This is a security feature which prevents reading of arbitrary files byunknown persons.) For example, SunOS uses the directory /tftp_boot as the default TFTPdirectory. When specifying a filename to a SunOS TFTP server, all filenames are relativeto /tftp_boot. As a result, you normally will be required to copy the file to download intothe directory used by the TFTP server.

A default filename for network downloads is maintained by dBUG. To change the defaultfilename, use the command:

set filename <filename>

When using the Ethernet network for download, either S-record, COFF, ELF, or Image filesmay be downloaded. A default filetype for network downloads is maintained by dBUG aswell. To change the default filetype, use the command:

set filetype <srecord|coff|elf|image>

Continuing with the above example, the compiler produces an executable COFF file,‘a.out’. This file is copied to the /tftp_boot directory on the server with the command:

rcp a.out santafe:/tftp_boot/a.out

Change the default filename and filetype with the commands:

set filename a.out

A-2 M5407C3 User’s Manual



Troubleshooting Network Problems

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set filetype coff

Finally, perform the network download with the ‘dn’ command. The network downloadprocess uses the configured IP addresses and the default filename and filetype for initiatinga TFTP download from the TFTP server.

A.3 Troubleshooting Network ProblemsMost problems related to network downloads are a direct result of improper configuration.Verify that all IP addresses configured into dBUG are correct. This is accomplished via the‘show ’command.

Using an IP address already assigned to another machine will cause dBUG networkdownload to fail, and probably other severe network problems. Make certain the client IPaddress is unique for the board.

Check for proper insertion or connection of the network cable. IS status LED lit indicatingthat network traffic is present?

Check for proper configuration and operation of the TFTP server. Most Unix workstationscan execute a command named ‘tftp’ which can be used to connect to the TFTP server aswell. Is the default TFTP root directory present and readable?

If ‘ICMP_DESTINATION_UNREACHABLE’ or similar ICMP message appears, then aserious error has occurred. Reset the board, and wait one minute for the TFTP server totime out and terminate any open connections. Verify that the IP addresses for the server andgateway are correct.

Appendix A. Configuring dBUG for Network Downloads A-3



Troubleshooting Network Problems

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A-4 M5407C3 User’s Manual



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Appendix BColdFire to ISA, IRQ7 and Reset Logic Abel Codemodule isa2

title 'isa controller'

"June 18 '00 version v4 of the 5407

"isa2 device 'ispLSI';

;"*****************************************************"

;"This abel file contains the code for a NE2000 compatible ethernet"

;"for the 5407 Coldfire processor as well as reset"

;"It was targeted to Lattice ispLSI LV 2032 PLD "

;"CS: B25D "

;"*****************************************************"

;"*****************************************************"

;"Declaration Section "

;"*****************************************************"

;" constants"

C,P,X,Z,H,L = .C.,.P.,.X.,.Z.,1,0;

;"*****************************************************"

DLYIOCHRDY0 node ISTYPE 'reg_d,buffer';

DLYIOCHRDY,ENDIT,END16,END8 node;

STARTISA node ISTYPE 'reg_d,buffer';

SBHE,IOR,IOW,ISAOE node;

DA,DLYDA node ISTYPE 'reg_d,buffer';

DAOE,CLK16MHZ node ISTYPE 'reg_d,buffer';

CLK8MHZ node ISTYPE 'reg_d,buffer';

CLK4MHZ node ISTYPE 'reg_d,buffer';

RSTMH node;

Appendix B. ColdFire to ISA, IRQ7 and Reset Logic Abel Code B-1



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BCLK0 node ISTYPE 'reg_d,buffer';



DIV6Q0 node ISTYPE 'reg_d,buffer';

DIV6Q1 node ISTYPE 'reg_d,buffer';

GNTANC_L pin 3; "Output - to Anchor 3042 to grant PCI bus

RST_L pin 4; "Output - to ColdFire reset

DB_CS_L pin 5; "Output - Data buffer enable for ethernet

A0IN pin 6; "INPUT - A0 received from CF through buffers

IOCHRDY pin 7; "Input - asserted by ethernet

CS0_L pin 8; "Input - Chip select 0 from ColdFire

IOCS16L pin 9; "Input - asserted by ethernet

SIZ1 pin 10;

XCLK0 pin 11; "Input - global clock currently 50MHz

IOWL pin 15; "Input - write signal from ethernet

RD pin 16; "INPUT - R/W* from the ColdFire

DIV6Q2 pin 17 ISTYPE 'reg_d,buffer';

BALE pin 18; "Output - address latch enable

A0 pin 19; "OUTPUT - A0 sent to the ethernet



CS3_L pin 22; "Input - From ColdFire

CS_FPCIBD_L pin 25; "Output - Chip selects 0,1 & 2 or'd fordata buffers

PORIN_L pin 26; "Input - Suppy Voltage Supervisor

GNTPCI_L pin 27; "Output - Grant signal to the PCI connector

ETHER_IRQ pin 28; "Input - Ethernet IRQ 3

IRQ3 pin 29; "Output - IRQ 3 into the ColdFire

RST_H pin 30; "Output - to the Ethernet

REQPCI_L pin 31; "Input - request from the PCI connector

HIZ_L pin 32; "Output - to ColdFire *HIZ

IORL pin 37; "Input - read signal from ethernet

A31 pin 38; "Input - A31 signal for CS to PCI controller

A16 pin 39;

TAL pin 40; "Input / Output - Transfer acknowledge

B-2 M5407C3 User’s Manual



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REQANC_L pin 41; "Input - request from the PCI controller

NOT_A31 pin 42; "Output - Inverted A31 for CS to PCIcontroller

SIZ0 pin 43;

BDM_RST_L pin 44; "Input - BDM reset input

; "********************************"

; " Lattice attributes "

; "********************************"

pLSI property 'CLK XCLK0 CLK0 ';

pLSI property 'CLK CLK8MHZ SLOWCLK ';

pLSI property 'ISP ON';

pLSI property 'PULLUP ON';

pLSI property 'Y1_AS_RESET OFF';

; "--------------------------------"

; " Output inverter macro "

; "--------------------------------"

OB21 MACRO (XO0, A0)

{

?XO0 = !?A0;

};

; "--------------------------------"

; " Tristate Output inverter macro "

; "--------------------------------"

OT21 MACRO (XO0, A0, OE)

{

?XO0.OE = ?OE;

?XO0 = !?A0;

};

CBU43 MACRO (Q0,Q1,Q2,CLK,EN,CS)




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{

[?Q0..?Q2].clk = ?CLK;

?Q0.D = ?Q0.Q & !?CS $ ?EN & !?CS ;

?Q1.D = ?Q1.Q & !?CS $ ( ?Q0.Q & ?EN & !?CS );

?Q2.D = ?Q2.Q & !?CS $ ( ?Q0.Q & ?Q1.Q & ?EN & !?CS );

};

equations

;"###########################################"

;"Bidirectional circuit equations"

;"###########################################"

OT21 (TAL, DA, DAOE)

OB21 (IORL, IOR)

OB21 (IOWL, IOW)

OB21 (RST_L, RST_H)

IRQ3 = !ETHER_IRQ;

!DB_CS_L = !RST_H & !CS3_L;

!CS_FPCIBD_L = !RST_H & (!CS0_L # !CS1_L # !CS2_L);

NOT_A31 = !A31;

!GNTPCI_L = !REQPCI_L & GNTANC_L; " Grant PCI bus if not in useby the PCI

" controller.

!GNTANC_L = !REQANC_L & GNTPCI_L; " Grant PCI controller the busif not

" already granted to the PCI connector.

RST_H = !PORIN_L # !BDM_RST_L;

HIZ_L = 1;




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DAOE := !CS3_L # DA;

DAOE.clk = XCLK0 ;

A0 = !SIZ1 & SIZ0 & !A0IN #

A16 ;

SBHE = STARTISA & !SIZ1 & SIZ0 & !A0IN #

STARTISA & SIZ1 & !SIZ0 & !A0IN #

STARTISA & !SIZ1 & !SIZ0 & !A0IN ;

CLK16MHZ := !CLK16MHZ ;

CLK16MHZ.clk = XCLK0 ;

CLK8MHZ := CLK8MHZ & !CLK16MHZ #

!CLK8MHZ & CLK16MHZ ;


CLK4MHZ := CLK4MHZ $ ( CLK16MHZ & CLK8MHZ ) ;


" Total div. 6 to produce 8.333MHzfor Ethernet

" controller - Davicom DM9008from 50MHz - XCLK0.

DIV6Q0 := !DIV6Q0 & !DIV6Q1 ; " First D-type in divide by 3chain using XCLK0.

DIV6Q0.clk = XCLK0 ;

DIV6Q1 := DIV6Q0 & !DIV6Q1 ; " Second D-type in div. by 3chain using XCLK0.

DIV6Q1.clk = XCLK0 ;

DIV6Q2 := !DIV6Q2 ; " Divide by 2 fed from div. 3(total div. 6).




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DIV6Q2.clk = DIV6Q1 ;

DA := !CS3_L & END16 & ENDIT & !IOCS16L & RD & !CLK8MHZ & SBHE #

!CS3_L & END8 & ENDIT & RD & !CLK8MHZ #

DLYDA & !CS3_L #

DA & !CS3_L;

DA.clk=XCLK0;

DLYDA :=!CS3_L & END16 & ENDIT & !IOCS16L & !RD & !CLK8MHZ & SBHE #

!CS3_L & END8 & ENDIT & IOCS16L & !RD & !CLK8MHZ #

!CS3_L & END8 & ENDIT & !SBHE & !RD & !CLK8MHZ ;

DLYDA.clk=XCLK0;

STARTISA := !CS3_L & !ENDIT ;

STARTISA.clk = CLK8MHZ ;

CBU43 (BCLK0,BCLK1,BCLK2,CLK8MHZ,STARTISA,!STARTISA)

BALE = STARTISA & !CLK8MHZ & !BCLK2 & !BCLK1 & !BCLK0 & !IOR & !IOW ;

IOR = STARTISA & !BCLK2 & !BCLK1 & BCLK0 & !CLK8MHZ & RD #

IOR & !CS3_L ;

IOW = STARTISA & !BCLK2 & !BCLK1 & BCLK0 & !CLK8MHZ & !RD #

IOW & STARTISA ;

END16 = !BCLK2 & BCLK1 & !BCLK0 & !CLK8MHZ#

END16 & STARTISA ;

END8 = BCLK2 & !BCLK1 & BCLK0 & !CLK8MHZ #

END8 & STARTISA ;

ENDIT = END16 & !IOCS16L & IOCHRDY & DLYIOCHRDY0 & DLYIOCHRDY & SBHE & STARTISA#




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END8 & IOCS16L & IOCHRDY & DLYIOCHRDY0 & DLYIOCHRDY & STARTISA #

END8 & !SBHE & IOCHRDY & DLYIOCHRDY0 & DLYIOCHRDY & STARTISA ;

DLYIOCHRDY0:= IOCHRDY;

DLYIOCHRDY0.clk = CLK8MHZ ;

DLYIOCHRDY = IOCHRDY & CLK8MHZ #

DLYIOCHRDY & !CLK8MHZ ;

;"****************************************************"

;" Test Vector Section"

;"****************************************************"

test_vectors 'HIZ_L Test Vector'

([XCLK0,PORIN_L,BDM_RST_L,CS3_L]->[RST_H])

[P,1,1,1,]->[X];

[C,1,1,1,]->[X];

[C,1,0,1,]->[X];

[C,1,0,1,]->[X];

[C,1,1,1,]->[X];

[C,1,1,1,]->[X];

[C,0,1,1,]->[X];

[C,0,1,1,]->[X];

[C,0,1,1,]->[X];

[C,1,1,1,]->[X];

[C,1,1,0,]->[X];

[C,1,1,1,]->[X];

[C,1,1,1,]->[X];

[C,1,1,1,]->[X];

[C,0,1,1,]->[X];

[C,0,1,1,]->[X];

[C,0,1,1,]->[X];

[C,0,1,1,]->[X];

[C,0,1,1,]->[X];

[C,0,1,1,]->[X];

[C,0,1,1,]->[X];




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[C,0,1,1,]->[X];

[C,0,1,1,]->[X];

[C,1,1,1,]->[X];

[C,1,1,1,]->[X];

[C,1,1,1,]->[X];

[C,1,1,1,]->[X];

[C,1,1,0,]->[X];

[C,1,1,1,]->[X];

[C,1,1,1,]->[X];

[C,1,1,1,]->[X];

end




apps docs:ColdFire:5407:Eval Board UM NEW:5407_C_SDRAM_Equations.fm 8/11/00

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Appendix CSDRAM MUX PAL Equationmodule SDRAMmux

title 'SDRAM Mux Controller for the MCF5407EVM'

"MAR 16 '99 First revision of the code based on Bill Benners application note"

"5307mux device 'ispLSI22LV10';

;"*****************************************************"

;"This abel file contains the code to mux the address lines"

;"allowing the MCF5407 to support all 168pin 1Bank x 64 bit PC compliant DIMMS"

;"It was targeted to Lattice ispLSI 22LV10 PAL "

;"All logic with this PAL is com

;"CS:4C86 "

;"*****************************************************"

;"*****************************************************"

;"Declaration Section "

;"*****************************************************"

;" constants"

C,P,X,Z,H,L = .C.,.P.,.X.,.Z.,1,0;

;"*****************************************************"

M0 PIN 3; "Mux Input (0)




CA18 PIN 2; "Input - ColdFire driven address (18)





Appendix C. SDRAM MUX PAL Equation C-1




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SA8 PIN 24; "Output - SDRAM input address (A8)






BA0 PIN 18; "Output - SDRAM input address (BA0)

BA1 PIN 26; "Output - SDRAM input address (BA1)

select = [M3,M2,M1,M0];

; "********************************"

; " Lattice attributes "

; "********************************"

"pLSI property 'CLK XCLK0 CLK0 ';

"pLSI property 'CLK CLK8MHZ SLOWCLK ';

pLSI property 'ISP ON';

pLSI property 'PULLUP ON';

pLSI property 'Y1_AS_RESET OFF';

equations

;"###########################################"

;"COMBINATORIAL Logic Only"

;"###########################################"

when (select == 0) then { SA8=CA18;

SA9=CA19;

SA10=CA20;

BA0=CA21;

C-2 BookTitle




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BA1=CA22;

}


SA9=CA20;

SA10=CA21;

BA0=CA22;

BA1=CA23;

}


SA9=CA21;

SA10=CA22;

BA0=CA23;

BA1=CA24;

}


SA9=CA19;

SA10=CA20;

SA11=CA21;

BA0=CA22;

BA1=CA23;

}

when (select == 4) then {

SA8=CA19;

SA9=CA20;

SA10=CA21;

SA11=CA22;

BA0=CA23;

BA1=CA24;

}


SA8=CA19;





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SA9=CA21;

SA10=CA22;

SA11=CA23;

BA0=CA24;

BA1=CA25;

}


SA8=CA19;

SA9=CA21;

SA10=CA23;

SA11=CA24;

BA0=CA25;

BA1=CA26;

}


SA9=CA19;

SA10=CA20;

SA11=CA21;

SA12=CA22;

BA0=CA23;

BA1=CA24;

}


SA9=CA20;

SA10=CA21;

SA11=CA22;

SA12=CA23;

BA0=CA24;

BA1=CA25;

}


SA9=CA21;

C-4 BookTitle




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SA10=CA22;

SA11=CA23;

SA12=CA24;

BA0=CA25;

BA1=CA26;

}

when (select == ^h0A) then { SA8=CA19;

SA9=CA21;

SA10=CA23;

SA11=CA24;

SA12=CA25;

BA0=CA26;

BA1=CA27;

}

"****************************************************"

" Test Vector Section"

"****************************************************"

test_vectors 'M0, M1, M2, M3 Test Vector'

([M3, M2, M1, M0, CA18, CA19, CA20, CA21, CA22, CA23, CA24, CA25, CA26,CA27]->[SA8, SA9, SA10, SA11, SA12, BA0, BA1])

[0,0,0,0,1,0,1,0,1,0,1,0,1,0]->[X,X,X,X,X,X,X];

[0,0,0,1,1,0,1,0,1,0,1,0,1,0]->[X,X,X,X,X,X,X];

[0,0,1,0,1,0,1,0,1,0,1,0,1,0]->[X,X,X,X,X,X,X];

[0,0,1,1,1,0,1,0,1,0,1,0,1,0]->[X,X,X,X,X,X,X];

[0,1,0,0,1,0,1,0,1,0,1,0,1,0]->[X,X,X,X,X,X,X];

[0,1,0,1,1,0,1,0,1,0,1,0,1,0]->[X,X,X,X,X,X,X];

[0,1,1,0,1,0,1,0,1,0,1,0,1,0]->[X,X,X,X,X,X,X];

[0,1,1,1,1,0,1,0,1,0,1,0,1,0]->[X,X,X,X,X,X,X];

[1,0,0,0,1,0,1,0,1,0,1,0,1,0]->[X,X,X,X,X,X,X];

[1,0,0,1,1,0,1,0,1,0,1,0,1,0]->[X,X,X,X,X,X,X];

end





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C-6 BookTitle




apps docs:ColdFire:5407:Eval Board UM NEW:5407_D_EvalBdBOM.fm 8/11/00

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Appendix DEvaluation Board BOM

Table D-1. MCF5407EVM_BOM

Item Qty Reference Part Function

1 1 BT1 VARTA CR2032PCB Battery for RTC (not populated)

2 41 C1,C2,C3,C4,C13,C14,C15,C16,C17,C18,C37,C38,C40,C41,C42,C43,C44,C62,C63,C64,C65,C66,C67,C79,C80,C82,C83,C86,C89,C90,C96,C99,C103,C104,C105,C106,C107,C108,C109,C110,C125

0.1 UF SMT Capacitor

3 53 C5,C6,C7,C8,C9,C10,C19,C20,C21,C22,C23,C24,C45,C46,C47,C48,C49,C50,C51,C53,C54,C55,C56,C57,C58,C59,C60,C61,C68,C69,C70,C71,C72,C73,C74,C75,C76,C77,C84,C85,C87,C91,C92,C93,C111,C112,C113,C114,C115,C116,C118,C119,C120

1nF SMT Capacitor

4 6 C11,C30,C31,C32,C33,C34 220pF SMT Capacitor

5 7 C12,C35,C94,C121,C122,C123,C124

10 uF TANT. SMT Capacitor

6 9 C25,C26,C27,C28,C29,C36,C39,C81,C88

10nF SMT Capacitor

7 1 C52 0.1uF SMT Capacitor

8 1 C95 100uF TANT. SMT Capacitor

9 2 C97,C101 AVX TPSE220M10RLM SMT Capacitor

10 1 C98 AVX TPSE330K10CLR SMT Capacitor

11 1 C100 1000uF 35V SMT Capacitor

12 6 D1,D3,D5,D7,D12,D13 LTL-94PCK-TA SMT LED

13 5 D2,D4,D6,D8,D11 LTL-94PGK-TA SMT LED

14 2 D9,D10 LTL-94PYK-TA SMT LED

Appendix D. Evaluation Board BOM D-1




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15 2 D14,D15 MRA4003T3 SMT Power Diode

16 5 D16,D18,D19,D20,D21 MBRS340T3 SMT Schottky Power Diode

17 1 F1 MULTICOMP MCHTE-15M

Fuse

18 17 JP1,JP2,JP3,JP4,JP5,JP6,JP7,JP8,JP9,JP10,JP11,JP12,JP13,JP14,JP19,JP25,JP29

JP2 2-way Jumpers

19 13 JP15,JP16,JP17,JP18,JP20,JP21,JP22,JP23,JP24,JP26,JP27,JP28,JP30

JP3 3-way Jumpers

20 2 J1,J2 AMP 177983-5 120-way SMT Receptacle expansion connectors

21 1 J3 Universal 32-bit PCI Connector

22 1 J4 JUMP1X8 Reset configuration jumpers

23 1 J5 HJ2X13 KEYED w/ plastic outline

BDM connector

24 1 J6 I2C Molex Conn. 71565 I2C socket (not populated)

25 1 J7 AMP350210-1 3-way +/-12V connector

26 1 L2 FERRITE_BEAD Inductor for Ethernet controller supply filter

27 2 L3,L4 SIEMENS B82111-B-C24 25uH PSU switching inductors

28 1 P1 RJ45 thru board connector

29 1 P3 Augat 25V-02 PSU bare wire connector

30 2 P5,P4 RS232 port thru board connectors DB9

31 1 P6 Switchcraft RAPC712 PSU barrel connector

32 23 RP1,RP4,RP6,RP7,RP8,RP9,RP10,RP11,RP12,RP15,RP16,RP17,RP18,RP19,RP20,RP21,RP22,RP24,RP25,RP26,RP30,RP31,RP34

PHILIPS ARV241-4K7 SMT 4K7x4 resistor packs

33 3 RP2,RP3,RP5 PHILIPS ARV241-270 SMT 270x4 resistor packs

34 6 RP13,RP14,RP27,RP28,RP29,RP32

PHILIPS ARV241-22 SMT 22x4 resistor packs

35 1 RP23 PHILIPS ARV241-22 SMT 22x4 resistor pack

36 1 RP33 PHILIPS ARV241-4K7 SMT 4K7x4 resistor pack

37 4 RP35,RP36,RP37,RP38 PHILIPS ARV241-4K7 SMT 4K7x4 resistor packs

Table D-1. MCF5407EVM_BOM (Continued)


D-2 BookTitle




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38 3 R1,R2,R23 SMT 4K7 resistors

39 1 R3 SMT 10 resistor


41 2 R5,R6 51

42 3 R7,R10,R11 SMT 270 resistors

43 1 R8 SMT 1K resistor

44 1 R9 SMT 3K resistor

45 1 R12 SMT 4.7K resistor

46 4 R13,R16,R17,R18 SMT 10K resistors



49 1 S1 KS11R23CQD Hard reset red push-button switch

50 1 S2 KS11R22CQD /IRQ7 black push-button switch

51 TP1,TP2,TP3,TP4,TP5,TP6,TP7,TP8,TP9,TP10

TEST POINTS

52 1 U1 MCF5407FT150 MCF5407 ColdFire processor

53 5 U2,U3,U4,U5,U7 MC74LCX16245DT 16-bit wide bus transceiver

54 1 U6 MC74LCX16244DT 16-bit wide bus buffer

55 1 U8 DM9008F Davicom 10BaseT ethernet controller

56 1 U9 AT93C46-10SC-2.7-8S1 I2C E2PROM not populated during assembly

57 1 U10 OSC 20 MHZ Oscillator for ethernet clock.

58 1 U11 FD22-101G Halo ethernet filter

59 1 U12 Am29PL160C-120 AMD 1Mx16 burst Flash memory

60 1 U13 MCM69F737TQ11* Burst FSRAM (not populated)

61 1 U14 M41T11M I2C Real-time clock

62 1 U16 X24C04S8 -1.8 I2C E2PROM (not populated)

63 1 U17 Anchor AN3042Q Cypress PCI Controller

64 1 U18 ispLSI2032V-100LJ 2000 series Lattice FPGA SMT

65 1 U19 MAX6355LSUT-T Maxim reset controller chip

66 1 U20 TLC7733ID TI switch debounce circuit

67 1 U21 OSC 50MHz System clock for the MCF5407



Appendix D. Evaluation Board BOM D-3




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*Alternate Parts - Samsung K7B403625M, GalvantechGVT71128E36,ISSI IS61SF12836,Micron MT58L128L36F1, GSI GS84036A, IDT 71V3577, Cypress CY7C1345

68 1 U22 LT1086CM 3.3V to 1.8V regulator

69 1 U23 LM2596S-3.3 5V to 3.3V regulator

70 1 U24 CDC351DB Clock driver IC 1 to 10 way

71 U25 LM2596S-5 +6.5V to +14V I/P to 5V regulator

72 1 U26 PC100 Unbuffered 1 Bank x 64 DIMM 8M or 16M, support for up to 512M

Volatile main system memory

73 1 U27 ispGAL22LV10 Lattice PAL - SDRAM multiplexing SMT

74 1 U28 MC145407DW RS232 transceiver (plus charge pump)

75 1 U29 MC145406DW RS232 transceiver

76 1 U30 OSC 33MHz PCI clock

77 1 U31 MPC905D Clock driver for 33MHz PCI clock signal, 1 to 6 way

78 11 V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11

VIA's

79 1 Y1 32.768KHz Real time clock watch crystal



D-4 BookTitle




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Appendix E Schematics

Appendix E . Schematics E-1




-2

M5407C3 User’s Manual


A A

B B

C C

D D

E E

44

33

22

11

INITIAL RESET CONFIGURATION:

D0: PRESET DIV0

D1: PRESET DIV1

D2: PRESET DIV2

D3: BE[3:0] CONF

D4: ADDR_CONF

D5: BOOT PORT SIZE [0]

D6: BOOT PORT SIZE [1]

D7: CS0 AA ENABLE

JUMPER 1&2 DEFAULT

SETTING IS INSTALLED

DURING ASSEMBLY.

Bi-Buffers

Bi-Buffers

Uni-Buffers

Uni-Buffers

Uni-Buffers

DEFAULT SETTING -

JUMPERS 5&7 SHOULD

BE INSTALLED DURING

ASSEMBLY.

MS

PS

SE

SG

Col

dFire

Gro

up

Bi-Buffers

MC

F54

07.B

UF

FE

RS

1.1

MC

F54

07 E

valu

atio

n B

oard

B

110

Frid

ay, J

uly

14, 2

000

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

MA

2

MA

4

MA

8

MA

10

MA

12

FB

_D25

B_D

[16:

31]

B_D

21

FB

_D26

FB

_D20 B_D

25

B_D

20

FB

_D16

FB

_D21

FB

_D22 B_D

24

B_D

31

B_D

19

FB

_D18

FB

_D19 B_D

23

B_D

26

FB

_D27

FB

_D28

FB

_D17

FB

_D29

FB

_D23

FB

_D31

FB

_D30

FB

_D24 B_D

16

B_D

28

B_D

18

B_D

22

B_D

27

B_D

17

B_D

30B

_D29

D27

D22

D21

D20

D25

D17

D17

D19

D18

D23

D16

D23

D28

D27

D31

D30

D24

D21

D20

D28

D30

D31

D29

D19

D25

D16

D26

D26

D24

D29

D22

D18 P

P2

PP

3

PP

7

D7

D6

D5

D4

D3

D2

D1

D0

PP

6

PP

4P

P5

PP

0P

P1

MA

16M

A17

MA

18M

A19

MA

20

A15

A22

A9

A12

A7

A23

A10

A20

A1

A14

A24

A11

A6

A0

A2

A3

A4

A5

A8

A13

MA

15M

A14

MA

13

MA

11

MA

9

MA

7M

A6

MA

5

MA

3

MA

1M

A0

A16

A17

A18

A19

A21

A25

A26

A27

A28

A29

FB

_D10

FB

_D11

FB

_D12

FB

_D13

FB

_D14

D15

D14

D5

D0

D4

D3

FB

_D9

D2

D1

D11

FB

_D4

FB

_D5

FB

_D6

FB

_D7

FB

_D8

D10

FB

_D15

D13

FB

_D[0

:31]

D9

D12

D8

D[0

:31]

D7

D6

FB

_D0

FB

_D1

FB

_D2

FB

_D3

+3.3

+3.3

+3.3 +3

.3

+3.3

+3.3

+3.3

+3.3

+3.3

RP

3

4x 2

70

11

22

33

44

55

66

77

88

D2

LED SMT GRN

C8

1nF

C2

0.1

UF

D7

LED SMT RED

JP10

12

C9

1nF

C3

0.1

UF

JP2

TO

UT

1

12

RP

1

4x 4

.7K

11

22

33

44

55

66

77

88

JP6

12

JP3

12

U3

MC

74LC

X16

245D

T

1B1

2

1B2

3

1B3

5

1B4

6

1B5

8

1B6

9

1B7

11

1B8

12

2B1

13

2B2

14

2B3

16

2B4

17

2B5

19

2B6

20

2B7

22

2B8

23

1DIR

1

1OE

48

2OE

25

2DIR

24

GN

D4

GN

D10

GN

D15

GN

D21

GN

D28

GN

D34

GN

D39

GN

D45

1A1

47

1A2

46

1A3

44

1A4

43

1A5

41

1A6

40

1A7

38

1A8

37

2A1

36

2A2

35

2A3

33

2A4

32

2A5

30

2A6

29

2A7

27

2A8

26

VC

C7

VC

C18

VC

C31

VC

C42

D1

LED SMT RED

V9

VIA

1V6

VIA

1

D9

LED SMT YEL

RP

4

4x 4

.7K

11

22

33

44

55

66

77

88

C10

1nF

C4

0.1

UF

V1

VIA

1

RP

6

4x 4

.7K

11

22

33

44

55

66

77

88

D6

LED SMT GRN

D3

LED SMT RED

JP7

12

U5

MC

74LC

X16

245D

T

1B1

2

1B2

3

1B3

5

1B4

6

1B5

8

1B6

9

1B7

11

1B8

12

2B1

13

2B2

14

2B3

16

2B4

17

2B5

19

2B6

20

2B7

22

2B8

23

1DIR

1

1OE

48

2OE

25

2DIR

24

GN

D4

GN

D10

GN

D15

GN

D21

GN

D28

GN

D34

GN

D39

GN

D45

1A1

47

1A2

46

1A3

44

1A4

43

1A5

41

1A6

40

1A7

38

1A8

37

2A1

36

2A2

35

2A3

33

2A4

32

2A5

30

2A6

29

2A7

27

2A8

26

VC

C7

VC

C18

VC

C31

VC

C42

D4

LED SMT GRN

C5

1nF

D10

LED SMT YEL

JP4

12

V10

VIA

1

U4

MC

74LC

X16

245D

T

1B1

2

1B2

3

1B3

5

1B4

6

1B5

8

1B6

9

1B7

11

1B8

12

2B1

13

2B2

14

2B3

16

2B4

17

2B5

19

2B6

20

2B7

22

2B8

23

1DIR

1

1OE

48

2OE

25

2DIR

24

GN

D4

GN

D10

GN

D15

GN

D21

GN

D28

GN

D34

GN

D39

GN

D45

1A1

47

1A2

46

1A3

44

1A4

43

1A5

41

1A6

40

1A7

38

1A8

37

2A1

36

2A2

35

2A3

33

2A4

32

2A5

30

2A6

29

2A7

27

2A8

26

VC

C7

VC

C18

VC

C31

VC

C42

V2

VIA

1 V7

VIA

1

D5

LED SMT RED

U6

MC

74LC

X16

244D

T

1Y1

2

1Y2

3

1Y3

5

1Y4

6

2Y1

8

2Y2

9

2Y3

11

2Y4

12

3Y1

13

3Y2

14

3Y3

16

3Y4

17

4Y1

19

4Y2

20

4Y3

22

4Y4

23

1OE

1

2OE

48

3OE

25

4OE

24

GN

D4

GN

D10

GN

D15

GN

D21

GN

D28

GN

D34

GN

D39

GN

D45

1A1

47

1A2

46

1A3

44

1A4

43

2A1

41

2A2

40

2A3

38

2A4

37

3A1

36

3A2

35

3A3

33

3A4

32

4A1

30

4A2

29

4A3

27

4A4

26

VC

C7

VC

C18

VC

C31

VC

C42

JP8

12

C6

1nF

V3

VIA

1

RP

5 4x 2

70

11

22

33

44

55

66

77

88

V11

VIA

1

JP5

12

C7

1nF

V4

VIA

1

U7

MC

74LC

X16

245D

T

1B1

2

1B2

3

1B3

5

1B4

6

1B5

8

1B6

9

1B7

11

1B8

12

2B1

13

2B2

14

2B3

16

2B4

17

2B5

19

2B6

20

2B7

22

2B8

23

1DIR

1

1OE

48

2OE

25

2DIR

24

GN

D4

GN

D10

GN

D15

GN

D21

GN

D28

GN

D34

GN

D39

GN

D45

1A1

47

1A2

46

1A3

44

1A4

43

1A5

41

1A6

40

1A7

38

1A8

37

2A1

36

2A2

35

2A3

33

2A4

32

2A5

30

2A6

29

2A7

27

2A8

26

VC

C7

VC

C18

VC

C31

VC

C42

RP

2

4x 2

70

11

22

33

44

55

66

77

88

D8

LED SMT GRN

U2

MC

74LC

X16

245D

T

1B1

2

1B2

3

1B3

5

1B4

6

1B5

8

1B6

9

1B7

11

1B8

12

2B1

13

2B2

14

2B3

16

2B4

17

2B5

19

2B6

20

2B7

22

2B8

23

1DIR

1

1OE

48

2OE

25

2DIR

24

GN

D4

GN

D10

GN

D15

GN

D21

GN

D28

GN

D34

GN

D39

GN

D45

1A1

47

1A2

46

1A3

44

1A4

43

1A5

41

1A6

40

1A7

38

1A8

37

2A1

36

2A2

35

2A3

33

2A4

32

2A5

30

2A6

29

2A7

27

2A8

26

VC

C7

VC

C18

VC

C31

VC

C42

C1

0.1

UF

JP1

TO

UT

0

12

JP9

12

V8

VIA

1V5

VIA

1

R/-

W-C

S_F

PC

IBD

FB

_D[0

:31]

A[0

:31]

B_D

[16:

31]

D[0

:31]

R/-

W-B

D_C

S3

-CS

_FP

CIB

DR

/-W

PP

[0:7

]

-CF

_RS

TI

TO

UT

0

TO

UT

1

MA

[0:2

0]

Fre

esc

ale

Se

mic

on

du

cto

r, I



nc

...

Appendix E . Schematics

-3


A A

B B

C C

D D

E E

4 3 2 1

DEFAULT SETTING

- JUMPERS 11&12

SHOULD BE

INSTALLED.

DEFAULT SETTING -

JUMPERS 13&14 SHOULD

BE INSTALLED.

ColdFire®

CPU Core supply decoupling.

I/O ring supply decoupling.

NOTE: R3 is 1206

size and may be

changed to 220uH

inductor in same

package.

SP

S S

ES

G C

oldF

ire G

roup

M

MC

F54

07 C

PU

1.1

MC

F54

07 E

valu

atio

n B

oar

d

B

21

0F

riday

, Jul

y 14

, 200

0

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

PP5

PP7

-CS

6

D9

D12

D24

SD

A

A1

D7

D17

A24

-CS

0-C

S1

A26

TIN

1

D[0

:31]

PP

[0:7

]

PP6

PP4

A2

A6

A12

D20

A27

A7

D18

PP2

D5

D22

A25

-CT

S1

RX

D0

PP5

D6

A9

A18

-RT

S0

PP0

PSTDDATA6PSTDDATA7

-CS

3

-CS

5

D8

A10

A14

A20

A28

TIN

0

-CT

S0A22

RX

D1

PS

TD

DA

TA

2-CS

7

A4

D16

A19

D11

D13

A23

D27

D31

A8

D14

D19

A0

D4

A21

D21

D26

D28

-RT

S1

TX

D1

PS

TD

DA

TA

1

D2

A11

A16

A17

D25

A31

TO

UT

0

D1

D3

D10

A13

A29

D30

-OE

PS

TD

DA

TA

0

PSTDDATA4P

ST

DD

AT

A3

PSTDDATA5

PP1

A5

D29

TO

UT

1

A[0

:31]

PP3

PP6

D0

A3

A15

D15

D23

A30

-CS

4

SC

L

-CS

2

PS

TD

DA

TA

[4:7

]

TX

D0

+3.

3

+3.

3

+3.

3

+3.

3

+3V

P

+3.

3

+3.

3

IVC

C

IVC

C

+3.

3+

3.3

+3.

3

+3.

3+

3.3

IVC

C

+3V

P

+3.

3

RP

134x

22

11

22

33

44

55

66

77

88

RP

74x

4.7

K

11

22

33

44

55

66

77

88

C21

1nF

RP

16 4x 4

.7K

11

22

33

44

55

66

77

88

C22

1nF

C26

10nF

RP

144x

22

11

22

33

44

55

66

77

88

RP

17 4x 4

.7K

11

22

33

44

55

66

77

88

C25

10nF

RP

34

4x 4

.7K

11

22

33

44

55

66

77

88

C23

1nF

RP

18

4x 4

.7K

11

22

33

44

55

66

77

88

C14

0.1

UF

JP14

DR

EQ

01

2

C18

0.1

UF

C27

10nF

C13

0.1

UF

U1

MC

F54

07F

T15

0

GND961

PSTDDATA0186

GND1069

MTMOD0176

GND1177

PSTDDATA1187

GND1393

PSTDDATA4192

GND14101

PSTDDATA2189

GND15104

MTMOD1177

GND16109

PSTDDATA3190

GND17117

TT0/PP0207

GND18125

MTMOD2181

GND19133

PSTDDATA5193

GND20141

MTMOD3182

GND21148

BW

E0

96

GND22156

GND1285

PSTDDATA6195

GND23162

TT1/PP1206

GND24169

PSTDDATA7196

GND25173

IRQ

172

GND26178

TM0/PP2204

GND27183

BW

E1

98

GND28188

TM1/PP3203

GND29194

CS

050

GND30201

TM2/PP4202

GND31208

BW

E2

99

DREQ1/PP5200

IRQ

371

DREQ0/PP6199

BW

E3

100

XTIP/PP7198

NC

179

IRQ

570

CS

151

IRQ

768

GND14

CS

254

IVCC11

CS

355

GND210

CS

456

A0

2

CS

558

GND317

CS

659

EVCC27

CS

760

GND425

D0147

GND533

EVCC313

GND641

A1

3

GND748

EVCC421

GND853

D1146

EVCC529

A2

5

EVCC637

D2144

EVCC745

A3

6

EVCC852

D3143

IVCC957

A4

8

EVCC1065

D4142

IVCC1173

A5

9

EVCC1281

D5140

EVCC1389

A6

11

EVCC1497

D6139

IVCC15105

A7

12

EVCC16113

D7138

EVCC17121

A8

14

EVCC18129

D8136

EVCC19137

A9

15

EVCC20145

D9135

IVCC21152

A10

16

IVCC22157

D10134

EVCC23167

A11

18

IVCC24171

D11132

IVCC25175

A12

19

PVCC180

D12131

IVCC27185

A13

20

EVCC28191

D13130

A14

22

D14128

A15

23

D15127

A16

24

D16126

A17

26

D17124

A18

27

D18123

A19

28

D19122

A20

30

D20120

A21

31

D21119

A22

32

D22118

A23

34

D23116

A24

/PP

835

D24115

A25

/PP

936

D25114

A26

/PP

1038

D26112

A27

/PP

1139

D27111

A28

/PP

1240

D28110

A29

/PP

1342

D29108

A30

/PP

1443

D30107 A31

/PP

1544

D31106

IVCC29197

EVCC30205

TA

64

AS

62

R/W

63

TS

66

RS

TI

67

BR

74

BD

75

BG

76

OE

49

SIZ

046

SIZ

147

TOUT079TOUT178TIN080TIN182

RA

S0/

SO

083

RA

S1/

SO

284

CA

S0/

DQ

M0

86

CA

S1/

DQ

M1

87

CA

S2/

DQ

M2

88

CA

S3/

DQ

M3

90

DR

AM

W91

SR

AS

92

SC

AS

94

SC

KE

95

SC

L10

2

SD

A10

3

DS

CLK

/TR

ST

149

TC

K15

0

DS

O/T

DO

151

DS

I/TD

I15

3

BK

PT

/TM

S15

4

HIZ

155

BC

LKO

170

RS

TO

172

CLK

IN17

4

PS

TC

LK18

4

CTS1158RTS1159RXD1160TXD1161

CTS0163RTS0164RXD0165TXD0166

ED

GE

SE

L16

8

RP

10

4x 4

.7K

11

22

33

44

55

66

77

88

C28

10nF

C17

0.1

UF

C29

10nF

C24

1nF

RP

11 4x 4

.7K

11

22

33

44

55

66

77

88

RP

15 4x 4

.7K

11

22

33

44

55

66

77

88

C30

220p

F

C19

1nF

C16

0.1

UF

JP13

DR

EQ

11

2

C31

220p

F

RP

8

4x 4

.7K

11

22

33

44

55

66

77

88

RP

124x

4.7

K

112

2

334

4

556

6

778

8

JP11

3.3V

12

C32

220p

F

R3

10

C15

0.1

UF

C11

220p

F

C33

220p

F

R1

4K7

C34

220p

F

C12

10 u

F T

AN

T.

C20

1nF

R2

4K7

PS

TD

DA

TA

[4:7

]

PP

[0:7

]D

[0:3

1]

A[0

:31]

-CS

1-C

S2

-CS

3-C

S4

-CS

5-C

S6

-CS

7

-CS

0

-OE

PS

TD

DA

TA

[0:3

]

SC

LS

DA

-RT

S1

TX

D1

-RT

S0

TX

D0

TO

UT

0T

OU

T1

RX

D0

-CT

S0

RX

D1

-CT

S1

TIN

1T

IN0

MT

MO

D3

MT

MO

D2

MT

MO

D1

MT

MO

D0

00

-OE

-CS

3

SC

KE

-SC

AS

IRQ

1IR

Q3

IRQ

5IR

Q7

-AS

R/-

W -TA

-TS

RS

TI

-BR

-BD

-BG

WE

0W

E1

WE

2W

E3

SIZ

0S

IZ1

ES

EL

TC

LKC

LKIN

RS

TO

LKO

HIZ

TM

S_T

DI

TD

OT

CK

RS

T

SO

0S

O2

M0

M1

M2

M3

MW

S

Freescale Semiconductor, I

Fre

esc

ale

Se

mic

on

du

cto

r, I

nc

.

Fo

r M

ore

In

form

ati

on

On

Th

is P

rod

uc

t,

Go

to

: w

ww

.fre

esc

ale

.co

m

nc...

F

ree

sca

le S

em

ico

nd

uc

tor,

I


c..

.

A A

B B

C C

D D

E E

Ethernet 10 Base-T

Ethernet E2

Ethernet Filter

Ethernet Osc.

SP

S S

ES

G C

old

Fire

Gro

up

M

MC

F5407 E

TH

ER

NE

T

MC

F5407 E

valu

atio

n B

oard

B

3F

riday, July

14, 2000

Title

Siz

eD

ocu

ment N

um

ber

Date

:S

heet

B_D

[16:3

1]

MA

8

MA

6

MA

1M

A2

MA

3M

A4

MA

5

MA

9

MA

7

B_D

16

B_D

17

B_D

18

B_D

19

B_D

20

B_D

21

B_D

22

B_D

23

B_D

24

B_D

25

B_D

26

B_D

27

B_D

28

B_D

29

B_D

30

B_D

31

+5

+5

+5

+5

+5

+5

+5

+5

+5

U11

FD

22-1

01G

TP

TX

+16

NC

115

TP

TX

-14

TP

RX

+11

NC

210

TP

RX

-9

TD

X+

1

AG

ND

12

TX

D-

3

RX

I+6

AG

ND

27

RX

I-8

R4 2

2

1 2 3 4 5 6 7 8

P1

RJ4

5 T

h

1 2 3 4 5 6 7 8

L2

FE

RR

ITE

_B

EA

D

12

RP

26

4x

4.7

K

11

22

33

44

55

66

77

88

C35

10

UF

TA

NT

.

C40

0.1

UF

C41

0.1

UF

C42

0.1

UF

C43

0.1

UF

C36

10nF

C44

0.1

UF

U8

DM

9008F

GN

D4

52

GN

D3

73

GN

D2

74

GN

D1

75

VC

C1

1

IRQ

36

VC

C2

53

PA

756

VC

C3

72

IRQ

48

MS

D7

71

IRQ

510

PA

657

IRQ

934

SY

SC

LK

14

IRQ

10

94

PA

558

IRQ

11

93

MS

D6_S

LO

T70

IRQ

12

92

PA

459

IRQ

15

91

SA

096

PA

360

MS

D5_B

NC

SW

69

PA

261

IOR

*19

PA

162

MS

D4

68

PA

063

SD

026

MS

D3

67

IOW

*21

MS

D2_E

EC

K66

SA

197

MS

D1_E

ED

065

SM

EM

R*

23

MS

D0_E

ED

164

SD

127

RS

T35

SA

298

AE

N*

24

SD

228

ME

MW

*89

SA

399

ME

MR

*90

SD

329

AV

DD

136

SA

43

AV

DD

247

SD

430

AV

DD

348

SA

54

AG

ND

143

SD

531

AG

ND

244

SA

65

AG

ND

351

SD

632

SA

77

SD

733

SA

89

SD

888

SA

911

SD

987

SA

10

12

SD

10

86

SA

11

13

SD

11

85

SD

12

84

SD

13

83

SD

14

82

SD

15

81

SA

14

15

SA

15

16

SA

16

17

SA

17

18

SA

18

20

SA

19

22

BA

LE

2

EE

CS

79

BP

CS

*80

IO16*

95

IOC

HR

DY

*25

X1

78

X2

77

BN

CE

N54

TX

+38

TX

-37

RX

+40

RX

-39

CD

+42

CD

-41

TP

TX

+50

TP

TX

-49

TP

RX

+46

TP

RX

-45

LIL

ED

55

NC

76

GN

D0

100

U10

OS

C 2

0 M

HZ

NC

1

GN

D7

CLK

8

VC

C14

C37

0.1

UF

C38

0.1

UF

RP

19

4x

4.7

K

11

22

33

44

55

66

77

88

R5

51

R6

51

C39

10nF

U9

AT

93C

46-1

0S

C-2

.7-8

S1 n

ot popula

ted d

uring a

ssem

bly

SK

2

DI

3

DO

4

CS

*1

NC

7

OR

G6

VC

C8

GN

D5

RP

20

4x

4.7

K

11

22

33

44

55

66

77

88

D11

LE

D G

RE

EN

R7

270

B_D

[16:3

1]

MA

[0:2

0]

SA

0

BA

LE

EC

LK

-IO

R

-IO

W

ET

H_

RE

SE

T

-IO

16

-IO

CH

RD

Y

-ET

H_IR

Q3

-4 M5407C3 User’s Manual




F

ree

sca

le S

em

ico

nd

uc

tor,

I


c..

.

AB

CD

E

4 3 2 1

SP

S S

ES

G C

old

Fire

Gro

up

M

120 w

ay

Exp

ansi

on C

onnect

ors

MC

F5407 E

valu

atio

n B

oard

B

Friday, July

14, 2000

Title

Siz

eD

ocu

ment N

um

ber

Date

:S

heet

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

D31

D[0

:31]

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

A[0

:31]

A16

PP

0P

P1

PP

2P

P3

PP

4

PP

5P

P6

PP

7

PS

TD

DA

TA

7P

ST

DD

AT

A6

PS

TD

DA

TA

5P

ST

DD

AT

A4

PS

TD

DA

TA

3P

ST

DD

AT

A2

PS

TD

DA

TA

1P

ST

DD

AT

A0P

P[0

:7]

+3

.3IV

CC

IVC

C+

3.3

+5

+5

IVC

C+

3.3

+5

IVC

C+

3.3

+5

+3

.3+

3.3

+3

.3

C55

1nF

C54

1nF

C53

1nF

C48

1nF

C49

1nF

C50

1nF

C51

1nF

C45

1nF

C46

1nF

C47

1nF

C61

1nF

J1

AM

P 1

77983-5

120w

ay S

MT

Recepta

cle

11

22

33

44

55

66

77

88

99

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

31

31

32

32

33

33

34

34

35

35

36

36

37

37

38

38

39

39

40

40

41

41

42

42

43

43

44

44

45

45

46

46

47

47

48

48

49

49

50

50

51

51

52

52

53

53

54

54

55

55

56

56

57

57

58

58

59

59

60

60

61

61

62

62

63

63

64

64

65

65

66

66

67

67

68

68

69

69

70

70

71

71

72

72

73

73

74

74

75

75

76

76

77

77

78

78

79

79

80

80

81

81

82

82

83

83

84

84

85

85

86

86

87

87

88

88

89

89

90

90

91

91

92

92

93

93

94

94

95

95

96

96

97

97

98

98

99

99

100

100

101

101

102

102

103

103

104

104

105

105

106

106

107

107

108

108

109

109

110

110

111

111

112

112

113

113

114

114

115

115

116

116

117

117

118

118

119

119

120

120

C60

1nF

J2

AM

P 1

77983-5

120w

ay S

MT

Recepta

cle

11

22

33

44

55

66

77

88

99

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

31

31

32

32

33

33

34

34

35

35

36

36

37

37

38

38

39

39

40

40

41

41

42

42

43

43

44

44

45

45

46

46

47

47

48

48

49

49

50

50

51

51

52

52

53

53

54

54

55

55

56

56

57

57

58

58

59

59

60

60

61

61

62

62

63

63

64

64

65

65

66

66

67

67

68

68

69

69

70

70

71

71

72

72

73

73

74

74

75

75

76

76

77

77

78

78

79

79

80

80

81

81

82

82

83

83

84

84

85

85

86

86

87

87

88

88

89

89

90

90

91

91

92

92

93

93

94

94

95

95

96

96

97

97

98

98

99

99

100

100

101

101

102

102

103

103

104

104

105

105

106

106

107

107

108

108

109

109

110

110

111

111

112

112

113

113

114

114

115

115

116

116

117

117

118

118

119

119

120

120

C59

1nF

C58

1nF

C57

1nF

C56

1nF

D[0

:31]

-HIZ

-BK

PT

_T

MS

DS

DI_

TD

I

DS

DO

_T

DO

TC

KD

SC

LK

_T

RS

T

A[0

:31]

SIZ

0S

IZ1

-OE

-CS

0-C

S1

-CS

2-C

S3

-CS

4

-CS

5-C

S6

-CS

7

-AS

R/-

W -TS

-CF

_R

ST

I

-BD

-BG

TO

UT

1T

OU

T0

TIN

0

TIN

1-R

_R

AS

0/S

O0

-R_R

AS

1/S

O2

-R_C

AS

0/D

QM

0-R

_C

AS

1/D

QM

1-R

_C

AS

2/D

QM

2

-R_C

AS

3/D

QM

3-R

_D

RA

MW

-R_S

RA

S

-R_S

CA

SR

_S

CK

E-B

WE

0

-BW

E1

-BW

E2

-BW

E3

SC

L

-A31

PS

TC

LK

MT

MO

D3

MT

MO

D2

MT

MO

D1

MT

MO

D0

CLK

IN

-RS

TO

BC

LK

O

ED

GE

SE

L

TX

D0

-RT

S0

TX

D1

-RT

S1

-CS

_F

PC

IBD

-TA

-BR

SD

A-C

TS

1

RX

D1

-CT

S0

RX

D0

PP

[0:7

]

PS

TD

DA

TA

[4

PS

TD

DA

TA

[0

-IR

Q1

-IR

Q3

-IR

Q5

-IR

Q7

Appendix E . Schematics -5




F

ree

sca

le S

em

ico

nd

uc

tor,

I


c..

.

A A

B B

C C

D D

E E

FSRAM

16-B

IT W

IDE

FLA

SH

DEFAULT SETTING -

JUMPER 15 SHOULD BE

INSTALLED ACROSS PINS

1&2.

SP

S S

ES

G C

old

Fire

Gro

up

M

MC

F5407 F

LA

SH

MC

F5407 E

valu

atio

n B

oard

B

Friday, July

14, 2000

Title

Siz

eD

ocu

ment N

um

ber

Date

:S

heet

FB

_D

15

FB

_D

14

FB

_D

13

FB

_D

12

FB

_D

11

FB

_D

10

FB

_D

9F

B_D

8

FB

_D

31

FB

_D

30

FB

_D

29

FB

_D

28

FB

_D

27

FB

_D

26

FB

_D

25

FB

_D

24

FB

_D

23

FB

_D

22

FB

_D

21

FB

_D

20

FB

_D

19

FB

_D

18

FB

_D

17

FB

_D

16

FB

_D

7F

B_D

6F

B_D

5F

B_D

4F

B_D

3F

B_D

2F

B_D

1F

B_D

0

FB

_D

[0:3

1]

MA

16

MA

17

MA

11

MA

8

MA

4

MA

14

MA

7

MA

10

MA

9

MA

13

MA

5

MA

15

MA

3

MA

12

MA

18

MA

6

MA

2

FB

_D

[0:3

1]

MA

19

MA

18

MA

8M

A7

MA

6M

A5

MA

4M

A3

MA

2M

A1

MA

9M

A10

MA

11

MA

12

MA

13

MA

14

MA

15

MA

16

MA

17

FB

_D

31

FB

_D

23

FB

_D

30

FB

_D

22

FB

_D

29

FB

_D

21

FB

_D

28

FB

_D

20

FB

_D

16

FB

_D

24

FB

_D

17

FB

_D

25

FB

_D

18

FB

_D

26

FB

_D

19

FB

_D

27

MA

20

+3

.3

+3

.3

+3

.3

+3

.3

+3

.3

+3

.3

C65

0.1

UF

C66

0.1

UF

C67

0.1

UF

C68

1nF

C69

1nF

C70

1nF

C71

1nF

C72

1nF

C73

1nF

C74

1nF

C75

1nF

C76

1nF

RP

21

4x

4.7

K

11

22

33

44

55

66

77

88

RP

22

4x

4.7

K

11

22

33

44

55

66

77

88

RP

9

4x

4.7

K

11

22

33

44

55

66

77

88

U13

MC

M69F

737T

Q11 n

ot popula

ted a

t assem

bly

NC

643

NC

114

NC

764

VD

D1

4

NC

866

NC

216

GN

D1

5

NC

338

VD

D2

11

NC

439

GN

D2

10

NC

542

VD

D3

15

SA

037

VD

D4

20

GN

D3

17

VD

D5

27

GN

D4

21

VD

D6

41

SA

136

VD

D7

54

GN

D5

26

VD

D8

61

GN

D6

40

VD

D9

65

QA

863

VD

D10

70

GN

D7

55

VD

D11

77

GN

D8

60

VD

D12

91

SA

232

GN

D9

67

GN

D10

71

SA

333

GN

D11

76

GN

D12

90

QB

17

80

SA

434

SA

535

QA

762

SA

644

SA

745

QC

26

13

SA

846

SA

947

QA

659

SA

10

48

SA

11

49

QB

16

79

SA

12

50

SA

13

81

QA

558

SA

14

82

SA

15

99

QD

35

30

SA

16

100

AD

SP

*84

QA

457

QB

15

78

QA

356

QC

25

12

QA

253

QB

14

75

QA

152

QD

34

29

QA

051

QB

13

74

QC

24

9

QB

12

73

QD

33

28

QB

11

72

QC

23

8

QB

10

69

QD

32

25

QB

968

QC

22

7

QD

31

24

QC

21

6

QD

30

23

QC

20

3

QD

29

22

QC

19

2

QD

28

19

QC

18

1

QD

27

18

AD

V*

83

AD

SC

85

K89

G*

86

SW

*87

SG

W*

88

SB

D*

96

SB

C*

95

SB

B*

94

SB

A*

93

LB

O*

31

SE

1*

98

SE

2*

97

SE

3*

92

JP

15

16M

Bit

Fla

sh B

oot

1

2

3

U12

Am

29P

L160C

-70

WE

#1

A18

2

A17

3

A7

4

A6

5

A5

6

A4

7

A3

8

A2

9

A1

10

A0

11

CE

#12

Vss

13

OE

#14

DQ

015

DQ

816

DQ

117

DQ

918

DQ

219

DQ

10

20

DQ

321

DQ

11

22

Vcc

23

DQ

424

DQ

12

25

DQ

526

DQ

13

27

DQ

628

DQ

14

29

DQ

730

DQ

15/A

-131

Vss

32

BY

TE

#33

A16

34

A15

35

A14

36

A13

37

A12

38

A11

39

A10

40

A9

41

A8

42

A19

43

NC

44

C62

0.1

UF

C63

0.1

UF

C64

0.1

UF

FB

_D

[0:3

1]

MA

[0:2

0]

R/-

W

-CS

0

-OE

MA

[0:2

0]

BC

LK

_S

RA

M

-BW

E2

-BW

E0

-BW

E1

-BW

E3

-CS

2

FB

_D

[0:3

1]

PU

_C

SP

CI

PU

_R

DP

CI





F

ree

sca

le S

em

ico

nd

uc

tor,

I


c..

.

AB

CD

E

SP

S S

ES

G C

old

Fire

Gro

upM

DEFAULT SETTING - FOR JUMPERS 25 &

29 SHOULD BE INSTALLED.

DEFAULT

SETTING -

JUMPER 16

SHOULD BE

INSTALLED

ACROSS

PINS 1&2.

NOTE - Ensure the clock trace to the PCI controller is 2.5

inches longer than the clock trace to the PCI connector.

PCI configued for max. 7.5W power.

DEFAULT SETTING -

JUMPER 27 SHOULD BE

INSTALLED ACROSS

PINS 1&2.

DEFAULT SETTING -

JUMPER 30 SHOULD

BE INSTALLED

ACROSS PINS 1&2.

NO

TE

: +12V

is o

nly

ava

ilable

when the

eva

luatio

n b

oard

is p

ow

ere

d fro

m a

PC

PS

U v

ia the P

C p

ow

er co

nnect

or.

MC

F5

40

7 P

CI

Inte

rfa

ce

MC

F5

40

7 E

va

lua

tio

n B

oa

rd

C

6F

rid

ay,

Ju

ly 1

4,

20

00

Title

Siz

eD

ocu

me

nt

Nu

mb

er

Da

te:

Sh

ee

to

f

AD

[0:3

1]

FB_D20

MA

12

AD

25

AD

12

AD

11

AD

17

AD

15

FB_D2

MA6

AD

27

AD27AD4

AD29

AD

5

AD

15

AD

7

AD

16

MA8

AD30

FB_D6

FB_D12

FB

_D

31

FB

_D

27

FB

_D

24

AD

13

FB_D14

FB_D17

FB

_D

22

MA5

MA

14

AD

14

AD

9

AD

1

AD

3

AD

16

FB_D19

FB

_D

28

AD

13

AD

9

FB_D1

FB_D11

MA

1

MA

13

AD3

AD

8

MA4

MA

10

MA

11

AD5

AD

4

AD

19

AD

21

AD

10

AD

20

FB_D4FB_D5

FB

_D

25

AD

14

AD

11

FB_D16

FB

_D

23

MA7

MA2

AD0

AD

20

AD

28

FB_D8

FB

_D

29

MA

9

AD

30

AD

8

AD

22

AD6

AD

21

FB_D0

FB_D10

MA3

AD7

AD

26

AD1

AD28

AD

0

AD

22

FB_D3

MA

0

AD

10

AD

30

AD2

AD

29

AD

24

FB_D15

AD

31

AD25

AD

6

AD

2

AD26

AD

12

AD

18

FB_D7

FB

_D

30

AD

23

AD

17

AD

18

FB_D9

FB_D13

FB_D18

FB

_D

26

FB

_D

21

AD

23

AD

31

AD31

AD

19

AD24

AD

[0:3

1]

AD

[0:3

1]

+3

.3

+3

.3

+3

.3

+5

+3

.3

+3

.3

-12

+3

.3

+3

.3

+1

2

+3

.3

+3

.3

+3

.3

+3

.3

+5

+3

.3

+3

.3

+3

.3

+3

.3

RP

35

4x 4

.7K

11

22

33

44

55

66

77

88

RP

36

4x 4

.7K

11

22

33

44

55

66

77

88

U1

7

An

ch

or

AN

30

42

Q

VDD11

ADR[8]2

ADR[7]3

ADR[6]4

ADR[5]5

ADR[4]6

ADR[3]7

ADR[2]8

VSS19

IRQ_IN11

IRQ_OUT12

VSS213

ALE10

VDD214

RSTOUTD15

RSTOUTD16

RSTOUT17

VSS318

SELECT19

SDA20

SCL21

TEST_MODE22

INTA23

RST24

CLK25

VSSP126

VDDP127

GNT28

REQ29

AD[31]30

AD[30]31

VSSP233

VDDP234

AD[28]35

AD[27]36

AD[26]37

AD[25]38

AD[24]39

VDDP340

VS

SP

34

1

C/B

E[3

]4

2

IDS

EL

43

AD

[23

]4

4

AD

[22

]4

5

NC

14

6

AD

[21

]4

7

AD

[20

]4

8

AD

[19

]4

9

VS

SP

45

0

VD

DP

45

1

AD

[18

]5

2

AD

[17

]5

3

AD

[16

]5

4

C/B

E[2

]5

5

NC

25

6

FR

AM

E5

7

IRD

Y5

8

TR

DY

59

VS

SP

56

0

VD

DP

56

1

DE

VS

EL

62

ST

OP

63

PE

RR

64

NC

36

5

SE

RR

66

PA

R6

7

C/B

E[1

]6

8

AD

[15

]6

9

VS

SP

67

0

VD

DP

67

1

AD

[14

]7

2

AD

[13

]7

3

AD

[12

]7

4

AD

[11

]7

5

AD

[10

]7

6

AD

[9]

77

AD

[8]

78

NC

47

9

VS

SP

78

0

VDDP781

C/BE[0]82

AD[7]83

AD[6]84

AD[5]85

AD[4]86

VSSP887

VDDP888

AD[3]89

AD[2]90

AD[1]91

AD[0]92

VSS493

VDD394

DQ[0]95

DQ[1]96

DQ[2]97

DQ[3]98

DQ[4]99

DQ[5]100

DQ[6]101

VSS5102

VDD4103

DQ[7]104

DQ[8]105

DQ[9]106

DQ[10]107

DQ[11]108

DQ[12]109

DQ[13]110

VSS6111

VDD5112

DQ[14]113

DQ[15]114

DQ[16]115

DQ[17]116

DQ[18]117

DQ[19]118

DQ[20]119

VSS7120

AD[29]32

VD

D6

12

1D

Q[2

1]

12

2D

Q[2

2]

12

3D

Q[2

3]

12

4D

Q[2

4]

12

5D

Q[2

5]

12

6D

Q[2

6]

12

7D

Q[2

7]

12

8D

Q[2

8]

12

9V

SS

81

30

VD

D7

13

1D

Q[2

9]

13

2D

Q[3

0]

13

3D

Q[3

1]

13

4V

SS

91

35

BLA

ST

13

6R

EA

D1

37

WR

ITE

13

8R

DY

_IN

13

9R

DY

_IN

14

0R

DY

_O

UT

14

1P

CL

KO

UT

01

42

PC

LK

OU

T1

14

3P

CL

KO

UT

21

44

VS

S1

01

45

CLK

IN1

46

VS

S1

11

47

VD

D8

14

8B

E[3

]1

49

BE

[2]

15

0B

E[1

]1

51

BE

[0]

15

2S

TR

OB

E1

53

AD

R[1

4]

15

4A

DR

[13

]1

55

AD

R[1

2]

15

6A

DR

[11

]1

57

AD

R[1

0]

15

8A

DR

[9]

15

9V

SS

12

16

0

J3U

niv

ers

al 3

2-b

it P

CI

Co

nn

ecto

r

-12

VB

1

TC

KB

2

GN

DB

3

TD

OB

4

+5

VB

5

+5

VB

6

INT

B#

B7

INT

D#

B8

PR

SN

T1

#B

9

RE

SE

RV

ED

B1

0

PR

SN

T2

#B

11

RE

SE

RV

ED

B1

4

GN

DB

15

CL

KB

16

GN

DB

17

RE

Q#

B1

8

+V

i/o

B1

9

AD

31

B2

0

AD

29

B2

1

GN

DB

22

AD

27

B2

3

AD

25

B2

4

+3

.3V

B2

5

C/B

E3

#B

26

AD

23

B2

7

GN

DB

28

AD

21

B2

9

AD

19

B3

0

+3

.3V

B3

1

AD

17

B3

2

C/B

E2

#B

33

GN

DB

34

IRD

Y#

B3

5

+3

.3V

B3

6

DE

VS

EL

#B

37

GN

DB

38

LO

CK

#B

39

PE

RR

#B

40

+3

.3V

B4

1

SE

RR

#B

42

+3

.3V

B4

3

C/B

E1

#B

44

AD

14

B4

5

GN

DB

46

AD

12

B4

7

AD

10

B4

8

GN

DB

49

AD

8B

52

AD

7B

53

+3

.3V

B5

4

AD

5B

55

AD

3B

56

GN

DB

57

AD

1B

58

+V

i/o

B5

9

AC

K6

4#

B6

0

+5

VB

61

+5

VB

62

TR

ST

#A

1

+1

2V

A2

TM

SA

3

TD

IA

4

+5

VA

5

INT

A#

A6

INT

C#

A7

+5

VA

8

RE

SE

RV

ED

A9

+V

i/o

A1

0

RE

SE

RV

ED

A1

1

RE

SE

RV

ED

A1

4

RS

T#

A1

5

+V

i/o

A1

6

GN

T#

A1

7

GN

DA

18

RE

SE

RV

ED

A1

9

AD

30

A2

0

+3

.3V

A2

1

AD

28

A2

2

AD

26

A2

3

GN

DA

24

AD

24

A2

5

IDS

EL

A2

6

+3

.3V

A2

7

AD

22

A2

8

AD

20

A2

9

GN

DA

30

AD

18

A3

1

AD

16

A3

2

+3

.3V

A3

3

FR

AM

E#

A3

4

GN

DA

35

TR

DY

#A

36

GN

DA

37

ST

OP

#A

38

+3

.3V

A3

9

SD

ON

EA

40

SB

O#

A4

1

GN

DA

42

PA

RA

43

AD

15

A4

4

+3

.3V

A4

5

AD

13

A4

6

AD

11

A4

7

GN

DA

48

AD

9A

49

C/B

E0

#A

52

+3

.3V

A5

3

AD

6A

54

AD

4A

55

GN

DA

56

AD

2A

57

AD

0A

58

+V

i/o

A5

9

RE

Q6

4#

A6

0

+5

VA

61

+5

VA

62

C8

11

0n

F

JP2

5S

CL

12

JP2

9S

DA

12

JP3

0

ST

RO

BE

1

2

3

RP

37

4x 4

.7K

11

22

33

44

55

66

77

88

RP

38

4x 4

.7K

11

22

33

44

55

66

77

88

U1

6

X2

4C

04

S8

-1

.8 A0

1A

12

A2

3S

CL

6W

P7

SD

A5

VC

C8

GN

D4

JP1

6

WR

ITE

PR

OT

EC

T

1

2

3

RP

23

4 x

22

11

22

33

44

55

66

77

88

R1

24

.7K

RP

33

4x 4

.7K

11

22

33

44

55

66

77

88

U3

0

33M

Hz

NC

1

GN

D7

CL

K8

VC

C1

4

C7

90.1

UF

U3

1

MP

C9

05

D

XT

AL

_O

UT

1

En

ab

le2

2

GN

D1

3

BC

LK

04

VD

D1

5

BC

LK

16

GN

D2

7

BC

LK

28

VD

D2

9B

CLK

31

0G

ND

31

1B

CLK

41

2V

DD

31

3B

CLK

51

4E

na

ble

11

5X

TA

L_IN

16

C8

00.1

UF

JP2

7

PC

I C

S

1

2

3

R1

61

0K

R1

71

0K

RE

Q#

GN

T#

-IR

Q1

-CF

_R

ST

I

-IR

Q5

-GN

T-R

EQ

MA

[0:2

0]

SIZ

0S

IZ1

BC

LK

_P

CI

-TA

R/-

WP

U_

RD

PC

I

PU

_C

SP

CI

-A3

1

-CS

1

-TS

FB

_D

[0:3

1]





F

ree

sca

le S

em

ico

nd

uc

tor,

I


c..

.

AB

CD

E

HARD_RESET

Ethernet ISA PLD

Debounced IRQ7 Signal

SP

S S

ES

G C

old

Fire

Gro

up

M

MC

F5407 P

LD

MC

F5407 E

valu

atio

n B

oard

B

710

Friday, July

14, 2000

Title

Siz

eD

ocu

ment N

um

ber

Date

:S

heet

of

+5

+3

.3+

5+

3.3

+3

.3

+5

+3

.3

+1

.8

+3

.3

+3

.3

+3

.3S

1

KS

11R

23C

QD

RE

SE

T

J4

1 2 3 4 5 6 7 8

R10

270

C87

1nF

RP

25

4x

4.7

K

11

22

33

44

55

66

77

88

S2

KS

11R

22C

QD

U18

ispLS

I2032V

-100LJ S

MT

socket

I/O

31

10

I/O

015

I/O

30

9I/O

116

I/O

29

8I/O

217

I/O

28

7I/O

318

I/O

27

6I/O

419

I/O

26

5I/O

520

I/O

25

4I/O

621

I/O

24

3I/O

722

I/O

23

44

I/O

825

I/O

22

43

I/O

926

I/O

21

42

I/O

10

27

I/O

20

41

I/O

11

28

I/O

19

40

I/O

12

29

I/O

18

39

I/O

13

30

I/O

17

38

I/O

14

31

I/O

16

37

I/O

15

32

TD

O*/

IN1

24

TD

I*/IN

014

ispE

N*/

NC

13

TM

S*/

NC

36

TC

K*/

Y2

33

Y0

11

RE

SE

T*/

Y1

35

GO

E0

2

VC

C0

12

VC

C1

34

GN

D0

1

GN

D1

23

R8

1K

R9

3K

U19

MA

X6355LS

UT

-T

RS

T1

GN

D2

MR

3V

cc3

4R

ST

IN5

Vcc

56

D13

RE

D L

ED

R11

270

C85

1nF

C82

0.1

UF

U20

TLC

7733ID

VC

C8

SE

NS

E7

RE

SE

T5

RE

SE

T6

CO

NT

RO

L1

GN

D4

CT

3

RE

SIN

2

C83

0.1

UF

C84

1nF

C86

0.1

UF

RP

24

4x4

.7K

11

22

33

44

55

66

77

88

D12

RE

D LE

D

C88

10nF

R18

10K

-IO

WR

/-W

EC

LK

BA

LE

SA

0-C

S1

-CS

2-C

S3

-CS

_F

PC

IBD

GN

T#

-ET

H_IR

Q3

-IR

Q3

ET

H_

RE

SE

TR

EQ

#-H

IZ

SIZ

1-I

O16

-CS

0-I

OC

HR

DY

MA

0-B

D_C

S3

-CF

_R

ST

I-G

NT

-BD

M_

RS

TI

SIZ

0-A

31

-RE

Q-T

AM

A16

A31

-IO

R

BC

LK

_F

PLA

PU

_IP

3

SC

LK

MO

DE

SD

I

SD

O

-IR

Q7





Freescale Semiconductor, I

Fre

esc

ale

Se

mic

on

du

cto

r, I

nc

.

Fo

r M

ore

In

form

ati

on

On

Th

is P

rod

uc

t,

Go

to

: w

ww

.fre

esc

ale

.co

m

nc...

A A

B B

C C

D D

E E

4 3 2 1

DEBUGGER PORT

100mil header

2x13pin

JUMPER 17 SHOULD BE


1&2 DURING ASSEMBLY

All resistors are

0805 body size

except R3 which

is 1206.

All caps less

than 1uF are

0805 body size.

Bus Clock Driver

Socketed CF

Osc.

BDM Header

3.3V Regulator

5.0V Regulator

1.8V Regulator

JUMPER 20 SHOULD

BE INSTALLED

ACROSS PINS 1&2

FOR DEFAULT

OPERATION AND

PINS 2&3 ARE

RESERVED.

JUMPER 18 SHOULD BE

INSTALLED ACROSS PINS 1&2

FOR A 5407 CPU AND PINS 2&3

FOR ALTERNATE CPU WITH JP19

FITTED.

JUMPER 19 SHOULD ONLY BE

FITTED FOR ALTERNATE

CLOCKING IN CONJUNCTION WITH

JP18.

NOTE: Diodes prevent excessive

difference between 3.3V & 1.8V

rails, at power up.

NOTE: Schottky Diode prevents excessive

difference between 3.3V & 1.8V

rails, at power down.

IMP

OR

TA

NT

NO

TE

: O

NLY

a 3

.3V

BD

M d

ebuggin

gca

ble

ca

n b

e u

sed

with

th

e M

CF

5407 p

roce

ssor.

JUMPER 26 INSTALLED ACROSS PINS

1&2 FOR DEFAULT POWER, PINS 2&3

RESERVED FOR ALTERNATE POWER.

SP

S S

ES

G C

old

Fire

Gro

upM

JP12 SHOULD BE INSTALLED

DURING ASSEMBLY.

Augat 25V

-02

2-way Bare Wire

Power Connector

NOTE: Mating connector for

J7 is AMP1-480303-0.

Power Jack Connector

- 2.1mm dia.

MC

F5407 P

OW

ER

MC

F5407 E

valu

atio

n B

oar

d

B

81

0F

riday,

July

14, 2000

Title

Siz

eD

ocu

ment N

um

ber

Date

:S

heet

of

PS

TD

DA

TA

2P

ST

DD

AT

A0

PS

TD

DA

TA

3P

ST

DD

AT

A5

PS

TD

DA

TA

7

PS

TD

DA

TA

1

BC

LK

_S

DR

AM

1

BC

LK

_S

DR

AM

0

BC

LK

_S

DR

AM

2

BC

LK

_S

DR

AM

3

PS

TD

DA

TA

6P

ST

DD

AT

A4

+3

.3

+3

.3

+3

.3

+1

.8

+3

.3

+1

.8

IVC

C

+5

+3

.3

+3

.3+

5

+3

.3+

1.8

+3

.3+

1.8

+1

.8

+3

.3+

1.8

+3

.3

+3

.3

-12

+1

2

JP12

12

RP

32

4x

22

11

22

33

44

55

66

77

88

C52

0.1

uF

JP17

1

2

3

U24

CD

C351D

B

GN

D1

1

Y1

23

GN

D2

12

Y2

21

GN

D3

13

Y3

19

GN

D4

17

Y4

18

GN

D5

20

Y5

16

GN

D6

24

Y6

14

VC

C1

3Y

711

Y8

9

Y9

4

Y10

2

0E

5

A6

P0

7

P1

8

VC

C2

10

VC

C3

15

VC

C4

22

C97

220uF

C77

1nF

C96

0.1

UF

JP18

CLO

CK

I/P

1

2

3

RP

27

4x

22

11

22

33

44

55

66

77

88

C95

10

0u

F T

AN

T.

U21

OS

C 5

0 M

HZ

NC

1

GN

D7

CLK

8

VC

C14

C89

0.1

UF

U22

LT

10

86

CM

VIN

3

ADJ1

VO

UT

2

C100

1000uF

L3

25uH

C90

0.1

UF

R14

120

C91

1nF

C99

0.1

UF

D14

MR

A4

00

3T

3

R15

56

D20

MB

RS

34

0T

3

21

P6

Sw

itchcr

aft R

AP

C712123

D15 M

RA

40

03

T3

J5

1 3 5 7 911

13

15

17

19

21

23

25

2 4 6 8 10

12

14

16

18

20

22

24

26

C92

1nF

J7

AM

P350210-11 2 3

L4

25uH

D16

MB

RS

34

0T

3

21

C93

1nF

C101

220uF

F1

5A

Fast

blo

w.

U23

LM

2596S

-3.3

VIN

1V

OU

T2

~O

N/O

FF

5

GND3

FB

4

TAB6

RP

28

4x

22

11

22

33

44

55

66

77

88

JP26

1

2

3

JP20

VC

C_C

OR

E

1

2

3

C103

0.1

UF

JP19

12

R23

4K

7

U25

LM

2596S

-5

VIN

1V

OU

T2

~O

N/O

FF

5

GND3

FB

4

TAB6

D21

MB

RS

34

0T

3

21

RP

29

4x

22

11

22

33

44

55

66

77

88

R13

10K

P3

1 2

D19

MB

RS

34

0T

3

21

C98

330uF

C94

10

uF

TA

NT

.

D18

MB

RS

34

0T

3

21

CLK

IN

BC

LK

DR

V_IP

BC

LK

O

BC

LK

DR

V_IP

BC

LK

_S

DR

AM

[0:3

]

BC

LK

_S

RA

M

BC

LK

_P

CI

BC

LK

_F

PLA

CLK

IN

ED

GE

SE

L

-SC

AS

SC

KE

-R_S

CA

SR

_S

CK

E

PU

_IP

3

-BD

M_

RS

TI

-BK

PT

_T

MS

DS

CL

K_

TR

ST

DS

DI_

TD

ID

SD

O_

TD

O

PS

TC

LK

-TA

PS

TD

DA

TA

[0:3

]

PS

TD

DA

TA

[4:7

]



F

ree

sca

le S

em

ico

nd

uc

tor,

I


c..

.

AB

CD

E

RS232 Driver

AUXILARY PORT

TERMINAL PORT

RS232 Driver

REAL-TIME CLOCK.

NO

TE

: T

he

I2

C/M

bu

s o

n th

e M

CF

54

07

will

ON

LY

sup

po

rt 3

.3V

de

vice

s.

NO

TE

: P

lace

TP

9 &

TP

10

at o

pp

osi

ted

iag

on

al c

orn

ers

of th

e P

CB

, to

att

ach

'sco

pe

gro

un

d le

ad

s.

NOT POPULATED AT ASSEMBLY.

NOT POPULATED AT ASSEMBLY.

DEFAULT SETTING FOR JP28 SHOULD BE

PINS 1&2 FOR NORMAL/BDM MODE AND PINS

2&3 FOR NORMAL/JTAG MODE.

SP

S S

ES

G C

old

Fire

Gro

up

M

NO

TE

: U

se

th

e n

etli

st n

am

es

to la

be

le

ach

of th

e te

st p

oin

ts o

n th

esi

lksc

ree

n.

Se

ria

l In

terf

aces, R

eal-T

ime C

lock &

Test poin

ts.

MC

F5407 E

valu

atio

n B

oard

.

B

10

Friday, July

14, 2000

Title

Siz

eD

ocu

ment N

um

ber

Date

:S

heet

+5

+5

VB

AT

VB

AT

+3

.3

+5

Y1

32.7

68K

Hz

P5

5 9 4 8 3 7 2 6 1

U14

M4

1T

11

M

OS

CI

1

OS

CO

2

VB

AT

3

VS

S4

SD

A5

SC

L6

FT

/OU

T7

VC

C8

U29

MC

145406D

W

DI1

14

TX

13

DO

115

DI2

12

RX

12

DO

213

DI3

10

TX

25

DO

311

VC

C16

RX

24

VD

D1

TX

37

RX

36

VS

S8

GN

D9

P4

5 9 4 8 3 7 2 6 1

C124

10

uF

TA

NT

.

C123

10

uF

TA

NT

.

JP

28

BD

M/J

TA

G 3

WA

Y J

UM

PE

R

1

2

3

U28

MC

145407D

W

DI1

15

DO

116

DI2

13

DO

214

DI3

11

DO

312

TX

16

RX

15

TX

28

RX

27

TX

310

RX

39

VC

C19

VD

D17

C2-

3C

2+

1C

1+

20

C1-

18

VS

S4

GN

D2

TP

1 TR

AN

S

1

TP

2 RE

AD

N

1

TP

3 CH

IP S

1

TP

4 CH

IP S

1

TP

5

TR

AN

SF

ER

AC

1

TP

6 AD

DR

E

1

TP

7 BU

S C

L

1

TP

8 MC

F54

1

TP

9 GN

D

1

J6

I2C

Mole

x C

onn. 71565

1 2 3 4

C125

0.1

uF

TP

10

GN

D

1

BT

1 3V

C122

10

uF

TA

NT

.

C121

10

uF

TA

NT

.

TX

D0

RX

D0

-RT

S0

-CT

S0

TX

D1

RX

D1

-RT

S1

-CT

S1

MT

MO

D0

PU

_M

TM

OD

0

PD

_M

TM

OD

0

SC

LS

DA

-TS

R/-

W

-CS

0

-CS

1

-TA

-AS

BC

LK

O

CLK

IN





4 3 2 1

1.1

10

Rev

F

ree

sca

le S

em

ico

nd

uc

tor,

I


c..

.

A A

B B

C C

D D

E E

4 3 2 1

DEFAULT SETTING - JUMPERS

21,22,23 & 24 SHOULD BE


1&2.

SDRAM

SDRAM MUX

SP

S S

ES

G C

old

Fire

Gro

up

M

MC

F5407 S

DR

AM

MC

F5407 E

valu

atio

n B

oard

B

9F

riday, July

14, 2000

Title

Siz

eD

ocu

ment N

um

ber

Date

:S

heet

of

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

D[0

:31]

A20

A21

A22

A23

A24

A25

A19

MA

14

MA

15

MA

9

MA

13

MA

11

MA

12

MA

17

MA

10

BC

LK

_S

DR

AM

0B

CLK

_S

DR

AM

1B

CLK

_S

DR

AM

2B

CLK

_S

DR

AM

3

PP

1

PP

3

PP

0

PP

2

A18

A26

A27

+3

.3

+3

.3

+3

.3

+3

.3

+3

.3

+3

.3

C108

0.1

UF

U26

PC

10

0 U

nb

uff

ere

d 1

Bank

x 64 D

IMM

8M

or

16M

, su

pport

for

up to 5

12M

CB

021

VS

S1

1

DU

131

CB

122

DU

244

VD

D1

6

DU

348

VS

S2

12

DQ

M7

131

VS

S3

23

CB

252

VD

D2

18

CB

353

VS

S4

32

VR

EF

162

A0

33

CK

E1

63

CB

4105

VS

S5

43

CB

5106

CLK

279

VD

D3

26

VS

S6

54

DQ

M6

130

NC

8109

CLK

1125

A11

123

VS

S7

64

CB

6136

VD

D4

40

CB

7137

A12

126

VS

S8

68

A13

132

VR

EF

2146

D9

13

VS

S9

78

NC

9134

VD

D5

41

NC

10

135

VS

S10

85

DQ

M5

113

VS

S11

96

NC

11

145

VD

D6

49

VS

S12

107

NC

12

147

A1

117

VS

S13

116

VD

D7

59

VS

S14

127

DQ

M4

112

VS

S15

138

VD

D8

73

VS

S16

148

D63

161

VS

S17

152

VD

D9

84

VS

S18

162

DQ

M3

47

VD

D10

90

A2

34

VD

D11

102

DQ

M2

46

VD

D12

110

D8

11

VD

D13

124

DQ

M1

29

VD

D14

133

A3

118

VD

D15

143

DQ

M0

28

VD

D16

157

D62

160

VD

D17

168

A4

35

D7

10

A5

119

D61

159

A6

36

D6

9

A7

120

D60

158

A8

37

D5

8

A9

121

D59

156

A10_A

P38

D4

7

BA

0122

D58

155

D3

5

D57

154

D2

4

D56

153

D1

3

D55

151

D0

2

D54

150

D53

149

D52

144

D51

142

D50

141

D49

140

D48

139

D47

104

D46

103

D45

101

D44

100

D43

99

D42

98

D41

97

D40

95

D39

94

D38

93

D37

92

D36

91

D35

89

D34

88

D33

87

D32

86

D31

77

D30

76

D29

75

D28

74

D27

72

D26

71

D25

70

D24

69

D23

67

D22

66

D21

65

D20

60

D19

58

D18

57

D17

56

D16

55

D15

20

D14

19

D13

17

D12

16

D11

15

D10

14

CK

E0

128

RA

S*

115

CA

S*

111

WE

*27

SO

2*

45

SO

0*

30

SD

A82

SC

L83

SA

2167

SA

1166

SA

0165

CLK

042

NC

024

NC

125

BA

139

NC

250

NC

351

NC

461

NC

580

NC

681

NC

7108

SO

1*

114

SO

3*

129

NC

13

164

CLK

3163

JP

21

1

2

3

JP

22

1

2

3

JP

23

1

2

3

RP

31

4x

4.7

K

11

22

33

44

55

66

77

88

JP

24

1

2

3

U27

ispG

AL22LV

10 S

MT

sock

et

TC

LK

1

I/C

LK

2

I03

I14

I25

I36

I47

MO

DE

8

I59

I610

I711

I812

I913

GN

D14

VC

C28

I10

16

I/O

/Q0

17

I/O

/Q1

18

I/O

/Q2

19

I/O

/Q3

20

I/O

/Q4

21

I/O

/Q5

23

I/O

/Q6

24

I/O

/Q7

25

I/O

/Q8

26

I/O

/Q9

27

TD

I15

TD

O22

C109

0.1

UF

C110

0.1

UF

C111

1nF

C112

1nF

C113

1nF

C114

1nF

C115

1nF

C116

1nF

C118

1nF

C119

1nF

C120

1nF

C106

0.1

UF

C105

0.1

UF

C104

0.1

UF

C107

0.1

UF

RP

30

4x

4.7

K

11

22

33

44

55

66

77

88

PP

[0:7

]A

[0:3

1]

MA

[0:2

0]

SC

LK

SD

I

MO

DE

SD

O

D[0

:31]

BC

LK

_S

DR

AM

[0:3

]

R_S

CK

E

-R_S

CA

S-R

_S

RA

S-R

_D

RA

MW

-R_C

AS

0/D

QM

0-R

_C

AS

1/D

QM

1-R

_C

AS

2/D

QM

2-R

_C

AS

3/D

QM

3

-R_R

AS

1/S

Q2

-R_R

AS

0/S

Q0

SD

AS

CL





F

ree

sca

le S

em

ico

nd

uc

tor,

I


c..

.





apps docs:ColdFire:5407:Eval Board UM NEW:5407_F_Errata.fm 8/11/00

F

ree

sca

le S

em

ico

nd

uc

tor,

I


c..

.

Appendix FErrata

1. The descriptions of the JP29 and JP25 on the back of the silkscreen table are wrong. Table 1-4 lists the correct functions.

2. The descriptions of the JP16 functionality on the back of the silkscreen are wrong. Table 1-2 lists the correct functions.

3. The pin numbering for U28, U29, and U24 on the silkscreen is reversed. Pin ll on the silkscreen should be pin 1, pin 20 should be pin 10, etc..

Appendix F. Errata F-1




F

ree

sca

le S

em

ico

nd

uc

tor,

I


c..

.

A-2 BookTitle




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