Jeff Shelton – 3 February 2015 = 1 ⋅ 2 + 1 ⋅ 2 + 1 ⋅2 + 1 ⋅ 2 = 1 + 2 ⋅ 1 + 2 ⋅ 1 +2 ⋅ 1 + 2 1
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Transcript
Jeff Shelton – 3 February 2015
𝑦 = 𝐵1 ⋅ 𝐵2 + 𝐵1 ⋅ 𝐵2 + 𝐵1 ⋅ 𝐵2 + 𝐵1 ⋅ 𝐵2
𝑦 = 𝐵1 + 𝐵2 ⋅ 𝐵1 + 𝐵2 ⋅ 𝐵1 + 𝐵2 ⋅ 𝐵1 + 𝐵2
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Jeff Shelton – 3 February 2015 3
Controls
Sensors
Actuators
Environment
Mechatronic Device
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Controls
Sensors
Actuators
Environment
Mechatronic Device
How might we best develop appropriate logic?
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Jeff Shelton – 3 February 2015
Drive forward
Flippers rotate
Drive forward with flippers
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•
•
•
•
•
•
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Imperative Declarative
?
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•
•
•
•
•
•
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Jeff Shelton – 3 February 2015
⟶
11
1
value = 0
last_CLK = 0 value = 0
0
Start
CLK⋅/last_CLK? last_CLK = 0 /CLK ⋅ last_CLK?
value?
0
value = 1 0 1
1
last_CLK = 0; value = 0; while 1 % put into infinite loop input CLK; if CLK == 1 && last_CLK == 0 if value = 0 value = 1; else value = 0; endif last_CLK = 1; elseif CLK == 0 && last_CLK == 1 last_CLK = 0; endif endwhile
CLK
Jeff Shelton – 3 February 2015
⟶
12
1
value = 0
last_CLK = 0 value = 0
0
Start
CLK⋅/last_CLK? last_CLK = 0 /CLK ⋅ last_CLK?
value?
0
value = 1 0 1
1
last_CLK = 0; value = 0; while 1 % put into infinite loop input CLK; if CLK == 1 && last_CLK == 0 if value = 0 value = 1; else value = 0; endif last_CLK = 1; elseif CLK == 0 && last_CLK == 1 last_CLK = 0; endif endwhile
CLK
Largely Procedural Information
Jeff Shelton – 3 February 2015
S0 S1
0 1
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This model tells us nothing about when transitions should occur, nor how the transition is to be accomplished.
Largely Declarative Information
Jeff Shelton – 3 February 2015
•
•
•
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Jeff Shelton – 3 February 2015
•
•
•
•
18
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•
•
•
•
19
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Q
Q
S
R
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S Q
Q R
EN CLK
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22
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CLOCK (evenly spaced)
HIGH LEVEL Enabled
ENABLE (may be unevenly spaced)
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CLOCK (evenly spaced)
ENABLE (may be unevenly spaced)
LOW LEVEL Enabled
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CLOCK (evenly spaced)
ENABLE (may be unevenly spaced)
Falling Transition after Rising Transition
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CLOCK (evenly spaced)
ENABLE (may be unevenly spaced)
LOW to HIGH transition (Rising Edge)
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CLOCK (evenly spaced)
ENABLE (may be unevenly spaced)
HIGH to LOW transition (Falling Edge)
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Jeff Shelton – 3 February 2015
Input
Clock
29
Tsu Th
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30
R
S
Q
Q’
R S Q Q’
0 0
0 1
1 0
1 1
Q Q’
1 0
0 1 not allowed
Jeff Shelton – 3 February 2015
R S Q Q’
0 0
0 1
1 0
1 1
R S Q Q*
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Q Q’ 1 0 0 1
not allowed
0 1
1 1
0 0
X X
next state
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Jeff Shelton – 3 February 2015
R SS-R
Latch 00 01 11 10
0Q
1
S0 S1
0 1
S=1, R=0
S=0, R=1
S=0 R=0
S=0 R=1
S=0 R=0
S=1 R=0
1
0 1 X
X
0
0 1 𝑄∗ = 𝑆 + 𝑄 ⋅ 𝑅
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Q
Q
S
R
R S /R /S Q Q’
0 0 1 1
0 1 1 0
1 0 0 1
1 1 0 0
Q Q’ 1 0 0 1
not allowed
74279 Quad S-R Latch
S Q
Q R R
S
Q
Q
S
R
+5V
+5V
Switch Debouncing Circuit
VQ
t
VR'
t
R
S
Q
Q’
Jeff Shelton – 3 February 2015
0 0
0
1
1
1
0 1
J KJ-KLatch 00 01 11 10
0Q
1
J
K
Q
/Q
J K Q Q*
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
Q
0
1
toggle
Q*Q J Q K34
J Q
Q K
Jeff Shelton – 3 February 2015
D Q Q* /Q*
0 X
1 X
1 0 1
0
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D Q
Q
D
Q
Q
NAND Gate Implementation
NOR Gate Implementation
D
Q
Q
Restricted input not possible
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J
K
CLK
Q
Q
Restricted state permits toggling action
Texas Instruments SN7475 4-Bit Bi-Stable Latches
37
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S Q
EN
R
S
R
Q
Q
EN
P S
CLK
R /P
Master Slave
Q
S
R
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•
•
39
CLOCK
S
R
Q
Glitch
Erroneous State
S Q
EN
R
S
R
Q
Q
EN
P S
CLK
R /P
Master Slave
Q
S
R
Jeff Shelton – 3 February 2015
CLK
J
K
Q
Q’
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J Q
Q CLK
K
Postponed Output
Texas Instruments SN74LS107 Dual J-K Flip-Flops with Clear
Jeff Shelton – 3 February 2015
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J Q
Q
CLK
K
𝐽
𝐾
CLK
𝑄
Q
D
EN
Q
Q
J K CL Q*
0 0 Q
0 1 0
1 0 1
1 1 /Q
X X 0 Q
X X 1 Q
74109 Dual J-K' Positive Edge-Triggered Flip Flop
Dynamic Input Indicator
Jeff Shelton – 3 February 2015
CLK
D
Q
Q’
D CLK Q Q*
0
1
0
1
X X 0
1 Q Q Q Q
𝑄∗ = 𝐷
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D Q
Q CLK
Reset Latch
Set Latch
Output Latch
Jeff Shelton – 3 February 2015
T
Q
Q’
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Quad S-R Latch
Dual J-K Flip-Flop with CLR
Dual D Flip-Flop with PRE
CLR
Hex D Flip-Flop CLR
R
S
Q
Q
S-R Latch
J
K
Q
Q
J-K Latch
J
K
Q
Q
Edge-Triggered J-K Flip-Flop
Edge-Triggered D Flip-Flop
D Q
Q
Jeff Shelton – 3 February 2015
J
K
Q
Q D
CLK
D flip-flop implemented by J-K flip-flop
D Q
Q
K
J
J-K flip-flop implemented by D flip-flop
Q Q* R S J K T D
0 0 X 0
0 1 0 1
1 0 1 0
1 1 0 X
X 0
0 1 1 0
X 0
1 0
0 1
1
0
0 1
S-R J-K T D
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•
•
•
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Q
QSET
CLR
D
ASYNC_IN
CLK
SYNC_IN
Synchronous
Logic
Synchronizer
Jeff Shelton – 3 February 2015
Q
QSET
CLR
D
ASYNC_IN
CLK
SYNC_IN
Synchronous
Logic
Synchronizer
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