Jan 06, 2016
Control Power Supply Architecture For
Ride Through In Power Converters Using
Ultracapacitors
A Project Report
Submitted in Partial Fulfilment of
Requirements for the Degree of
Master of Engineering
in
Electrical Engineering
By
Anand Vivek Ravi
Department of Electrical Engineering
Indian Institute of Science
Bangalore - 560 012
India
June 2010
Acknowledgements
I extend a great thanks to Prof. Vinod John for giving me an opportunity to work in the
Power Electronics Group.I would like to express my admiration for him on the various in-
teresting ideas suggested during the course of project. Work under him had always been a
great pleasure and I take this opportunity to acknowledge all the timely help rendered by
him, right from awarding me a very interesting project till the final completion of it. I would
like to acknowledge the confidence and the encouragement provide by him during the final
bottleneck situations, which was a great motivation, helping me complete the work.
I express my humble gratitude to Prof. V. Ramanarayanan, who has been a pillar of support
to all the students in the group. I,having cherished attending his lectures and seminars,
would like to thank him for teaching us to progress on becoming good power electronics
design engineers.
I would like to thank Prof. V. T. Ranganathan for his patient lectures and in making a not so
conspicuous topic into an easily comprehensive one. I would like to thank Prof. G. Narayanan
for providing insights on the various PWM techniques through his course.
I thank my close frinds Venkat, Manoj, Shan, Arun Karuppaswamy,Raju and Tarak for
being supportive and critical of me and for the interesting discussions had with them. I
would also like to thank Vishnu, Prakash and the other students of the batch for their sup-
port. I thank all PhD students of the PEG group Kamalesh Hatua, Amit Jain, Shivaprasad,
Anirban, Dipankar De, Soumitra Das and Binoj Kumar for their help. I would like to thank
Srinath in helping me out on various aspects of the project.
I thank Ms. Silvi Jose, Mr. Paul, Mr. Ravi and members of the department workshop for
their cordial demeanour. I also extend my thanks to Mr D. M. Channegowda and his team
at the department office for their good administrative activities.
I would like to thank Shankar, Anil Adapa and Mr. Krishna of M/s CHIPKRAFT TECH-
i
ii Acknowledgements
NOLOGIES for helping at a very difficult situation, the result of which the project got
completed.
Finally, I would like to thank my parents who have put up with me inspite of my maverick
behaviour and for being by my side in all my failures and success. I would like to thank
my adoring grandparents and my guru shri Anandha Bharathi Ayya for providing me the
mental strength during bleak periods and the God Almighty for having been my best buddy,
for giving me the opportunity to study at this prestigious institute, to work under such an
understanding and a patient guide and finally for providing me a career through this project
along with the completion of the project.
Abstract
High power converters are used in variable speed induction motor drive applications. These
power converters consist of active front end rectifier, a DC link and an inverter feeding the
motor. The power devices employed in this converter are high voltage IGBTs.
The following figure shows a typical block diagram of the inverter fed induction motor drive
system
Figure 0.1: A typical induction motor drive system
The switching action of these devices depends on the gating pulses generated by the gate
drive cards. The voltage and currents on the ac side are sensed through voltage and current
sensing cards respectively to monitor faults and for closed loop control. The power supply
failure of these control cards results in shut down of the entire system.
This project addresses the failure of the control power supply due to voltage sags or blackouts
by providing backup using ultracapacitors for a period of 10secs. The project involved design
and testing of a bi-directional buck-boost converter, design of a stack of ultracapacitor cells
and characterization of the individual cells, design and implementation of the controllers for
closed loop control using Microchips dsPIC30F2023.
iii
Contents
Acknowledgements i
Abstract iii
List of Tables vii
List of Figures viii
Nomenclature x
1 Introduction 1
1.1 Outline of the Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 The Ride-Through System . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2.1 Need for a power converter . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Organisation of the Project Report . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Ultracapacitors - Modelling and Sizing 6
2.1 Construction of Ultracapacitor . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Comparison of Various Energy Sources . . . . . . . . . . . . . . . . . . . . . 8
2.3 Electrical characteristics of Ultracaps . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Design of the Ultracapacitor Stack for the Ride Through System . . . . . . . 9
2.4.1 Number of Ultracapacitor cells . . . . . . . . . . . . . . . . . . . . . . 11
2.4.2 Ultracapacitor voltage management . . . . . . . . . . . . . . . . . . . 12
2.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
iv
Contents v
3 Hardware Design 14
3.1 Power Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1.1 Power Devices Selection . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1.2 Gate Drive Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1.3 Filter Inductor and Capacitor Selection . . . . . . . . . . . . . . . . . 15
3.1.4 Losses in the switches . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1.5 Power Circuit Schematic . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2 Theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3 Controller Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4 Current and Voltage Sensing Circuit . . . . . . . . . . . . . . . . . . . . . . 18
3.4.1 Voltage Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4.2 Current Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4 Controller Design 21
4.1 Principle of Closed Loop Control . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1.1 Control Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2 Buck Converter Control with Resistive Load . . . . . . . . . . . . . . . . . . 24
4.2.1 Inner current loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.2.2 Outer Voltage Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.3 Buck Converter Controller for Charging Ultracapacitors . . . . . . . . . . . . 28
4.3.1 Inner Current Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.3.2 Outer Voltage Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.4 Boost Converter Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5 Experimental Results 33
5.1 Ultracapacitor Characterisation . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.2 Ultracapacitor Voltage Monitoring Circuit . . . . . . . . . . . . . . . . . . . 33
5.3 Closed Loop Control Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.3.1 Buck Converter - Ultracapacitor Charging Test Results . . . . . . . . 35
5.3.1.1 Charging at 1A . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.3.1.2 Charging at 2A . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.3.2 Boost Converter Test Results . . . . . . . . . . . . . . . . . . . . . . 38
5.3.3 Boost Converter test results with ultracapacitor input . . . . . . . . . 42
vi Contents
5.3.3.1 Boost Converter Operation with 25W(23V, 20) load . . . . 42
5.3.3.2 Boost Converter Operation with 50W(23V, 10) load . . . . 42
5.3.4 Integrated Operation of Buck and Boost converter . . . . . . . . . . . 43
5.4 Efficiency of the Power Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.5 Thermal Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6 Conclusions 48
A Schematics and Experimental Setup 50
A.1 Power Circuit Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
A.2 Controller Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
A.3 Ultracapacitor board - Top View . . . . . . . . . . . . . . . . . . . . . . . . 52
A.4 Ultracapacitor board - Side View . . . . . . . . . . . . . . . . . . . . . . . . 53
A.5 Power Circuit Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
A.6 Voltage and Current Sensing Circuit Hardware . . . . . . . . . . . . . . . . . 55
A.7 Controller Circuit Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
References 57
List of Tables
1.1 System Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Comparison between batteries and ultracapacitors . . . . . . . . . . . . . . . 9
2.2 Power consumed by the inverter control cards . . . . . . . . . . . . . . . . . 10
3.1 Inductor Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1 Ultracapacitors Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.2 Efficiency of Power Circuit in Buck mode . . . . . . . . . . . . . . . . . . . . 45
6.1 Ride Through System Results . . . . . . . . . . . . . . . . . . . . . . . . . . 49
vii
List of Figures
0.1 A typical induction motor drive system . . . . . . . . . . . . . . . . . . . . . iii
1.1 Control Power Flow in a Motor Drive . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Block Diagram of the Ride Through System . . . . . . . . . . . . . . . . . . 3
1.3 Need for a Bi-directional Converter . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 construction of double layer capacitor . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Ragones Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4 Discharge Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.5 cell voltage management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 Power circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2 Buck Mode of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3 Boost Mode of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4 Voltage Sensing Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.5 Current sensing Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1 Closed Loop Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.2 Closed Control Loop - Outer Voltage Loop . . . . . . . . . . . . . . . . . . . 22
4.3 Current to Control transfer function i(s)/d(s) . . . . . . . . . . . . . . . . . 25
4.4 inner current loop - Loop gain GH transfer function i(s)/ iref (s) . . . . . . . 25
4.5 Voltage to Current transfer function V(s)/i(s) . . . . . . . . . . . . . . . . . 27
4.6 Outer Voltage Loop - Loop gain GH transfer function V(s)/Vref (s) . . . . . . 27
4.7 Current to Control transfer function - ultracap charging i(s)/d(s) . . . . . . 29
4.8 Current Loop gain GH - ultracap charging i(s)/iref . . . . . . . . . . . . . . 29
viii
List of Figures ix
4.9 Voltage to Control transfer function - ultracap discharging v(s)/d(s) . . . . . 31
4.10 Voltage Loop gain GH - ultracap Discharging V(s)/Vref (s) . . . . . . . . . . 32
5.1 Ultracapacitors Charging Plots . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.2 Ultracapacitors Voltage Management Circuit . . . . . . . . . . . . . . . . . . 35
5.3 Charging of Ultracaps - 1A . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.4 Charging of Ultracaps - 2A . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.5 Boost Converter Constant Voltage Control - 4.7V input, 6V output, 20ohm
load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.6 Boost Converter Constant Voltage Control - Step Increase in Input . . . . . 39
5.7 Boost Converter Constant Voltage Control - Step Decrease in Input . . . . . 39
5.8 Boost Converter Constant Voltage Control - 15V input, 25V output, 20ohm
load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.9 Boost Converter Constant Voltage Control - Step Increase in Voltage . . . . 40
5.10 Boost Converter Constant Voltage Control - Step Decrease in Voltage . . . . 41
5.11 Boost Converter Operation with 25W load . . . . . . . . . . . . . . . . . . . 42
5.12 Boost Converter Operation with 50W load . . . . . . . . . . . . . . . . . . . 43
5.13 Integrated operation - 75W(23V,7) . . . . . . . . . . . . . . . . . . . . . . 43
5.14 Integrated operation - 75W(zoomed view) . . . . . . . . . . . . . . . . . . . 44
5.15 Integrated operation 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.16 Integrated operation 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.17 Thermal Test - Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.18 Thermal Test - Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.19 Thermal Test - IR2110 and HCPL 3101 . . . . . . . . . . . . . . . . . . . . . 47
A.1 Power Circuit Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
A.2 dsPIC Controller Board Schematic . . . . . . . . . . . . . . . . . . . . . . . 51
A.3 Ultracapacitor Hardware - Top View . . . . . . . . . . . . . . . . . . . . . . 52
A.4 Ultracapacitor Hardware - Side View . . . . . . . . . . . . . . . . . . . . . . 53
A.5 Power Circuit Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
A.6 Sensing Circuit Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
A.7 Controller Circuit Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Nomenclature
Symbols : Definitions
P : Maximum load to which the ultracaps are subjected to
Vmax : Maximum Voltage across the Ultracapacitor stack
Vmin : Minimum Voltage across the Ultracapacitor stack
Vnominal : Nominal Voltage across the Ultracapacitor stack
Vcell : Rated Voltage of each Ultracapacitor
Imax : Maximum Current from the supercapacitor stack
Ct : Capacitance of the ultracapacitor stack
: Time constant of the ultacapacitors capacitance and ESR
L : Filter inductor in the power converter
C : Output filter capacitor in the power converter
Irms : RMS current through the switching device
RDSon : On state drain-source resistance of MOSFET
Vav : Average voltage across the body diode of MOSFET
Iav : Average current through the body diode of MOSFET
tr, tf : Rise and fall times of the switching device
Pswon, Pswoff : Turn on and turn off switching power loss
Vg : Input voltage variable used in controller design
v(s) : Very Small perturbation in Output voltage
i(s) : Very Small perturbation in Output current
ev : Error voltage corresponding to difference between reference and fedback voltage
ei : Error voltage corresponding to difference between reference and fedback current
error[n] : Error at nth sampling instant in digital implentation
kp[n] : Proportional controller output at nth sampling instant
x
Nomenclature xi
ki[n] : Integral controller output at nth sampling instant
D : Steady State Duty ratio
d(s) : Small variation perturbation in the duty cycle
Chapter 1
Introduction
The power line disturbances like voltage sags and blackouts affect the continuous process
industries to a great extent, the severity being dependent on the magnitude and duration
of the sag. Faults lasting even less than 0.5s can have dentrimental effects on the produc-
tion. Each industrial equipment reacts to voltage sag in different ways [2]. Voltage sags are
defined as a momentary dip in voltage - below 10 % lasting from a few cycles(10ms) to 150
cycles(0.3s) [16].
Voltage sags cause diruption of service but do not cause damage to sensitive loads. On the
Figure 1.1: Control Power Flow in a Motor Drive
other hand, the voltage swells, which may exist cause damage but doesnt dirupt sensitive
1
2 Chapter 1. Introduction
loads. More than 62% of the disturbances are due to voltage sags with duration less thanhalf
a second [16]. A severe voltage is one where voltage falls below 85 %. Voltage sags are caused
by faults within the system, starting currents of motor.
In the induction motor drive, severe voltage sags on the control power supply feeding the
DSP, Gate drive cards, Current and Voltage sensing cards might cause the entire motor drive
system to shutdown. The control flow diagram is shown in figure 1.1. So a ride-through sys-
tem consisting of DC-DC converter, an energy source has been designed to overcome the
effect of these voltage sags and momentary black-outs.
1.1 Outline of the Project
The project involves
1. Design of The Energy Storage System Designing a stack of Ultracapacitors for provid-
ing fault ride through for a maximum load of 85W for 10s. This involves choice of
the capacitors based on the required capacitance and design of the capacitor voltage
balancing circuit.
2. Design of The Power Processing System- Designing a bi-directional buck-boost con-
verter. This involved selection of the power devices, Gate drive circuit, Heat sink,
design of the dsPIC30F2023 digital controller board and the design of feedback signals
sensing circuit.
3. Characterisation of the ultracapacitors assuming a simple first order R-C circuit model.
This involved testing the capacitors for their leakage resistance and capacitance.
4. Testing the converter in buck mode of operation and boost mode of operation in closed
loop fashion and developing the controllers and implementing them in dsPIC30F2023
controller.
5. Testing of the ride-through system with the converter.
1.2. The Ride-Through System 3
1.2 The Ride-Through System
The project aims at developing a fault ride through system using Ultracapacitors as the
source of energy. The ride through system consists of a bank of ultracapacitor charging and
discharging through a bi-directional buck-boost converter. The system has been designed to
provide back-up over a period of 10s. The ride through system is shown in figure 1.2. The
main power to the control cards is fed through the PFC boost converter circuit, consisting
of a transformer-rectifier system in cascade with boost converter to make the input current
continuous, feeding the bi-directional converter and the sensing cards in parallel.
Figure 1.2: Block Diagram of the Ride Through System
1.2.1 Need for a power converter
The block diagram of the ride through system consists of a power converter interfacing the
ultracapacitor and the loads. The converter is used to take control of the voltage levels
enabling the ultracapacitor to be charged to a voltage higher than the dc bus voltage or less
than that, in other words to shape the voltage profile of capacitor during charging and dis-
charging. Without the converter, the capacitor will get charged to the dc bus voltage without
any control over the charging current. The ultracapcitor is charged through the converter
at constant current when the main power is available, and during surges/blackouts the ca-
4 Chapter 1. Introduction
Figure 1.3: Need for a Bi-directional Converter
pacitor bank discharges through the boost converter at constant voltage. The specifications
of the ride through system are as given in table 1.1:
1.3 Organisation of the Project Report
The project project has been organised as follows elaborating the various points mentioned
in the outline
1 The characteristics of Ultracapacitors is explained in the second chapter. The con-
structional features of ultracapacitors along with their structural differences from the
electrolytic capacitors is discussed. With the construction, the applications of the ultra-
capacitors as back-up energy storage devices are put forth. Finally for the specifications
mentioned in table 1.1, the ultracapacitor bank design and cell voltage monitoring are
explained.
2 The third chapter discusses the the design of the experimental set up which consists
of:
i The bidirectional buck-boost converter which in turn involves:
- Selection of the Switching devices along with their gate drive circuit.
- Filter inductor and capacitor design.
1.4. Conclusion 5
Table 1.1: System Specifications
Parameter Value
VA Rating 240 VA
Maximum Load 85 W
Back up Capacity 10s
Maximum Voltage of the Ultracapacitor bank 30V
Nominal Voltage of the Ultracapacitor bank 24V
Switching Frequency 100kHz
ii The Digital controller dsPIC30F2023 board for the generation of PWM signals
iii The Feedback signals sensing circuit for sensing the currents and voltages for the
purpose of closed loop control.
iv Power factor correction circuit which becomes the primary source of power for
the loads.
3 The fourth chapter discusses the results. First the ultracapacitor characterisation test
results are presented. Then the closed loop control test results of the converter in buck
and boost mode of operation is discussed along with the bode plots for the design of
controllers . The fifth chapter gives conclusion of the designs done and the experiments
conducted.
1.4 Conclusion
This chapter gave an outline of the project. It discussed the voltage sag effects and reason
behind the project. The next chapter describes in detail the characteristics, construction and
applications of the ultracapacitors along with their sizing for the above mentioned system
specifications.
Chapter 2
Ultracapacitors - Modelling and
Sizing
This chapter describes the constructional features of ultracapacitor, applications of ultraca-
pacitor and sizinf of ultracapacitor. Ultracapacitors store energy in electrostatic form with
the constructional features similar to that of a battery. A simple parallel plate capacitor
stores energy in the electric field between the plates, the capacitance given by
C = Ad
(2.1)
Where A is the area of the parallel plates and d is the distance between the two parallel plates
and e is the permittivity of the medium. The electrolytic capacitor differs in construction
from the ordinary capacitor. An electrolytic capacitor has a metal electrode over which
there is a metal foil contact with the external circuit. There is a thin layer of metal oxide
formed on the electrode surface by the process of electrolysis i.e. passing current through a
electrolyte placed in contact with the electrode and the quantity of material deposited on
the electrode is given by the Faradays law of electrolysis
m = Z I t (2.2)
where m is the mass of material deposited and z is the electrochemical equivalent and I*t is
the charge applied.
The electrolytic capacitor consists of the electrolyte which acts as the cathode and the
electrode acts as anode. There is a separator which is used to prevent contact of the anode
with the wall of the container. The breakdown strength of the oxide layer is of the order of
several MV/cm which is the reason for very high capacitance of electrolytic capacitor. The
6
2.1. Construction of Ultracapacitor 7
typical metals used are valve metals like Aluminium, Titanium, Niobium and Tantalum,
Aluminium being more preferred because of its low cost. The electrolyte will vaporize at
high temperatures and crystallize at low temperatures making the ESR of the capacitor
requiring attention.
2.1 Construction of Ultracapacitor
Ultracapacitors are Electrochemical double layer capacitors (EDLC). A double layer is
formed at the interface between two different materials or phases. One phase is the metal
electrode and the other phase is the electrolyte. The particles at the interface represent a
double layer capacitor. figure 5.11 shows construction of a typical double layer capacitor.
Figure 2.1: construction of double layer capacitor
[13]
An ultracapacitor consists of two carbon electrodes (active excited porous carbon electrodes).
The active excitation increases the diameter of pores on the surface of carbon electrode which
helps in absorbing more ions and hence very high capacitance per unit volume. Electrolyte
acts as the ionic conductor flowing between the plates. The very high capacitance is due
to the small thickness of the layer separating the charges. The electrolyte type and the
number of pores determine the typical voltage withstand ability of a single ultracapacitor
cell. The decomposition voltage of sulphuric acid is about 1.2V. Typical capacitance of an
8 Chapter 2. Ultracapacitors - Modelling and Sizing
ultracapacitor varies from a few to 3000 Farads.
2.2 Comparison of Various Energy Sources
The various energy storage devices like batteries, fuel cells, ultracapacitors are compared
using a log-log plot called Ragones plot. The Ragones plot is a plot of power density versus
energy density. figure 2.2 shows the Ragones plot from which the particular device can
Figure 2.2: Ragones Plot
[17]
be chosen depending on the application. It shows that Ultracapacitors have higher power
density but lower energy density indicating that ultracapacitors are suited for high bursts of
power whereas it cannot be used to supply power continuously i.e. not suitable as primary
source of energy,. Batteries have a very high energy density whereas very low power density
making it not suitable for delivering high bursts of power. Thus ultracapacitors are being
widely used where high power is required to be delivered or absorbed in a very short time as
is the case in regenerative braking of motor where very high energy is available for a short
duration, which can be trapped using ultracapacitor. Table 2.1 gives a comparison between
2.3. Electrical characteristics of Ultracaps 9
Table 2.1: Comparison between batteries and ultracapacitors
Feature Ultracapacitor Batteries
Energy Storage Electrostatic Electrochemical
Charge/discharge cycles greater than 1,00,000 cycles less than 1000cycles
Energy density less than one-tenth of battery high
Charge and discharge rates low high
Shelf life high low
Weight Very heavy for same capacity as batteries heavy
Maintenance Maintenance free Requires maintenance
ultracapacitors and batteries.
2.3 Electrical characteristics of Ultracaps
The Electrical characteristics of Ultracapacitors is similar to that of an electrolytic capacitor.
The Ultracapacitors have been assumed to have a simple first order R-C circuit as shown
in figure 2.3. The ESR represents the series resistance due to the lead resistances, Contact
resistance of the electrodes and the electrolyte resistance. Rleak represents the loss of charge
when the ultracapacitor is left charged to its rated voltage.
2.4 Design of the Ultracapacitor Stack for the Ride
Through System
The total power consumed by the control cards is given in table 2.2. The power requirement
of the Control cards of the inverter has been calculated to be 78W (considering a safety
factor of 2 for the total current drawn by the cards). For the above system specifications,
assuming an efficiency of 70% for the converter, the ultracapacitor is sized for 125W.
10 Chapter 2. Ultracapacitors - Modelling and Sizing
Figure 2.3: Electrical characteristics
Table 2.2: Power consumed by the inverter control cards
Inverter Card Currents drawn(A) Power consumed(W)
+15V -15V 5V
Annunciation card 0.052 0.005 1.71
Voltage sensing cards(AC + DC) 0.238 0.033 8.13
Current sensing cards(4) 0.736 11.04
PD card 0.122 0.066 0.504 10.64
DSP card 0.1 0.1 1.5 10
Gate Drive Cards(6) 3 45
Total power 78
2.4. Design of the Ultracapacitor Stack for the Ride Through System 11
2.4.1 Number of Ultracapacitor cells
Befor calculating the number of ultracapacitor cells required, it would be good to know the
discharge characteristics of ultracapacitors under constant power through the use of power
converter. The discharge characteristics of the ultracapacitor is given by figure 2.4. As per
Figure 2.4: Discharge Profile
the system specifications
Vmax = 30V, Vmin = 13.7V, Vnominal = 24V (2.3)
dV = Vnominal Vmin (2.4)
Imax =P
Vmin(2.5)
Imin =P
Vmax(2.6)
The maximum current is decided from the ultracapacitor datasheet, which fixes the minimum
voltage to which the ultracap can drop to.
dV =IavgCt
(t+ ) (2.7)
In equation 2.7, is the timeconstant of the ultracap which is taken normally as 1.1s and t
is the time for the ultracap to provide ride throuugh, in this case being 10s. From equations
12 Chapter 2. Ultracapacitors - Modelling and Sizing
2.3, 2.4, 2.5, 2.6 and 2.7 the required capacitance is calculated to be 11F.
The number of cells required is calculated by
Ct = Ccell parallelcellsseriescells
(2.8)
The number of series cells is determined by the voltage rating of the stack.
numberofcellsinseries =VmaxVcell
(2.9)
The number of cells in series and parallel are calculated to be 12 and 1 respectively. Hence
the total number of ultracapacitor cells was chosen to be 12. The ultracapacitors used were
Maxwell BCAP0150 capacitors of capacitance 150F.
2.4.2 Ultracapacitor voltage management
The maximum voltage withstood by each ultracapacitor is about 2.5V or 2.7V, limited by
the electrolyte decomposition voltage. The series connection of the ultracapacitor leads to
unbalance in the voltage across each cell because of the differences in self-discharge rates.
This might lead to excess voltage on one cell and a lesser voltage on some other cell. To
prevent overvoltage across a particular cell, voltage equalization is done.
The equalization method adopted here is connecting a series string of Diodes, LEDs and
Figure 2.5: cell voltage management
a resistor of appropriate value in parallel with each cell. When the voltage across each cell
2.5. Conclusion 13
is more than forward voltage drop of the diodes plus that of the LEDs, the LEDs starts
glowing thereby discharging the cell. A 1.5 resistor was chosen to be used along with one
diode (BA159) and one LED.
The ultracapacitor hardware is shown in the appendix figures A.3 and A.4
2.5 Conclusion
The chapter explained the construction of ultracaps, difference between the various energy
sources, sizing of ultracapacitors for the ride through system and the voltage management
circuit. The tests done to test the capacitance and leakage resistance of the ultracaps along
with the characterisation results is explained in later chapters.
Chapter 3
Hardware Design
In this chapter, the hardware, which includes the power circuit, controller board, current
and voltage sensing card, has been discussed.
3.1 Power Circuit
The power circuit used is a 240VA bi-directional buck-boost converter. It comprises the
choice of switching devices, design of the filter elements, Device gate drive circuit.
3.1.1 Power Devices Selection
The minimum voltage to which the stack of ultracapacitors is discharged is determined by
the maximum current rating of the ultracapacitors. The power devices must carry this
current. The switches selected for this topology were IRF540N, the blocking voltage and
current rating of which are 100V and 33A respectively. External anti-parallel diodes are not
used with the MOSFETs, the body diodes of these devices are made use of.
3.1.2 Gate Drive Circuit
The driver circuit for the MOSFET consists of an optocoupler IC HCPL3101 to isolate the
control circuit from the power circuit and IR2110 which is the driver with separate High
and Low side referenced output channels. The driver circuit is powered by the power circuit
itself with isolation through a flyback converter. The gate drive voltage obtained from the
IR2110 is in the range of 10-20V. The bootstrap capacitor is selected as 10F based on the
formula given in the IR2110 datasheet.
14
3.1. Power Circuit 15
3.1.3 Filter Inductor and Capacitor Selection
The switching frequency is chosen as 100kHz. The inductor is designed for a current ripple
of 0.2A as follows
V = L dIdt
(3.1)
dI is the current ripple of 0.2A. dt is the on/off time of the switch. The inductor details
are as specified in the table 3.1. The value of V is chosen such that the product V*d is
Table 3.1: Inductor DetailsParameter Value
Inductor 300H
Switching Frequency 100kHz
Peak Current 9.1 A
Current ripple (peak-peak) 0.2A
Core Ferrite, E65/32/27
SWG 13
Air gap 1.6 mm
maximum. This occurs at the minimum value of the ultracapacitor voltage. The required
inductance is calculated as 300H. The filter capacitor is chosen depending on the voltage
ripple which is chosen to be less than 0.1 %. The capacitor is calculated to be 5000F. Hence
five nos. of 1000F ,63V Electrolytic capacitors are chosen with a 1F ,63V high frequency
capacitor. The high frequency capacitor is used in parallel with electrolytic ones because at
high frequencies the electrolytic capacitor starts becoming resistive thereby exhibiting higher
voltage ripple at switching frequencies.
3.1.4 Losses in the switches
The various losses in the devices are calculated as follows:
1. Forward conduction loss The forward conduction loss in the active switch(Mosfet) is
calculated to be
I2rms RDSon = 3.2W (3.2)
16 Chapter 3. Hardware Design
2. Reverse conduction loss The reverse conduction loss in the passive switch(Body diode
of complementary Mosfet) is calculated to be
Vav Iav = 3.86W (3.3)
3. Switching loss
Pswon = 0.5 VDS ID trT 0.5W (3.4)
Pswoff = 0.5 VDS ID tfT 0.5W (3.5)
3.1.5 Power Circuit Schematic
The entire power circuit schematic is given in the appendix. The current in the circuit is
sensed through the wire wound current sense resistor of 0.1. LM 2576 is a 12V,3A Buck
converter IC from National Semiconductors. It eliminates the need for external power supply,
hence keeping the area of experimental set up small. It is used to power
1. Gate drive card
2. dsPIC30F2023 Controller board.
It gets power from the upstream mains when it is present and from the ultracapacitor fed
boost converter in case of outage. All the components used in the power circuit along with
their values are listed in appendix. The power circuit with the various constituents are shown
in the appendix figure A.5.
3.2 Theory of operation
The block diagram of the ride through system was shown in figure 1.2. The power circuit
used in the system is shown in figure 3.1. The switches Q1 and Q2 are MOSFETS with anti-
parallel diodes. The circuit represents one leg of an H-bridge circuit. The circuit operates in
buck mode to charge the ultracapacitor. The circuit diagram in buck mode is as shown in
3.2 The switch Q1 is turned on by Gate pulse and the diode D2 freewheels to conduct when
Q2 is turned off. The controllers are designed such that the current through the inductor
is constant and the Ultracapcitors are charged at constant current.When there is an outage
the ultracapacitor discharges through the active switch Q2 and the diode D1. Q2 is gated
3.2. Theory of operation 17
Figure 3.1: Power circuit
Figure 3.2: Buck Mode of Operation
18 Chapter 3. Hardware Design
and D1 freewheels. This is the boost mode of operation. The controllers are designed so
that Q2 switches accordingly by varying the duty ratio to the switch.
Figure 3.3: Boost Mode of Operation
3.3 Controller Platform
The controller is implemented digitally through dsPIC30F2023. The existing controller board
[3] was used without modifications. The schematic given in appendix is also referred from
[3]. The Controller board is shown in figure appendix A.7.
3.4 Current and Voltage Sensing Circuit
To perform the controller action, all the voltages and currents should be converted into the
processors voltage range, here this being 5V. For this purpose, a LM-324 quad Op-amp
based cerrent and voltage sensing circuit was designed. The power for the LM-324 is fed
through the LM 2576 power supply IC. Hence the op-amps power supply terminals are
+12V and Ground. Negative potentials cannot be represented. The output of these cards
are fed to the ADC pins of the processor through an anti-aliasing filter circuit with a cut off
frequency less than 1kHz.
3.4. Current and Voltage Sensing Circuit 19
3.4.1 Voltage Sensing
Two voltages DC bus voltage and ultracapacitor voltage are sensed. The voltages are stepped
down by a magnitude of 10 using the non-inverting amplifier circuit. The circuit for voltage
sensing is shown in 3.4
Figure 3.4: Voltage Sensing Circuit
3.4.2 Current Sensing
The current is sensed through the current sense resistor of value 0.1. A capacitor is used
in parallel with the resistor, the resultant time constant being very less than switching time
of the converter. The current sensing part is used to produce a voltage as per the equation
VOadc = 2.5 + (0.167 I) (3.6)
Equation 3.6 is used to produce a output of 5V for a maximum current of 15A and 0V for
a maximum negative current of -15A. The circuit implementation and the hardware of the
sensing circuit are shown in fig. 3.5 and appendix figure A.6. This chapter explained the
design of entire hardware starting with power circuit to controller design and signals sensing
circuit. The next chapter explains the controller design.
20 Chapter 3. Hardware Design
Figure 3.5: Current sensing Circuit
Chapter 4
Controller Design
This chapter explains the design of controllers and their transformation to the z-domain and
finally implementation in dsPIC30F2023 through C programming.
4.1 Principle of Closed Loop Control
The closed loop control is done to prevent variations in the output voltage or output current,
due to any disturbances, by introducing a control variable in the form of duty ratio. This
control variable d, is used to turn on the active devices in the switching circuits for a duration
corresponding to its value. Closed loop control varies the duty ratio, in case of any deviation
in output parameter, from its present steady state value to a new steady state value thereby
correcting for the variation in the output.
4.1.1 Control Objective
The control objectives are as follows
1. Steady State Accuracy The steady state accuracy is required to be more than 99%.
The DC gain of the system is chosen to be very high.
2. Settling time in response to disturbances Any disturbance in the form of input variations
detours the output from its set value. The time to respond to this variation is kept as
small as possible. In other words, the bandwidth of the system is made high.
For the above objectives, first controller for the inner current loop is designed with a high
bandwidth and when controller for the outer voltage loop is designed, it is assumed the gain
21
22 Chapter 4. Controller Design
Figure 4.1: Closed Loop Control
Figure 4.2: Closed Control Loop - Outer Voltage Loop
4.1. Principle of Closed Loop Control 23
of inner current loop as unity. Then the controller is designed for the above objectives and
bandwidth of the outer voltage loop is kept atleast one-tenth the bandwidth of inner current
loop. This is because when the outer voltage loop is active, the actual current in the circuit
should have reached the set current reference. The outer voltage loop sets the inner current
reference. The references, output capacitor voltage and inductor current, are the dynamic
variables in the system.
24 Chapter 4. Controller Design
4.2 Buck Converter Control with Resistive Load
The buck converter was first tested with a resistive load, before charging the ultracaps. The
control involved providing an inner current loop and an outer voltage loop. The bandwidth
of the inner current loop is kept as one-tenth the switching frequency. In the following
section, the controller equations, bode plot and their implementation in z-domain is given.
4.2.1 Inner current loop
The figure 4.1 shows the control structure adopted. The bandwidth of the voltage loop is
kept as one-tenth the bandwidth of the current loop. The small signal transfer function of
current to control is given by
g(s) =i(s)
d(s)=VgR
1 + sRC
LCs2 + sLR
+ 1
The bode plot of the transfer function with the experimental values of
Vg-19V,R-10, C=1000F, L=300 is shown in figure 4.3
g(s) =i(s)
d(s)= 1.9
1 + s100
1 + s33333
+ s1825
2 (4.1)
As per the control objective, a PI controller is designed to make
1. Steady State Gain very high
2. Crossover at unity gain
3. Bandwidth high. Here bandwidth of the inner current loop is kept at 10krad/sec.
The transfer function of the PI controller used is
h(s) =d(s)
ei(s)=
1 + s1825s
250
(4.2)
The bode plot of the loop gain GH is given in figure 4.4 The digital implementation of the
above PI controller is done using bilinear transformation. The controller implemented with
a sampling frequency of 20kHz is
kp[n] = (0.144 error[n]) (4.3)
ki[n] = ki[n 1] + (0.00625 error[n]) + (0.00625 error[n 1]) (4.4)The duty ratio is generated by the addition of equations 4.3 and 4.4
4.2. Buck Converter Control with Resistive Load 25
Figure 4.3: Current to Control transfer function i(s)/d(s)
Figure 4.4: inner current loop - Loop gain GH transfer function i(s)/ iref (s)
26 Chapter 4. Controller Design
4.2.2 Outer Voltage Loop
The small signal transfer function of voltage to current is given by
g(s) =v(s)
i(s)=
R
1 + sRC(4.5)
g(s) =v(s)
i(s)=
10
1 + s100
The Voltage loop PI controller is chosen for a bandwidth of 1000 rad/sec. The transfer
function of the PI controller used is
h(s) =iref (s)
ev(s)=
1 + s100
s100
(4.6)
The above controller in digital domain is
kp[n] = (1 error[n]) (4.7)
ki[n] = ki[n 1] + (0.0025 error[n]) + (0.0025 error[n 1]) (4.8)iref [n] = kp[n] + ki[n] (4.9)
The reference current for the inner loop is set by 4.9. The bode plots for the outer voltage
loop are shown in figures 4.5 and ??
4.2. Buck Converter Control with Resistive Load 27
-20
-10
0
10
20
30
40
50
Magni
tude (d
B)
100 101 102 103 104-90
-45
0
Phase
(deg)
Frequency (rad/sec)
Figure 4.5: Voltage to Current transfer function V(s)/i(s)
Figure 4.6: Outer Voltage Loop - Loop gain GH transfer function V(s)/Vref (s)
28 Chapter 4. Controller Design
4.3 Buck Converter Controller for Charging Ultraca-
pacitors
The control structure adopted for charging ultracapacitors is the same as shown in figure
4.1. The controller gains are different.
4.3.1 Inner Current Loop
g(s) =i(s)
d(s)=
VgCs
LCs2 + sLR
+ 1
Here the charging was done at
Vg=10V,C=12.5F,L=300H, R-0.2. R is the total ESR of the Ultracapacitor stack and
was measured per cell using Network analyser.
g(s) =i(s)
d(s)=
125s
1 + s667
+ s16
2 (4.10)
The PI controller used to achieve the control objective is
h(s) =d(s)
ei(s)=
1 + s1000s
253
(4.11)
and in digital domain, the PI controller is
kp[n] = (0.253 error[n]) (4.12)
ki[n] = ki[n 1] + (0.006325 error[n]) + (0.006325 error[n 1]) (4.13)d[n] = kp[n] + ki[n] (4.14)
The duty ratio is given by equation 4.14. During charging of the ultracapacitors, the duty
ratio varies from zero to one, with the ultracapacitor stack charging slightly over the set
reference and finally the duty ratio settles at zero at this overcharged value. The bode plots
of the current to control transfer function and current loop gain are shown in figures 4.7 and
4.8
4.3. Buck Converter Controller for Charging Ultracapacitors 29
Figure 4.7: Current to Control transfer function - ultracap charging i(s)/d(s)
Figure 4.8: Current Loop gain GH - ultracap charging i(s)/iref
30 Chapter 4. Controller Design
4.3.2 Outer Voltage Loop
In this case the outer voltage loop controller can be just a proportional controller. The small
signal transfer function of voltage to current is given by
g(s) =v(s)
i(s)=
1
Cs(4.15)
g(s) =v(s)
i(s)=
1
12.5s
The Voltage loop PI controller is chosen for a bandwidth of 1000 rad/sec. The transfer
function of the PI controller used is
h(s) =iref (s)
ev(s)= 12500 (4.16)
The above controller in digital domain is
kp[n] = (12500 error[n]) (4.17)
iref [n] = kp[n] (4.18)
The reference current for the inner loop is set by 4.18.
4.4. Boost Converter Controller 31
4.4 Boost Converter Controller
The boost converter control structure implemented is a voltage loop control. Here, in ad-
dition to a PI controller, a lead compensator is used to improve phase margin at the gain
cross over frequency. The voltage to control transfer function is given by
g(s) =v(s)
d(s)=
VgR(1 D)2
1 s LR((1D)2
1 + s LR((1D)2 +
LC(1D)2 s
2
In the experiment done, the values used were C=1000F, Vg=10V, L=300H, R=20,
D=0.375 The transfer function turns out to be
g(s) =v(s)
d(s)= 38.4
1 s26042
1 + s26042
+ s510
2 (4.19)
h(s) =d(s)
ev(s)=
1 + s510
s208
1 + s510
1 + s10000
(4.20)
error(s) in equation 4.20 is the voltage error which is given by the difference in the voltage
between the set reference value through the processor and the sensed value from the system.
Bode plots of the voltage to control transfer function and the loop gain transfer function are
shown in figures 4.9 and 4.10 respectively.
-100
-80
-60
-40
-20
0
20
40
60
80
100
Magni
tude (d
B)
102 103 104 105 106-270
-180
-90
0
Phase
(deg)
Frequency (rad/sec)
Figure 4.9: Voltage to Control transfer function - ultracap discharging v(s)/d(s)
32 Chapter 4. Controller Design
-60
-40
-20
0
20
40
60
80
Magni
tude (d
B)
101 102 103 104 105 106-270
-225
-180
-135
-90
-45
0
Phase
(deg)
Frequency (rad/sec)
Figure 4.10: Voltage Loop gain GH - ultracap Discharging V(s)/Vref (s)
Chapter 5
Experimental Results
In this Chapter, the results obtained as a result of experiments conducted are presented.
5.1 Ultracapacitor Characterisation
The first in the series of experiments was to test the Ultracapcitors individually for their
Capacitance and leakage resistance. For this, the ultracaps were charged at constant current
to a voltage slightly below the rated voltage using a 30V,2A power supply and discharged
through a 5 load. The data was logged using YOKOGAWA MX100 Datalogger. To
monitor the leakage resistance, the cells were charged to 2.5V and disconnected from external
circuits. The voltages across the cells were monitored over a weeks period at 24 hour interval.
Table 5.1 gives the values of the 12 ultracapacitors being used. The values logged were used
in excel and line of best fit was constructed and the values found. The values for the above
12 capacitors were plotted using excel and the plot is shown in figure 5.1
5.2 Ultracapacitor Voltage Monitoring Circuit
The voltage monitoring circuit was tested with a comination of resistor, LEDs and diodes
of different ratings. The results which were consequential in choosing the components used
in the ultracapacitor board are summarised in figure 5.2 The characteristic required should
be such that at over 2.5V, the ultracap should exhibit a significant leakage current to bring
the voltage down to 2.1 or 2V, at which the leakage current should be almost zero. As per
the figure 5.2, the characteristic is satisfied by a series combination of 1 LED, 1.5 resistor
and 1 diode, which is hence chosen.
33
34 Chapter 5. Experimental Results
Table 5.1: Ultracapacitors Parameters
S.No Capacitance(F) Leakage resistance(k)
1 123.43 9.528
2 123.77 10.26
3 131.33 9.838
4 146.11 9.094
5 148.14 9.646
6 150.69 10.24
7 152.72 10.63
8 153.37 11.42
9 158.05 10.11
10 158.78 11.4
11 159.62 12.6
12 160.43 16.97
Figure 5.1: Ultracapacitors Charging Plots
5.3. Closed Loop Control Results 35
Figure 5.2: Ultracapacitors Voltage Management Circuit
5.3 Closed Loop Control Results
5.3.1 Buck Converter - Ultracapacitor Charging Test Results
The following describe the waveforms captured on scope
1. Blue waveform - DC bus Voltage
2. Brown waveform - Ultracapacitor current (Sensing circuit output)
3. Red waveform - Ultracapacitor Voltage
5.3.1.1 Charging at 1A
The input voltage was kept fixed at 24V. The charging was done with a charging current
reference of 1A. The scope waveform shows the capacitor getting charged from 7V to 23V in
almost 175secs. This is validated below. For an ultracapacitor current of 1A, output from
sensing circuit should be 2.67V which can be seen on scope. Figure 5.3 shows the charging
at 1A.
I = Cdv
dt(5.1)
Iadc = 2.5 + (0.167 1) = 2.67V (5.2)t = dv C
I= (23 7) 12.5
1= 200s (5.3)
36 Chapter 5. Experimental Results
Figure 5.3: Charging of Ultracaps - 1A
5.3.1.2 Charging at 2A
The input voltage was kept fixed at 24V. The charging was done with a charging current
reference of 2A. The scope waveform shows the capacitor getting charged from 4V to 23V
in almost 90secs. This is validated below. For an ultracapacitor current of 2A, output from
sensing circuit should be 2.83V which can be seen on scope. Figure 5.4 shows the charging
at 2A.
Figure 5.4: Charging of Ultracaps - 2A
I = 2A (5.4)
Iadc = 2.5 + (0.167 2) = 2.83V (5.5)
5.3. Closed Loop Control Results 37
t = dv CI
= (23 4) 12.52
= 125s (5.6)
38 Chapter 5. Experimental Results
5.3.2 Boost Converter Test Results
First the boost converter was tested with the controller programmed to take a 4V input and
generate a 6V output with the latter as the reference voltage. The following describe the
waveforms captured on scope
1. Green Waveform : Input Voltage,
2. Blue waveform : Output Voltage.
The above waveforms are each 2V/div for figures 5.5,5.6,5.7 and at 10V/div for 5.8,5.9 and
5.10.
1. Figure 5.5 shows output voltage of the boost converter whiich was at slightly less than
4V reaching 6V in nearly 1sec. The voltage spikes on the waveforms are switching
spikes and power supply noise.
Figure 5.5: Boost Converter Constant Voltage Control - 4.7V input, 6V output, 20ohm load
2. The figure 5.6 shows a step change in input voltage from 4V to 5.7V. The output
voltage increases momentarily and settles down at 6V in about 1sec.
3. Figure 5.7 shows a step change in voltage from 5.6V to 4.5V, the output decreases
alongwith the input and finally settles down at the set reference of 6V.
5.3. Closed Loop Control Results 39
Figure 5.6: Boost Converter Constant Voltage Control - Step Increase in Input
Figure 5.7: Boost Converter Constant Voltage Control - Step Decrease in Input
40 Chapter 5. Experimental Results
The boost converter was then tested to simulate the voltage decrement across the ultraca-
pacitor from 24V to 14V. This was done by varying a 60V,5A power supply from 24 to 14V,
although the load in the intended application is 6. Here the test was done with a 20,50W
resistor. The various test results are as follows
All the tests were done with a reference voltage of 25V.
1. Figure 5.8 shows the converter reaching steady state voltage of 25V from initial voltage
of slightly over 18V when the controller is turned on. The steady state voltage is
reached in almost 1sec.
Figure 5.8: Boost Converter Constant Voltage Control - 15V input, 25V output, 20ohm load
2. Figure 5.9 shows a step increase in the input from 15V to 22V. The output voltage
increases and finally settles down to 25V in about a sec.
Figure 5.9: Boost Converter Constant Voltage Control - Step Increase in Voltage
5.3. Closed Loop Control Results 41
3. Figure 5.10 shows a step decrease in the input from 22V to 15V. The output voltage
decreases and finally settles down to 25V in about a sec. This is the condition that
happens when the ultracap is conducting, where the voltage decreases from 24 to 14V.
Figure 5.10: Boost Converter Constant Voltage Control - Step Decrease in Voltage
42 Chapter 5. Experimental Results
5.3.3 Boost Converter test results with ultracapacitor input
The following are the waveforms captured on scope:
1. Blue waveform - DC bus Voltage
2. Brown waveform - Ultracapacitor current (Sensing circuit output)
3. Red waveform - Ultracapacitor Voltage
5.3.3.1 Boost Converter Operation with 25W(23V, 20) load
Figure 5.11: Boost Converter Operation with 25W load
The figure 5.11 shows the discharge profile of ultracapacitors under a 25W (23V, 20)
load. It can be seen that the discharge takes place for almost 50secs, after which the PWM
is turned off because the ultracapacitor has dischared to its minimum voltage level which
has been set as 15V.
5.3.3.2 Boost Converter Operation with 50W(23V, 10) load
The figure 5.12 shows the discharge profile of ultracapacitors under a 50W (23V, 10) load.
It can be seen that the discharge takes place for almost 25secs, after which the PWM is
turned off because the ultracapacitor has dischared to its minimum voltage level which has
been set as 15V.
5.3. Closed Loop Control Results 43
Figure 5.12: Boost Converter Operation with 50W load
5.3.4 Integrated Operation of Buck and Boost converter
The integrated opeartion is about creating the effect of voltage sag at the terminals of the
ultracapacitor and the converter and letting the ultracapacitor discharge with a 75W load
and the power supply would be turned on to charge the capacitors once again. Figures 5.13
Figure 5.13: Integrated operation - 75W(23V,7)
and 5.14 show the integrated operation of the Ride through system with a 75W load. It can
be seen that the voltage outage is detected in less than a second and the boost converter
operates for almost 9secs. Few more results were taken similar to figures 5.13 and 5.14
which are given below explaining the response to voltage outages. These figures show that
blackouts are detected in less than a second.
44 Chapter 5. Experimental Results
Figure 5.14: Integrated operation - 75W(zoomed view)
Figure 5.15: Integrated operation 1
5.4. Efficiency of the Power Circuit 45
Figure 5.16: Integrated operation 2
5.4 Efficiency of the Power Circuit
The Power circuit was tested in the buck mode with a 10 load for efficiency and with duty
ratios varying from 0.5 to 1. The results are tabulated as in table 5.2
Table 5.2: Efficiency of Power Circuit in Buck mode
Vin Iin Vo Io Dutycycle Efficiency
19 0.4 7.75 0.78 0.4 79
19 0.266 6.23 0.63 0.33 76.8
19 0.536 9.26 0.93 0.487 84.2
19.1 0.673 10.73 1.07 0.57 90
19.1 0.85 12.25 1.22 0.64 92.2
19.1 1.055 13.76 1.38 0.72 94
19.1 1.288 15.21 1.52 0.79 94
19.1 1.548 16.7 1.67 0.87 94.3
46 Chapter 5. Experimental Results
5.5 Thermal Test
A temperature rise test was done on the entire system by running the converter in buck
mode. The results were monitored using FLUKE TI20 THERMAL IMAGER. The
pictures taken using the thermal imager are shown below. It can be seen that the processor
dsPIC30F2023 is the hottest in the entire system. The current levels in the power circuit
were not too high to cause any significant copper loss in the inductor or conduction loss in
the conducting devices. The figure 5.17 shows the temperature rise of the half bridge and
Figure 5.17: Thermal Test - Switches
LM2576 power supply IC. A black tape was put on the heat sink of the individual devices
to account for the emissivity of surfaces. The heat sink surface of the power supply IC was
black, not necessitating the use of tape. The figure 5.18 shows the temperature rise of the
processor board. The processors temperature rise is justified, as when program is flashed
into the processor, it draws significant power. The figure 5.19 shows the temperature rise of
the gate drive circuit, the black surfaces emissivity has been recorded in spite of not drawing
power.
5.5. Thermal Test 47
Figure 5.18: Thermal Test - Processor
Figure 5.19: Thermal Test - IR2110 and HCPL 3101
Chapter 6
Conclusions
The project on providing ride through for control power supply could be completed with the
following points noted during course of the project
1. The boost converter control was succcessfully tested and the results captured with
both power supply and the ultracapacitor input.
2. The charging of ultracapcitors in buck mode was tested at two current levels - 1A and
2A and the charging profile was found to be satisfactory. Voltage spikes of very high
magnitudes were experienced both at lower and higher voltage levels, which might have
a detrimental effect on the life of ultracapacitors.
3. The integration of buck and boost converter operations and hence testing of the whole
system could be completed successfully with the tests carried out by turning off the
power supply and allowing the ultracapacitor to feed the load and turning on the power
supply, whence it started charging back to the set reference.
The back up offered for various loads is shown in table 6.1.
The following issues might also be interesting.
1. Gate Drive Card : When charging was tried, with the capacitor already charged to
slightly more than half the reference voltage, the controller immediately saturated, but
the high side switch of the half bridge remained switched off. This finally turned out
to be an issue with the bootstrap capacitor on the Gate driver IR2110. If the low side
48
49
Table 6.1: Ride Through System Results
Load Backup Period
25W 50s
50W 25s
75W 9s
switch never turns on, there is no other way to charge the bootstrap capacitor. So an
isolated 12V power supply was used for charging this bootstrap capacitor.
2. Issues with dsPIC30F2023 target board : There was a plenitude of processor failures.
The reason is attributed to momentary overvoltages above its rated voltage of 5V
through the Analog input channels.So a 4.7V zener was used to avoid the processor
failures. The processor failures can also be reasoned due to the temperature rise. So
forced cooling (using fans) has to be adopted to avoid the processor failures. It might
also be because the target processor board layout is not satisfactory on the thermal side.
Sufficient space has to provided around the dsPIC30F2023 processor before connecting
it to the other components.
3. Another issue with the converter was that, the controller programs wouldnt run in
debug mode with the boost converter mode of operation and hence had to done in pro-
grammer mode. The reason is, in buck mode of operation, the main 12V power supply
powered both the converter and the processor with the MPLAB ICD2 experiencing
no undervoltages due to the switching. But in boost mode of operation, main power
supply is absent and the switching spikes got propogated through the current sense
resistor, which is connected to ground, whereby the debugger experience undervoltages
and shutdown in the middle of execution/running the target. This was solved by exe-
cuting the processor in a stand alone mode without the debugger and connecting the
debugger only when it was necessary to program.
4. The final issue being the switching spikes which need to be eliminated. This is because
of stray inductances due to the usage of long wires in various paths.
Appendix A
Schematics and Experimental Setup
A.1 Power Circuit Schematics
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
S
D
S
D
POWER CIRCUIT
GATE DRIVE CIRCUIT
NCC11
1u,63V
R9
10k21
TP8
1
U2
HPCL3101
1234 5
678
F1
FUSE
TP1
1
JP5
12
C20.1u
1
2
JP2
12
R11
0.1 ohms, 10W21
JP6
12
C310u
1
2
C9
1000u,63V
R64.7k
2
1
C12100u
JP3
12
R1
1.2k
21
M2IRF540N
TP6
1
JP1
12
M2
IRF540N
IR2110
U3
89
1011121314
7654321
NCVDDHINSDLINVssNC
HOVBVSNC
VCCCOM
LO
D3
15 V
12
U4
LM2576123456
123456
TP7
1
TP4
1
D1BYW29-150
31
TP2
1
JP3
12
Q22N2222
3
2
1
D2 15 V1 2
R2
4.7k
21
R34.7k
2
1
TP10
1
L2
680uH1 2
JP4
123
C40.1u
1
2
TP3
1
C510u
1
2
R7 1221
L1
300uH1 2
C60.1u
1
2
R8
1221
C131000u,35V
C710u
1
2
C101000u,63V
C10.1u
1
2
TP9
1
C80.1u
1
2
R4
1.2k
21
R1010k
2
1
JP7
12
U1
HPCL3101
1234 5
678
TP5
1
D11 1N5814
12
Q12N2222
3
2
1
R5
4.7k
21
H0M
GND
Vcap
N
Vbus
Isense
L0
GND3
VcapGND
GND3Vbus
GND2Vcc1
PWM1PWM2GND1
VpGND1
Vcc2GND3
VprocGND3
GND3Isense
L0
GND2
PWM2
Vcc
H0
GND1
Vcc1
PWM1
NGND2
GND2
Vp
M
Vp
GND1
GND3
GND3
Vcc2
Vproc
Vcc
Figure A.1: Power Circuit Schematic
50
A.2. Controller Schematics 51
A.2 Controller Schematics
Figure A.2: dsPIC Controller Board Schematic
[3]
52 Appendix A. Schematics and Experimental Setup
A.3 Ultracapacitor board - Top View
Figure A.3: Ultracapacitor Hardware - Top View
A.4. Ultracapacitor board - Side View 53
A.4 Ultracapacitor board - Side View
Figure A.4: Ultracapacitor Hardware - Side View
54 Appendix A. Schematics and Experimental Setup
A.5 Power Circuit Hardware
Figure A.5: Power Circuit Hardware
A.6. Voltage and Current Sensing Circuit Hardware 55
A.6 Voltage and Current Sensing Circuit Hardware
Figure A.6: Sensing Circuit Hardware
56 Appendix A. Schematics and Experimental Setup
A.7 Controller Circuit Hardware
Figure A.7: Controller Circuit Hardware
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57
58 References
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