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KCT- M.E [AE] I to IV Semester Curriculum and Syllabus R 2009 1/48

Signature of the Chairman BOS M.E [AE]

KUMARAGURU COLLEGE OF TECHNOLOGY, COIMBATORE-6(An Autonomous College Affiliated to Anna University, Coimbatore)

M.E. APPLIED ELECTRONICS

REGULATION 2009

SEMESTER I

Code No. Course Title L T P CTHEORYMAT506 Applied Mathematics for Electronics Engineers 3 1 0 4ANE501 Advanced Digital System Design 3 1 0 4ANE502 VLSI Design Techniques 3 0 0 3ANE503 Advanced Digital Signal Processing 3 0 0 3ET1*** Elective I 3 0 0 3ET2*** Elective II 3 0 0 3

PRACTICALANE701 VLSI Laboratory 0 0 3 1Total 21

SEMESTER II

Code No. Course Title L T P CTHEORYANE504 Analysis and Design of Analog Integrated Circuits 3 1 0 4ANE505 Computer Architecture and Parallel Processing 3 0 0 3ANE506 Embedded Systems 3 0 0 3

ANE507 ASIC Design 3 0 0 3ET3*** Elective III 3 0 0 3ET4*** Elective IV 3 0 0 3PRACTICALANE702 Electronic System Design Project 0 0 3 1Total 20

SEMESTER III

Code No. Course Title L T P CTHEORYET5*** Elective V 3 0 0 3ET6*** Elective VI 3 0 0 3ET7*** Elective VII 3 0 0 3ANE524 Research Methodology 2 0 0 2PRACTICALANE703 Project Work (Phase I) 0 0 12 6Total 17

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SEMESTER IV

Code No. Course Title L T P CANE703 Project Work (Phase II) 0 0 24 12Total 12

GRAND CREDIT: 70

LIST OF ELECTIVES

M.E. APPLIED ELECTRONICS

Code No. Course Title L T P CANE508 Digital Image Processing 3 0 0 3

ANE509 Neural Networks and Applications 3 0 0 3ANE510 Low Power VLSI Design 3 0 0 3ANE511 DSP Integrated Circuits 3 0 0 3ANE512 Digital Control Engineering 3 0 0 3ANE513 Design and Analysis of Algorithms 3 0 0 3COM517 Soft Computing 3 0 0 3COM519 Internetworking Multimedia 3 0 0 3ANE514 DSP Processor Architecture and Programming 3 0 0 3COM521 High Performance Communication Networks 3 0 0 3COM522 High Speed Switching Architecture 3 0 0 3ANE515 Advanced Processors 3 0 0 3ANE516 VLSI Signal Processing 3 0 0 3ANE517 Analog VLSI Design 3 0 0 3ANE518 Computer Aided Design of VLSI Circuits 3 0 0 3MAT507 Stochastic Models and Simulation 3 1 0 4CSE501 Data Structures and Algorithms 3 0 0 3CSE502 Advanced Computer Architecture 3 0 0 3CSE504 Network Engineering 3 1 0 4CSE505 Object Oriented Software Engineering 3 0 0 3CSE506 Web Technology 3 0 0 3ANE519 Mobile Computing 3 0 0 3ANE520 Cellular and Mobile Communication 3 0 0 3ANE521 E-Commerce Technology 3 0 0 3ANE522 Real Time and Embedded Systems 3 0 0 3ANE523 Visualization Techniques 3 0 0 3

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MAT506 APPLIED MATHEMATICS FOR ELECTRONICS ENGINEERS3 1 0 4

(Common to Communication Systems and Applied Electronics)

UNIT I

NUMERICAL SOLUTION OF EQUATIONS AND EIGEN VALUEPROBLEM 9Method of false position Newton Raphson method Iteration method Solution of linear system by Gaussian elimination and Gauss-Jordon methods- Iterative methods:Gauss Jacobi and Gauss-Seidel methods Eigen values of a matrix by Power method.

UNIT IIWAVE EQUATION 9Solution of initial and boundary value problems Characteristics Significance of characteristic curves Laplace transform solutions for displacement in a long string.

UNIT III SPECIAL FUNCTIONS 9Bessels equation Bessel Functions Legendres equation Legendre polynomials Rodrigues formula Recurrence relations Generating functions and orthogonalproperty of Bessel functions and Legendre Polynomials.

UNIT IVRANDOM VARIABLES 9One-dimensional Random Variables Moments and MGF Binomial, Poisson,Geometric, Exponential and Normal distributions Two-dimensional Random Variables Marginal and Conditional distribution Covariance and Correlation coefficient.

UNIT VQUEUEING THEORY 9Single and Multiple server - Markovian queueing models Steady state system sizeprobabilities Littles formula M/G/1 queueing system P-K formula (Derivationsexcluded for all models).

L: 45 T: 15 Total : 60

TEXT BOOKS:

1. Jain M.K., Iyengar S.R.K & Jain R.K., Numerical Methods for Scientific andEngineering Computation, New Age International Publishers (P) Ltd, 2007.

2. Sankara Rao K., Introduction to Partial Differential Equation, Prentice Hall of India, 2007.

3. Grewal B.S., Higher Engineering Mathematics, Khanna Publications, 40 th Edition2007.

4. Veerarajan. T., Probability and Random Process, Tata McGraw Hill,2008

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REFERENCES:

1. Kapur J.N., Saxena H.C., Mathematical Statistics, S. Chand & Company Limited,New Delhi 2007.

2. Taha H.A., Operations Research - An Introduction, Prentice Hall of India, 2008.

3.

Gross. D & Harris C.M., Fundamentals of Queuing Theory, John Wiley & Sons,2008.4. Jain R.K., Iyengar S.R.K., Advanced Engineering Mathematics, Narosa Publishers,

2007.5. Kandasamy P., Thilagavathi K. and Gunavathi K., Probability, Statistics and

Queuing Theory, S.Chand and Company Ltd, 2007.

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ANE501 ADVANCED DIGITAL SYSTEM DESIGN 3 1 0 4UNIT I 9SEQUENTIAL CIRCUIT DESIGNAnalysis of Clocked Synchronous Sequential Networks (CSSN) Modeling of CSSN State Stable Assignment and Reduction Design of CSSN Design of Iterative Circuits

ASM Chart ASM Realization.UNIT II 9ASYNCHRONOUS SEQUENTIAL CIRCUIT DESIGNAnalysis of Asynchronous Sequential Circuit (ASC) Flow Table Reduction Races inASC State Assignment Problem and the Transition Table Design of ASC Staticand Dynamic Hazards Essential Hazards Data Synchronizers Designing VendingMachine Controller Mixed Operating Mode Asynchronous Circuits.

[

UNIT III 9IMPLEMENTING LOGIC FUNCTIONS USING MSI AND PROGRAMMABLEDEVICESImplementing Logic Functions using MSI Multiplexers Shannons Expansion Theorem,Designing with Multiplexers, Additional Techniques for Designing with Multiplexers,Implementing Logic Functions using MSI Decoders, Implementing Logic Functionsusing Exclusive OR and Exclusive NOR Elements, Implementing Logic Functions usingProgrammable Devices - Programmable Read Only Memory(PROM), ProgrammableArray Logic(PAL), Programmable Logic Array(PLA), Multi Level PLDs.UNIT IV 9FAULT DIAGNOSIS AND TESTABILITY ALGORITHMSFault Table Method Path Sensitization Method Boolean Difference Method KohaviAlgorithm Tolerance Techniques The Compact Algorithm Practical PLAs Faultin PLA Test Generation Masking Cycle DFT Schemes Built-in Self Test.UNIT V 9SYSTEM DESIGN USING VHDLVHDL Description of Combinational Circuits Arrays VHDL Operators Compilation and Simulation of VHDL Code Modeling using VHDL Flip Flops Registers Counters Sequential Machine Combinational Logic Circuits - VHDLCode for Serial Adder, Binary Multiplier Binary Divider complete SequentialSystems Design of a Simple Microprocessor. - Introduction to test benches.

L: 45 T: 15 Total : 60TEXT BOOK: 1. Donald G. Givone, Digital principles and Design, Tata McGraw Hill 2002 2. Nripendra N Biswas, Logic Design Theory, Prentice Hall of India, 2001.3. Richard S.Sandige, Modern Digital Design, McGraw Hill International Editions,

1990.4. Volnei A. Pedroni, Circuit Design with VHDL, MIT Press, 2004.

REFERENCES: 1. Stephen Brown and Zvonk Vranesic, Fundamentals of Digital Logic with VHDL

Design, Tata McGraw Hill, 2002.2. Peter J Ashendem, The Designers Guide to VHDL ,Harcourt India Pvt Ltd, 2002.3. Mark Zwolinski, Digital System Design with VHDL ,Pearson Education, 2004.

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ANE502 VLSI DESIGN TECHNIQUES 3 0 0 3

UNIT I 9MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGYNMOS and PMOS transistors, Threshold voltage- Body effect- Design Equations -

Second order effects. MOS models and small signal AC characteristics. Basic CMOStechnology.

UNIT II 9INVERTERS AND LOGIC GATES NMOS and CMOS Inverters, Stick diagram, Inverter ratio, DC and transientcharacteristics , switching times, Super buffers, CMOS logic structures , Transmissiongates, Static CMOS design, dynamic CMOS design.

UNIT III 9CIRCUIT CHARACTERISATION AND PERFORMANCE ESTIMATION

Resistance estimation, Capacitance estimation, Inductance, Inverter switchingcharacteristics fall time, rise time, propagation delay. CMOS - Gate transistor sizing,power dissipation.

UNIT IV 9VLSI SYSTEM COMPONENTS CIRCUITS AND SYSTEM LEVEL PHYSICALDESIGNMultiplexers, Decoders, comparators, priority encoders, Shift registers Arithmetic circuits Ripple carry adders, Carry look ahead adders, High-speed adders, Multipliers. Physicaldesign Delay modelling, cross talk, floor planning, power distribution. Clock distribution.

UNIT V 9TESTING AND DESIGN FOR TESTABILITYNeed for testing-Fault models- Fault Orient test pattern generation Fault simulation Testability improvement Structural design for testability Boundary scan test.

Total: 45TEXT BOOK:

1. Neil H.E. Weste and Kamran Eshraghian, Principles of CMOS VLSI Design,Pearson Education ASIA, 2 nd edition, 2000.

REFERENCES:

1. Pucknell, Basic VLSI Design, Prentice Hall of India Publication, 1995.2. John P.Uyemura ,Introduction to VLSI Circuits and Systems, John Wiley & Sons,

Inc., 2002.3. Samir Palnitkar, Verilog HDL, Pearson Education, 2 nd Edition, 2004.4. Mark Zwolinski Digital system Design with VHDL , Second Edition, Pearson

Education Pvt .Ltd, New Delhi-2004.

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ANE503 ADVANCED DIGITAL SIGNAL PROCESSING 3 0 0 3[Review of discrete-time signals and systems- DFT and FFT, Z-Transform, Digital Filtersis recommended]

UNIT I 9

DISCRETE RANDOM SIGNAL PROCESSINGDiscrete Random Processes- Ensemble averages, stationary processes, Autocorrelationand Auto covariance matrices- Parameter estimation: Bias and consistency-Parseval'sTheorem, Wiener-Khintchine Relation- Spectral Factorization, Filtering randomprocesses, Low Pass Filtering of White Noise.

UNIT II 9SPECTRUM ESTIMATIONEstimation of spectra from finite duration signals, Non-Parametric Methods-CorrelationMethod, Periodogram Estimator, Performance Analysis of Estimators -Unbiased,Consistent Estimators- Modified Periodogram, Bartlett and Welch methods, Blackman

Tukey method. Parametric Methods - AR, MA, ARMA model based spectral estimation.Parameter Estimation -Yule-Walker equations.

UNIT III 9LINEAR ESTIMATION AND PREDICTION Linear prediction- Forward and backward predictions, Solutions of the Normal equations-Levinson algorithm, Levinson-Durbin algorithm. Least mean squared error criterion -Wiener filter for filtering and prediction, FIR Wiener filter and Wiener IIR filters,Discrete Kalman filter.

UNIT IV 9ADAPTIVE FILTERS FIR adaptive filters -adaptive filter based on steepest descent method-Widrow-Hoff LMSadaptive algorithm, Normalized LMS. Adaptive channel equalization-Adaptive echocancellation-Adaptive noise cancellation- Adaptive recursive filters (IIR). RLS adaptivefilters-Exponentially weighted RLS-sliding window RLS.

UNIT V 9MULTIRATE DIGITAL SIGNAL PROCESSING Mathematical description of change of sampling rate - Interpolation and Decimation ,Decimation by an integer factor - Interpolation by an integer factor, Sampling rateconversion by a rational factor, Filter implementation for sampling rate conversion- directform FIR structures, Polyphase filter structures, time-variant structures. Multistageimplementation of multirate system. Application to sub band coding - Wavelet transformand filter bank implementation of wavelet expansion of signals.

L :45 Total: 45TEXT BOOK:

1. Monson H.Hayes, Statistical Digital Signal Processing and Modeling, John Wiley andSons, Inc., Singapore, 2002.

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REFERENCES:

1. John G. Proakis, Dimitris G.Manolakis, Digital Signal Processing Pearson Education,2002.

2. John G. Proakis et.al.,Algorithms for Statistical Signal Processing, Pearson

Education, 2002.3. Dimitris G.Manolakis et.al.,Statistical and adaptive signal Processing, McGraw Hill,New York, 2000.

4. Rafael C. Gonzalez, Richard E.Woods, Digital Image Processing, PearsonEducation, Inc., Second Edition, 2004.( For Wavelet Transform Topic)

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ANE701 VLSI LABORATORY 0 0 3 1

Experiments based on front-end and back-end tools of the following circuits:

Using Xilinx ISE front-end software (using VHDL only)

Combinational logic:

4-bit parallel adder

4-bit serial adder

Parallel multipliers

Multiply Accumulate unit

Sequential logic:

Multi-bit pre-settable, up/down counters

FIFO buffer

Sequence detectors

Real-time Clock

Using Microwind /Tanner back-end software:

4-bit parallel adder

4-bit serial adder

4-bit pre-settable, up/down counters

16 byte FIFO buffer

3-bit Sequence detectors

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ANE504 ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS3 1 0 4

UNIT I 9MODELS FOR INTEGRATED CIRCUIT ACTIVE DEVICESDepletion region of a PN junction large signal behavior of bipolar transistors- small

signal model of bipolar transistor- large signal behavior of MOSFET- small signal modelof the MOS transistors- short channel effects in MOS transistors weak inversion inMOS transistors- substrate current flow in MOS transistor.

UNIT II 9CIRCUIT CONFIGURATION FOR LINEAR ICCurrent mirrors using BJT, Analysis of difference amplifiers with active load using BJTand FET, supply and temperature independent biasing techniques, voltage references.Output stages: Emitter follower, Push pulls output stages.

UNIT III 9OPERATIONAL AMPLIFIERS

Operational amplifiers with single ended output, Analysis of operational amplifierscircuit, Bi-polar amplifier, Quantitative description of circuit operation, DC analysis of 741 operating amplifier, Small signal analysis of 741 operational amplifiers, Designconsideration of bi-polar, monolithic operating amplifier. Designs of low driftOperational amplifier and low input current operational amplifier. Analysis of frequencyresponse of 741 operating amplifier, high frequency equivalent circuit of 741 op-amp,calculation of -3dB frequency of 741 op-amp, non dominant pole of 741.

UNIT IV 9ANALOG DESIGN WITH MOS TECHNOLOGYMOS Current Mirrors Simple, Cascode, Wilson and Widlar current source Sourcefollower output stage, CMOS Class AB output stages Two stage MOS OperationalAmplifiers, with Cascode, MOS Telescopic-Cascode Operational Amplifier MOSFolded Cascode and MOS Active Cascode Operational Amplifiers

UNIT V 9ANALOG MULTIPLIER AND PLLAnalysis of four quadrant and variable trans conductance multiplier, voltage controlledoscillator, closed loop analysis of PLL, Monolithic PLL design in integrated circuits.Noise In Integrated Circuits -Sources of noise- Noise models of Integrated-circuitComponents Circuit Noise Calculations Equivalent Input Noise Generators NoiseBandwidth Noise Figure and Noise Temperature, Op-amp noise.

Total: 45

TEXT BOOK:

1. Gray, Meyer, Lewis, Hurst, Analysis and design of Analog ICs, Fourth Edition,Willey International, 2002.

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REFERENCES:

1. Behzad Razavi, Principles of data conversion system design, S.Chand and companyltd, 2000

2. Nandita Dasgupata, Amitava Dasgupta,Semiconductor Devices, Modelling and

Technology, Prentice Hall of India Pvt. Ltd, 2004.3. Grebene, Bipolar and MOS Analog Integrated circuit design, John Wiley & sons,Inc., 2003.

4. Phillip E.Allen Douglas R. Holberg, CMOS Analog Circuit Design, SecondEdition- Oxford University Press-2003

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ANE505 COMPUTER ARCHITECTURE AND PARALLEL PROCESSING 3 0 0 3

UNIT I 9PRINCIPLES OF PARALLEL PROCESSINGMultiprocessors and Multicomputers Multivector and SIMD Computers- PRAM and

VLSI Models- Conditions of Parallelism- Program Partitioning and scheduling-programflow mechanisms- parallel processing applications- speed up performance law.

UNIT II 9PROCESSOR AND MEMORY ORGANIZATIONAdvanced processor technology Superscalar and vector processors- Memory hierarchytechnology- Virtual memory technology- Cache memory organization- Shared memoryorganization.

UNIT III 9PIPELINE AND PARALLEL ARCHITECTURE

Linear pipeline processors- Non linear pipeline processors- Instruction pipeline design-Arithmetic design- Superscalar and super pipeline design- Multiprocessor systeminterconnects- Message passing mechanisms.

UNIT IV 9VECTOR, MULTITHREAD AND DATAFLOW ARCHITECTUREVector processing principle- Multivector Multiprocessors- Compound Vector processing-Principles of multithreading- scalable and multithread architectures Dataflow andhybrid architectures.

UNIT V 9SOFTWARE AND PARALLEL PROCESSINGParallel programming models- parallel languages and compilers- parallel programmingenvironments- synchronization and multiprocessing modes- message passing programdevelopment- multiprocessor UNIX design goals- MACH/OS kernel architecture- OSF/1architecture and applications.

Total: 45TEXT BOOK:

1. Kai Hwang, Advanced Computer Architecture, TMH 2001.

REFERENCES:

1. William Stallings, Computer Organization and Architecture, McMillan PublishingCompany, 1990.

2. M.J. Quinn, Designing efficient Algorithms for parallel computer, McGraw HillInternational, 1994.

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ANE506 EMBEDDED SYSTEMS 3 0 0 3 UNIT I 9EMBEDDED ARCHITECTUREEmbedded Computers, Characteristics of Embedded Computing Applications, Embedded

system design process- Requirements, Specification, Architectural Design, DesigningHardware and Software Components, System Integration, Unified modeling language(UML), Formalism for System Design- Structural Description, Behavioral Description,Design Example: Model Train Controller.

UNIT II 9EMBEDDED PROCESSOR AND COMPUTING PLATFORMARM processor- processor and memory organization, Data operations, Flow of Control,SHARC processor- Memory organization, Data operations, Flow of Control, parallelismwith instructions, CPU Bus configuration, ARM Bus, SHARC Bus-Design Example :Alarm Clock.

UNIT III 9NETWORKSDistributed Embedded Architecture- Hardware and Software Architectures, Networks forembedded systems- I2C, CAN Bus, SHARC link ports, Ethernet, Myrinet, Internet,Network-Based design- Communication Analysis, system performance Analysis,Hardware platform design, Allocation and scheduling, Design Examples: ElevatorController, Ink jet printer- Hardware Design and Software Design, Personal DigitalAssistants, Set-top Boxes.

UNIT IV 9REAL-TIME CHARACTERISTICSClock driven Approach, weighted round robin Approach, Priority driven Approach,Dynamic Versus Static systems, effective release times and deadlines, Optimality of theEarliest deadline first (EDF) algorithm, challenges in validating timing constraints inpriority driven systems, Off-line Versus On-line scheduling.

UNIT V 9REAL TIME OPERATING SYSTEMOperating system service-I/O sub system- Network operating systems-Interrupt routinesin RTOS environment- RTOS task scheduling models-interrupts- Performance metric inscheduling models-IEEE standard POSIX functions for standardization of RTOS andinter task communication functions- List of basic function and pre emptive scheduling-fifteen point strategy for synchronization between processors, ISRs, OS functions andtasks Organization OF Vx Works- RTOS programming & Debugging tools- Examplesfor RTOS

Total: 45

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TEXT BOOK:

1. Wayne Wolf, Computers as Components: Principles of Embedded ComputingSystem Design, Morgan Kaufman Publishers, 2001.

2. Rajkamal, Embedded System Architecture Programming and Design Tata

McGraw- Hill, First reprint, 2003

REFERENCES:

1. Jane.W.S. Liu ,Real-Time systems, Pearson Education Asia, 2000.2. C. M. Krishna and K. G. Shin, Real-Time Systems, McGraw-Hill, 1997.3. Frank Vahid and Tony Givargi Embedded System Design: A Unified

Hardware/Software Introduction, s, John Wiley & Sons, 2000.

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ANE507 ASIC DESIGN 3 0 0 3

UNIT I 9INTRODUCTION TO ASICS, CMOS LOGIC AND ASIC LIBRARY DESIGNTypes of ASICs - Design flow - Combinational Logic Cell Sequential logic cell - Data

path logic cell - Transistors as Resistors - Transistor Parasitic Capacitance- Logical effortLibrary cell design - Library architecture.

UNIT II 9 PROGRAMMABLE ASICS, PROGRAMMABLE ASIC LOGIC CELLS ANDPROGRAMMABLE ASIC I/O CELLSAnti fuse -Static RAM - EPROM and EEPROM technology - PREP benchmarks - ActelACT - Xilinx LCA Altera FLEX - Altera MAX - DC & AC inputs and outputs - Clock & Power inputs - Xilinx I/O blocks.

UNIT III 9

PROGRAMMABLE ASIC INTERCONNECT, PROGRAMMABLE ASIC DESIGNSOFTWARE AND LOW LEVEL DESIGN ENTRYActel ACT - Xilinx LCA - Xilinx EPLD - Altera MAX 5000 Altera FLEX Designsystems - Schematic entry - Low level design language - EDIF- CFI designrepresentation.

UNIT IV 9LOGIC SYNTHESIS, SIMULATIONLogic synthesis -Logic synthesis - Examples for simple combinational logic andsequential logic circuits using VHDL

UNIT V 9SIMULATION AND FAULT ANALYSISTypes of simulation Types of faults - Fault models D-calculus- Fault simulation LFSR - Signature analysis Built in self test - Automatic test pattern generationalgorithms.

Total: 45TEXT BOOK:1. M.J.S .Smith, "Application Specific Integrated Circuits, Addison Wesley Longman

Inc., 1997.

REFERENCES

1. Farzad Nekoogar and Faranak Nekoogar, From ASICs to SOCs: A PracticalApproach, Prentice Hall PTR, 2003.

2. Wayne Wolf, FPGA-Based System Design, Prentice Hall PTR, 2004.3. R. Rajsuman and Santa Clara, System-on-a-Chip Design and Test, CA: Artech

House Publishers, 2000.4. F. Nekoogar, Timing Verification of Application-Specific Integrated Circuits

(ASICs), Prentice Hall PTR, 1999.

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ANE702 ELECTRONIC SYSTEM DESIGN PROJECT 0 0 3 1

RULES AND REGULATIONS

There shall be three reviews during the course of the semester. The students are required to submit a report (not exceeding 25 pages) in the

prescribed format at the end of the semester. The work shall be carried out in the department only. There shall be a supervisor for each student, and also an internal committee

comprising of the following members to monitor the progress of the mini project : HOD Course Coordinator Project Coordinator Class Advisor Project Guide

There shall be 50 marks for internal evaluation and 50 marks for externalevaluation (Total: 100 marks).

The internal marks distribution for the mini project is as below:

Reviews : 30 (minimum of three with 10 marks each)Attendance : 5Report : 15--------------------------Total : 50

--------------------------

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ANE524 RESEARCH METHODOLOGY 2 0 0 2

UNIT IRESEARCH CONCEPTS 6 Concepts, meaning, objectives, motivation, types of research, approaches, research(Descriptive research, Conceptual, Theoretical, Applied & Experimental).

Formulation of Research Task Literature Review, Importance & Methods, Sources,quantification of Cause Effect Relations, Discussions, Field Study, Critical Analysis of Generated Facts, Hypothetical proposals for future development and testing, selection of Research task.

UNIT II MATHEMATICAL MODELING AND SIMULATION 6Concepts of modeling, Classification of Mathematical Models, Modeling with Ordinarydifferential Equations, Difference Equations, Partial Differential equations, Graphs,Simulation, Process of formulation of Model based on Simulation.

UNIT IIIEXPERIMENTAL MODELING 6Definition of Experimental Design, Examples, Single factor Experiments, Guidelines fordesigning experiments. Process Optimization and Designed experiments, Methods forstudy of response surface, determining optimum combination of factors, Taguchiapproach to parameter design.

UNIT IVANALYSIS OF RESULTS 6Parametric and Non-parametric, descriptive and Inferential data, types of data, collectionof data (normal distribution, calculation of correlation coefficient), processing, analysis,

error analysis, different methods, analysis of variance, significance of variance, analysisof covariance, multiple regression, testing linearity and non-linearity of model.

UNITVREPORT WRITING 6Types of reports, layout of research report, interpretation of results, style manual, layoutand format, style of writing, typing, references, tables, figures, conclusion, appendices.

Total : 30REFERENCES

1. R. Panneerselvam, Reseach Methodology, PHI 2004.2. Douglas Montgomary, Design of Experiments, Statistical Consulting Services, 1990.3. Douglas H. W. Allan, Statistical Quality Control: An Introduction for Management,

Reinhold Pub Corp, 1959.4. Cochran and Cox, Experimental Design, John Willy & Sons, 2 nd Edition , May 19925. S. S. Rao, Optimization Theory and Application, Wiley Eastern Ltd., New Delhi,

1996.6. C. R. Kothari, Research Methodology, New Age Publishers, 2005.

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ANE508 DIGITAL IMAGE PROCESSING 3 0 0 3

UNIT I 9DIGITAL IMAGE FUNDAMENTALSElements of digital image processing systems, Elements of visual perception, Imagesampling, Quantization, Mathematical representation of quantization, psycho visualmodel, brightness, contrast, hue, saturation, mach band effect, Color image fundamentals-RGB,HSI models, Psychovisual model.

UNIT II 9IMAGE TRANSFORMS 1D DFT, 2D transforms DFT, DCT, Walsh-Hadamard, Slant, KLT, WaveletTransform- Properties of transforms.

UNIT III 9IMAGE ENHANCEMENT AND RESTORATIONHistogram modification and specification techniques, Noise distributions, Spatialaveraging, Directional Smoothing, Median, Geometric mean, Harmonic mean,

Contraharmonic and Yp mean filters, Homomorphic filtering, Color image enhancement.Image Restoration degradation model, Unconstrained and Constrained restoration,Inverse filtering removal of blur caused by uniform linear motion, Wiener filtering,Geometric transformations spatial transformations, Gray-Level interpolation.

UNIT IV 9IMAGE SEGMENTATION AND RECOGNITIONEdge detection. Image segmentation by region growing, region splitting and merging,edge linking.. Image Recognition Patterns and pattern classes, Matching by minimumdistance classifier, Matching by correlation, Back Propagation Neural Network, NeuralNetwork applications in Image Processing.

UNIT V 9APPLICATIONS IN IMAGE PROCESSINGNeed for Data compression- Huffman, Run length encoding, Arithmetic coding, Vector

Quantization, Transform Coding - DCT Wavelet, JPEG, MPEG standards-Noise, Typesof Noise in image, transmission effects, quantization effects, noise model, DenoisingTechniques.

Total: 45TEXT BOOK:1. Rafael C. Gonzalez, Richard E.Woods, Digital Image Processing, Pearson

Education, Inc., Second Edition, 2004.

REFERENCES: 1. David Salomon ,Data Compression The Complete Reference, Springer Verlag

New York Inc., 2 nd Edition, 20012. Rafael C. Gonzalez, Richard E.Woods, Steven Eddins, Digital Image Processing

using MATLAB, Pearson Education, Inc., 2004.3. William K.Pratt, Digital Image Processing, John Wiley, New York, 2002.4. Milman Sonka, Vaclav Hlavac, Roger Boyle, Image Processing, Analysis, and

Machine Vision, Brooks/Cole, Vikas Publishing House, II ed., 1999.

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ANE509 NEURAL NETWORKS AND APPLICATIONS 3 0 0 3

UNIT I 9BASIC LEARNING ALGORITHMSBiological Neuron Artificial Neural Model - Types of activation functions

Architecture: Feed forward and Feedback Learning Process: Error Correction LearningMemory Based Learning Hebbian Learning Competitive Learning - BoltzmanLearning Supervised and Unsupervised Learning Pattern Space Weight Space Learning Tasks: Pattern Association Pattern Recognition Function Approximation Control Filtering - Beamforming Memory Single Layer Perceptron PerceptronLearning Algorithm Perceptron Convergence Theorem Least Mean Square LearningAlgorithm Multilayer Perceptron Back Propagation Algorithm XOR problem Limitations of Back Propagation Algorithm.

UNIT II 9RADIAL-BASIS FUNCTION NETWORKS AND SUPPORT VECTOR

MACHINES:RADIAL BASIS FUNCTION NETWORKS:Covers Theorem on the Separability of Patterns - Exact Interpolator Generalized RadialBasis Function Networks - Learning in Radial Basis Function Networks - Applications:XOR Problem Image Classification. Support Vector Machines: Optimal Hyper-planefor Linearly Separable Patterns and Non- Separable Patterns Support Vector Machinefor Pattern Recognition XOR Problem - -insensitive Loss Function Support VectorMachines for Nonlinear Regression

UNIT III 9COMMITTEE MACHINES:

Ensemble Averaging - Boosting Associative Gaussian Mixture Model HierarchicalMixture of Experts Model (HME) Model Selection using a Standard Decision Tree APriori and Postpriori Probabilities Maximum Likelihood EstimationNEURODYNAMICS SYSTEMS:Dynamical Systems Attractors and Stability Non-linear Dynamical Systems-Lyapunov Stability Neuro Dynamical Systems The Cohen- Grossberg Theorem.

UNIT IV 9ATTRACTOR NEURAL NETWORKS:Associative Learning Attractor Neural Network Associative Memory Linear

Associative Memory Hopfield Network Content Addressable Memory Strange

Attractors and Chaos - Error Performance of Hopfield Networks Simulated Annealing Bidirectional Associative Memory BAM Stability Analysis Error Correction inBAMs -Continuous BAMs Adaptive BAMs ApplicationsADAPTIVE RESONANCE THEORY:Noise-Saturation Dilemma - Solving Noise-Saturation Dilemma Building Blocks of

Adaptive Resonance Substrate of Resonance Structural Details of Resonance Model Adaptive Resonance Theory Applications

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UNIT V 9SELF ORGANISING MAPS:Self-organizing Map Maximal Eigenvector Filtering Sangers Rule GeneralizedLearning Law Competitive Learning - Vector Quantization Mexican Hat Networks -Self-organizing Feature Maps Applications

PULSED NEURON MODELS:Spiking Neuron Model Integrate-and-Fire Neurons Conductance Based Models Computing with Spiking Neurons.

Total: 45TEXT BOOK:

1. Satish Kumar, Neural Networks: A Classroom Approach, Tata McGraw- HillPublishing Company Limited, New Delhi, 2004.

2. Simon Haykin, Neural Networks: A Comprehensive Foundation, 2ed, AddisonWesley Longman (Singapore) Private Limited, Delhi, 2005.

REFERENCES:1. Martin T.Hagan, Howard B. Demuth, and Mark Beale, Neural Network Design,

Thomson Learning, New Delhi, 2003.2. James A. Freeman and David M. Skapura, Neural Networks Algorithms,

Applications, and Programming Techniques, Pearson Education (Singapore) PrivateLimited, Delhi, 2003.

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ANE510 LOW POWER VLSI DESIGN 3 0 0 3

UNIT I 9POWER DISSIPATION IN CMOSHierarchy of limits of power Sources of power consumption Physics of power

dissipation in CMOS FET devices- Basic principle of low power design.

UNIT IIPOWER ESTIMATION 9Power estimation techniques Logic level power estimation Simulation power analysis Probabilistic power analysis.

UNIT IIIPOWER OPTIMIZATION 9Logical level power optimization Circuit level low power design Circuit techniquesfor reducing power consumption in adders and multipliers.

UNIT IV 9 DESIGN OF LOW POWER CMOS CIRCUITSComputer Arithmetic techniques for low power systems Reducing power consumptionin memories Low power clock, Interconnect and layout design Advanced techniques Special techniques.

UNIT V 9SYNTHESIS AND SOFTWARE DESIGN FOR LOW POWERSynthesis for low power Software of low power- Software for Power optimizationBehavioral level transforms- Software design for low power co design for low power.

Total: 45TEXT BOOK:

1. K.Roy and S.C. Prasad , LOW POWER CMOS VLSI circuit design,Wiley,2000

REFERENCES:

1. Dimitrios Soudris, Chirstian Pignet, Costas Goutis, DESIGNING CMOS CIRCUITSFOR LOW POWER, Kluwer,2002

2. J.B. Kuo and J.H Lou, Low voltage CMOS VLSI Circuits, Wiley 1999.3. A.P.Chandrakasan and R.W. Broadersen, Low power digital CMOS design,

Kluwer, 1995.4. Gary Yeap, Practical low power digital VLSI design, Kluwer, 1998.5. Abdellatif Bellaouar, Mohamed.I. Elmasry, Low power digital VLSI Design,

Kluwer, 1995.6. James B. Kuo, Shin chia Lin, Low voltage SOI CMOS VLSI Devices and

Circuits, John Wiley and sons, inc 2001

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ANE511 DSP INTEGRATED CIRCUITS 3 0 0 3

UNIT I 9NUMBER SYSTEMS, ARITHMETIC UNITS AND INTEGARTED CIRCUITDESIGN Conventional number system, Redundant Number system, Residue Number System .Bit-parallel and Bit-Serial arithmetic, Basic shift accumulator, Reducing the memory size,Complex multipliers, Improved shift-Accumulator.

UNIT II 9 DIGITAL SIGNAL PROCESSINGDigital signal processing, Sampling of analog signals, Selection of sample frequency,Signal-processing systems, Frequency response, Transfer functions, Signal flow graphs,Filter structures, Adaptive DSP algorithms, FFT-The Fast Fourier Transform Algorithm,Image coding, Discrete cosine transforms.

UNIT III 9DIGITAL FILTERS AND FINITE WORD LENGTH EFFECTSFIR filters, FIR filter structures, FIR chips, IIR filters, Specifications of IIR filters, Multi-rate systems, Interpolation with an integer factor L, Sampling rate change with a ratioL/M, Multirate filters. Finite word length effects -Parasitic oscillations, Scaling of signallevels, Round-off noise, Measuring round-off noise, Coefficient sensitivity, Sensitivityand noise.

UNIT IV 9DSP INTEGARTED CIRCUITS AND VLSI CIRCUIT TECHNOLOGIESStandard digital signal processors, Application specific ICs for DSP, DSP systems, DSPsystem design, Integrated circuit design. MOS transistors, MOS logic, VLSI processtechnologies, Trends in CMOS technologies.

UNIT V 9DSP ARCHITECTURES AND SYNTHESIS OF DSP ARCHITECTURESDSP system architectures, Standard DSP architecture, Ideal DSP architectures,

Multiprocessors and multi computers, Systolic and Wave front arrays, Shared memoryarchitectures. Mapping of DSP algorithms onto hardware, Implementation based oncomplex PEs, Shared memory architecture with Bit serial PEs, Layout of VLSI circuits,FFT processor, DCT processor and Interpolator as case studies.

Total: 45TEXT BOOK:

1. Lars Wanhammer, DSP INTEGRATED CIRCUITS , Academic press, New York 1999.

REFERENCES:1. A.V.Oppenheim et.al, Discrete-time Signal Processing Pearson education, 2000.2. Emmanuel C. Ifeachor, Barrie W. Jervis, Digital signal processing A practical

approach , 2nd edition, Prentice Hall, 2001.3. Keshab K.Parhi, VLSI digital Signal Processing Systems design and

Implementation John Wiley & Sons, 1999.

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ANE512 DIGITAL CONTROL ENGINEERING 3 0 0 3

UNIT I 9INTRODUCTION TO DISCRETE TIME SYSTEMSIntroduction discrete systems, Transform methods, properties of Z transform, Solution of difference equation, Inverse Z transform, Simulation Diagram and flow Graphs, Sampled

Data control systems, Ideal Sampler, Evaluation of E*(S),Results from the FourierTransform, Properties of E*(S),Data Reconstruction, Digital to Analog Conversion ,Analog to Digital Conversion.

UNIT II 9STATE SPACE ANALYSISState space representation of discrete time system, solving discrete time space equation,Pulse transfer function matrix, Continuous time state space equation, Discretization of continuous time state space equation, controllability, observability, useful transformationin state space analysis and design.

UNIT III 9

DESIGN IF DISCRETE TIME CONTROL SYSTEM VIA TRANSFORMMETHODSIntroduction, Obtaining discrete time equivalent of continuous time filter, Discretizing asimple continuous time filter, Backward difference method, Bilinear transformationmethod, Bilinear transformation method with frequency and prewarping, Impulseinvariance method, Step invariance method, matched pole Zero mapping method,Design principle based on a discrete time equivalent of an analog controller.

UNIT IV 9TIME RESPONSE AND STABILITY ANALYSIS OF DISCRETE TIMESYSTEMTransient analysis and steady state response analysis, transient response specification forsecond order continuous time system, relationship between Z plane pole and zerolocation and transient response, steady state error analysis is designed based on root locusmethod, design based on the frequency response method , Bode Diagrams., Stability-Bilinear transformation , Routht Hurwitz criterian, Juriss stability test.

UNIT V 9DIGITAL CONTROLLER DESIGNControl system specification, Compensation, Phase lag compensation, Phase leadcompensation, Design procedure using Bode plot, Integration and Differentiation, DigitalDIP controllers.

Total : 45

TEXT BOOK:1. Katsuhiko Ogata, Discrete Time Control System, Prentice Hall.inc, 1987.

REFERENCES:1. Charles .L Phillips and H.Troy Nagle,Digital control system analysis and design

Third Edition ,Prentice Hall International Edition.2. M.Gopal Digital control and state variable methods,Tata McGraw publication

company limited.

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ANE513 DESIGN AND ANALYSIS OF ALGORITHMS 3 0 0 3 UNIT I 9INTRODUCTIONPolynomial and Exponential algorithms, big "oh" and small "oh" notation, exact

algorithms and heuristics, direct / indirect / deterministic algorithms, static and dynamiccomplexity, stepwise refinement.

UNIT II 9 DESIGN TECHNIQUESSubgoals method, working backwards, work tracking, branch and bound algorithms fortraveling salesman problem and knapsack problem, hill climbing techniques, divide andconquer method, dynamic programming, greedy methods.

UNIT III 9SEARCHING AND SORTING

Sequential search, binary search, block search, Fibonacci search, bubble sort, bucketsorting, quick sort, heap sort, average case and worst case behavior, FFT.

UNIT IV 9GRAPH ALGORITHMSMinimum spanning, tree, shortest path algorithms, R-connected graphs, Even's andKleitman's algorithms, ax-flow min cut theorem, Steiglitz's link deficit algorithm.

UNIT V 9SPECIAL ALGORITHMSNP Completeness Approximation Algorithms, NP Hard Problems, Strasseu's MatrixMultiplication Algorithms, Magic Squares, Introduction To Parallel Algorithms andGenetic Algorithms, Monti-Carlo Methods, Amortised Analysis.

Total : 45TEXT BOOK:

1. Sara Baase, "Computer Algorithms: Introduction to Design and Analysis", AddisonWesley, 1988.

REFERENCES

1. T.H.Corman, C.E.Leiserson and R.L.Rioest, "Introduction to Algorithms", Mc GrawHill, 1994.

2. E.Horowitz and S.Sahni, "Fundamentals of Computer Algorithms", GalgotiaPublications, 1988.

3. D.E.Goldberg, "Genetic Algorithms: Search Optimization and Machine Learning",Addison Wesley, 1989.

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COM517 SOFT COMPUTING 3 0 0 3

UNIT I 9ARTIFICIAL NEURAL NETWORKSSupervised learning Neural networks-Introduction, Perception- Adaline, Back

propagation- Multi layer perception- Unsupervised learning and other Neural networks-Introduction, Competitive learning networks, Kolonen self organizing networks,Learning vector quantization, Hebbian learning, Hopfield network , Content addressablenature, Binary Hopfield network, Continuous-valued Hopfield network , TravellingSalesperson problem.

UNIT II 9FUZZY SET THEORYFuzzy sets, Basic definitions and terminology, Member function formulation &parameterization, Fuzzy rules , fuzzy reasoning - Extension principle, Fuzzy relation,Fuzzy inference systems: Mamdani model, Sugeno model. Tsukamoto model, Input

space partitioning, Fuzzy modeling.UNIT III 9OPTIMIZATIONDerivative based optimization-Descent methods, Method of steepest descent, ClassicalNewtons method, Step-size determination; Derivative free optimization- Geneticalgorithm, Simulated annealing, Random search, Downhill search.

UNIT IV 9ADVANCED NEURO-FUZZY MODELLINGClassification and regression trees: decision tress, Cart algorithm Data clusteringalgorithms: K means clustering, Fuzzy C means clustering, Mountain clustering,Subtractive clustering rule base structure , Input space partitioning, rule basedorganization, focus set based rule combination; Neuro fuzzy control: Feedback ControlSystems, Expert Control, Inverse Learning, Specialized Learning, Back propagationthrough Real Time Recurrent Learning.

UNIT V 9GENETIC ALGORITHMFundamentals of genetic algorithm- Basic concepts, creation of offsprings, Workingprinciple , Encoding Binary, Octal , Hex, Permutation, Value and tree, Reproduction-Roulette-wheel selection, Boltzman selection, Tournament selection, Rank selection,Steady state selection, Crossover single site, Two point, Multi point, Uniform and matrix,Crossover rate, Inversion , Deletion and duplication ,Deletion and Regeneration,Segregation, Crossover, Mutation, Generational cycle.

Total: 45TEXT BOOK:

1. Jang J.S.R.,Sun C.T and Mizutani E Neuro Fuzzy and Soft computing, Pearsoneducation (Singapore) 2004.

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REFERENCES:

1. S.Rajasekaran and G.A.Vijayalakshmi Pai Neural networks, Fuzzy logics, andGenetic algorithms, Prentice Hall of India,2003.

2. David E.Goldberg : Genetic Algorithms in Search, Optimization, and Machine

Learning, Pearson Education, Asia,19963. Laurene Fauseett: Fundamentals of Neural Networks, Prentice Hall India, NewDelhi, 1994.

4. Timothy J.Ross: Fuzzy Logic Engineering Applications, McGraw Hill, New York,1997.

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COM 519 INTERNETWORKING MULTIMEDIA 3 0 0 3

UNIT I 9MULTIMEDIA NETWORKINGDigital sound, video and graphics, basic multimedia networking, multimedia

characteristics, evolution of Internet services model, network requirements for audio/ video transform, multimedia coding and compression for text, image, audio and video.

UNIT II 9BROADBAND NETWORK TECHNOLOGYBroadband services, ATM and IP, IPV6, High speed switching, resource reservation,Buffer management, traffic shaping, caching, scheduling, and policing, throughput, delayand jitter performance. Storage and media services, voice and video over IP, MPEG-2over ATM/IP, indexing synchronization of requests, recording and remote control.

UNIT III 9

RELIABLE TRANSPORT PROTOCOL AND APPLICATIONSMulticast over shared media network, multicast routing and addressing, scaling multicastand NBMA networks, Reliable transport protocols, TCP adaptation algorithm, RTP,RTCP. MIME, Peer- to-Peer computing, shared application, video conferencing,centralized and distributed conference control, distributed virtual reality, light weightsession philosophy.

UNIT IV 9MULTIMEDIA COMMUNICATION STANDARDSObjective of MPEG- 7 standard, Functionalities and systems of MPEG-7, MPEG-21Multimedia Framework Architecture, - Content representation, Content Management andusage, Intellectual property management, Audio visual system- H322: Guaranteed QOSLAN systems; MPEG_4 video Transport across internet.

UNIT V 9MULTIMEDIA COMMUNICATION ACROSS NETWORKSPacket Audio/video in the network environment, video transport across Genericnetworks- Layered video coding, error Resilient video coding techniques, Scalable Ratecontrol, Streaming video across Internet, Multimedia transport across ATM networks andIP network, Multimedia across wireless networks.

Total : 45TEXT BOOK: 1. Jon Crowcroft, Mark Handley, Ian Wakeman, Internetworking Multimedia, Harcourt

Asia Pvt. Ltd. Singapore, 1998.

REFERENCES:1. B.O. Szuprowicz, Multimedia Networking, McGraw Hill, Newyork. 19952. Tay Vaughan, Multimedia - Making it to work, 4ed, Tata McGraw Hill , New Delhi,

2000.3. K.R.Rao, Zoran S. Bojkovic and Dragorad A. Milovanovic, Multimedia

Communication systems, PHI , 2003

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ANE514 DSP PROCESSOR ARCHITECTURE AND PROGRAMMING 3 0 0 3

UNIT I 9FUNDAMENTALS OF PROGRAMMABLE DSPsMultiplier and Multiplier accumulator Modified Bus Structures and Memory access in

P-DSPs Multiple access memory Multi-port memory VLIW architecture- Pipelining Special Addressing modes in P-DSPs On chip Peripherals.

UNIT II 9 TMS320C5X PROCESSORArchitecture Assembly language syntax - Addressing modes Assembly languageInstructions - Pipeline structure, Operation Block Diagram of DSP starter kit Application Programs for processing real time signals.

UNIT III 9TMS320C3X PROCESSOR

Architecture Data formats - Addressing modes Groups of addressing modes-Instruction sets - Operation Block Diagram of DSP starter kit Application Programsfor processing real time signals Generating and finding the sum of series, Convolutionof two sequences, Filter design Introduction to code composer studio

UNIT IV 9ADSP PROCESSORSArchitecture of ADSP-21XX and ADSP-210XX series of DSP processors- Addressingmodes and assembly language instructions Application programs Filter design, FFTcalculation.

UNIT V 9ADVANCED DSP PROCESSORSArchitecture of TMS320C54X: Pipe line operation, Code Composer studio - Architectureof TMS320C6X - Architecture of Motorola DSP563XX Comparison of the features of DSP family processors .

Total : 45

TEXT BOOK:

1. B.Venkataramani and M.Bhaskar, Digital Signal Processors Architecture,Programming and Applications Tata McGraw Hill Publishing Company Limited.New Delhi, 2003.

REFERENCES:

1. User guides Texas Instrumentation, Analog Devices, Motorola.

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COM521 HIGH PERFORMANCE COMMUNICATION NETWORKS 3 0 0 3

UNIT I 9PACKET SWITCHED NETWORKSOSI and IP models, Ethernet (IEEE 802.3), Token ring (IEEE 802.5), Wireless LAN(IEEE 802.11) FDDI, DQDB, SMDS: Internetworking with SMDS

UNIT II 9ISDN AND BROADBAND ISDNISDN - overview, interfaces and functions, Layers and services - Signaling System 7(SS7)- Broadband ISDN architecture and Protocols.

UNIT III 9ATM AND FRAME RELAYATM: Main features-addressing, signaling and routing, ATM header structure-adaptationlayer, management and control, ATM switching and transmission.Frame Relay: Protocols and services, Congestion control, Internetworking with ATM,Internet and ATM, Frame relay via ATM.

UNIT IV 9ADVANCED NETWORK ARCHITECTUREIP forwarding architectures overlay model, Multi Protocol Label Switching (MPLS),integrated services in the Internet, Resource Reservation Protocol (RSVP), DifferentiatedServices

UNIT V 9BLUE TOOTH TECHNOLOGYThe Blue tooth module-Protocol stack Part I: Antennas, Radio interface, Base band, TheLink controller, Audio, The Link Manager, The Host controller interface; The Blue toothmodule-Protocol stack Part I: Logical link control and adaptation protocol, RFCOMM,Service discovery protocol, Wireless access protocol, Telephony control protocol.


1. Jean Walrand and Pravin varaiya ,High Performance Communication networks,2ndedition, Harcourt and Morgan Kauffman,London,2000.

REFERENCES:

1. William Stallings,ISDN and Broadband ISDN with Frame Relay and ATM, 4 th edition, Pearson education Asia, 2002.

2.

Leon Gracia, Widjaja, Communication networks ", Tata McGraw-Hill, New Delhi,2000.3. Jennifer Bray and Charles F.Sturman,Blue Tooth Pearson education Asia, 2001.4. Sumit Kasera, Pankaj Sethi, ATM Networks ", Tata McGraw-Hill, New Delhi, 2000.5. Rainer Handel, Manfred N.Huber and Stefan Schroder ,ATM Networks,3 rd edition,

Pearson education asia,2002.6. C.Siva Ram Murthy and B.S.Manoj AdHoc Wireless Networks Architecture and

protocols ,Pearson Education ,First Indian Reprint 2005

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COM522 HIGH SPEED SWITCHING ARCHITECTURE 3 0 0 3

UNIT I 9HIGH SPEED NETWORK:Introduction- LAN, WAN, Network evolution through ISDN to B-ISDN, Transfer mode

and control of B-ISDN, SDH multiplexing structure, ATM standard, ATM adaptationlayers.

UNIT II 9LAN SWITCHING TECHNOLOGY:Switching Concepts, switch forwarding techniques, switch path control, LAN Switching,cut through forwarding, store and forward, virtual LANs

UNIT III 9ATM SWITCHING ARCHITECTURESwitch model, ATM,QOS,Blocking networks - basic - and- enhanced banyan networks,

sorting networks - merge sorting, re-arrangable networks - full-and- partial connectionnetworks, non blocking networks - Recursive network construction, comparison of non-blocking network, Switching with deflection routing - shuffle switch, tandem banyan

UNIT IV 9QUEUES IN ATM SWITCHESInternal Queueing -Input, output and shared queueing, multiple queueing networks combined Input, output and shared queueing - performance analysis of Queued switches.

UNIT V 9IP SWITCHINGAddressing model, IP Switching types - flow driven and topology driven solutions, IPOver ATM address and next hop resolution, multicasting, Photonic switching - Photonicswitching architectures.

Total : 45

TEXT BOOK:1. Achille Pattavina, Swtching Theory: Architectures and performance in Broadband

ATM networks "John Wiley & Sons Ltd, New York. 1998.

REFERENCES:

1. Christopher Y Metz, Switching protocols & Architectures, McGraw HillProfessional Publishing, NewYork.1998.

2. Rainer Handel, Manfred N Huber, Stefan Schroder, ATM Networks ConceptsProtocols, Applications III Edition, Addison Wesley, New York. 1999.

3. John A.Chiong: Internetworking ATM for the internet and enterprise networks.McGraw Hill, New York, 1998.

4. S.Kar and T.Srinivas, Optical fiber communications ,Priniciples and Practice,TatavMc Graw Hill ,2002.

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ANE515 ADVANCED PROCESSORS 3 0 0 3

UNIT I 9MICROPROCESSOR ARCHITECTUREInstruction set Data formats Instruction formats Addressing modes Memory

hierarchy register file Cache Virtual memory and paging Segmentation Pipelining The instruction pipeline pipeline hazards Instruction level parallelism reduced instruction set Computer principles RISC versus CISC RISC properties RISC evaluation.UNIT II 9HIGH PERFORMANCE CISC ARCHITECTURE PENTIUMThe software model functional description CPU pin descriptions Addressing modes Processor flags Instruction set Bus operations Super scalar architecture Pipelining Branch prediction The instruction and caches Floating point unitProgramming the Pentium processor.

UNIT III 9HIGH PERFORMANCE CISC ARCHITECTURE PENTIUM INTERFACEProtected mode operation Segmentation paging Protection multitasking Exception and interrupts - Input /Output Virtual 8086 model Interrupt processing.

UNIT IV 9HIGH PERFORMANCE RISC ARCHITECTURE: ARM

The ARM architecture ARM assembly language program ARM organization andimplementation The ARM instruction set - The thumb instruction set.

UNIT V 9SPECIAL PURPOSE PROCESSORSAltera Cyclone Processor Audio codec Video codec design Platforms Generalpurpose processor Digital signal processor Embedded processor Media Processor Video signal Processor Custom Hardware Co-Processor.


1. Daniel Tabak, Advanced Microprocessors McGraw Hill.Inc., 1995.2. James L. Antonakos, The Pentium Microprocessor , Pearson Education, 1997.

REFERENCES:

1. Steve Furber, ARM System On Chip architecture Addison Wesley, 2000.2. Gene .H.Miller. Micro Computer Engineering, Pearson Education, 2003.3. Barry.B.Brey, The Intel Microprocessors Architecture, Programming and

Interfacing , PHI, 2002.4. Valvano "Embedded Microcomputer Systems" Thomson Asia PVT LTD first reprints

2001.5. Iain E.G.Richardson, Video codec design, John Wiley & sons Ltd, U.K, 2002

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ANE516 VLSI SIGNAL PROCESSING 3 0 0 3

UNIT I 9INTRODUCTION TO DSP SYSTEMSIntroduction To DSP Systems -Typical DSP algorithms; Iteration Bound data flowgraph representations, loop bound and iteration bound, Longest path Matrix algorithm;Pipelining and parallel processing Pipelining of FIR digital filters, parallel processing,pipelining and parallel processing for low power.

UNIT II 9 RETIMINGRetiming - definitions and properties; Unfolding an algorithm for Unfolding, propertiesof unfolding, sample period reduction and parallel processing application; Algorithmicstrength reduction in filters and transforms 2-parallel FIR filter, 2-parallel fast FIRfilter, DCT algorithm architecture transformation, parallel architectures for rank-orderfilters, Odd- Even Merge- Sort architecture, parallel rank-order filters.

UNIT III 9FAST CONVOLUTIONFast convolution Cook-Toom algorithm, modified Cook-Took algorithm; Pipelined andparallel recursive and adaptive filters inefficient/efficient single channel interleaving,Look- Ahead pipelining in first- order IIR filters, Look-Ahead pipelining with power-of-two decomposition, Clustered Look-Ahead pipelining, parallel processing of IIR filters,combined pipelining and parallel processing of IIR filters, pipelined adaptive digitalfilters, relaxed look-ahead, pipelined LMS adaptive filter.

UNIT IV 9BIT-LEVEL ARITHMETIC ARCHITECTURESScaling and roundoff noise- scaling operation, roundoff noise, state variable descriptionof digital filters, scaling and roundoff noise computation, roundoff noise in pipelinedfirst-order filters; Bit-Level Arithmetic Architectures- parallel multipliers with signextension, parallel carry-ripple array multipliers, parallel carry-save multiplier, 4x 4 bitBaugh- Wooley carry-save multiplication tabular form and implementation, design of Lyons bit-serial multipliers using Horners rule, bit-serial FIR filter, CSD representation,CSD multiplication using Horners rule for precision improvement.

UNIT V 9PROGRAMMING DIGITAL SIGNAL PROCESSORSNumerical Strength Reduction sub expression elimination, multiple constantmultiplications, iterative matching. Linear transformations; Synchronous, Wave andasynchronous pipelining- synchronous pipelining and clocking styles, clock skew inedge-triggered single-phase clocking, two-phase clocking, wave pipelining, asynchronouspipelining bundled data versus dual rail protocol; Programming Digital Signal Processors general architecture with important features; Low power Design needs for low powerVLSI chips, charging and discharging capacitance, short-circuit current of an inverter,CMOS leakage current, basic principles of low power design.

Total : 45

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TEXT BOOK:

1. Keshab K.Parhi, VLSI Digital Signal Processing systems, Design andimplementation, Wiley, Inter Science, 1999.

REFERENCES:

1. Gary Yeap, Practical Low Power Digital VLSI Design, Kluwer AcademicPublishers, 1998.

2. Mohammed Isamail and Terri Fiez, Analog VLSI Signal and InformationProcessing, Mc Graw-Hill, 1994.

3. S.Y. Kung, H.J. White House, T. Kailath, VLSI and Modern Signal Processing,Prentice Hall, 1985.

4. Jose E. France, Yannis Tsividis, Design of Analog - Digital VLSI Circuits forTelecommunication and Signal Processing, Prentice Hall, 1994.

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ANE517 ANALOG VLSI DESIGN 3 0 0 3

UNIT I 9BASIC CMOS CIRCUIT TECHNIQUES, CONTINUOUS TIME AND LOW-VOLTAGESIGNAL PROCESSING:

Mixed-Signal VLSI Chips-Basic CMOS Circuits-Basic Gain Stage-Gain BoostingTechniques-Super MOSTransistor- Primitive Analog Cells-Linear Voltage-CurrentConverters-MOS Multipliers and Resistors-CMOS,Bipolar and Low-Voltage BiCMOSOp-Amp Design-Instrumentation Amplifier Design-Low Voltage Filters.

UNIT II 9 BASIC BICMOS CIRCUIT TECHNIQUES, CURRENT -MODE SIGNALPROCESSING AND NEURAL INFORMATION PROCESSINGContinuous-Time Signal Processing-Sampled-Data Signal Processing-Switched-CurrentData Converters-Practical Considerations in SI Circuits Biologically-Inspired NeuralNetworks - Floating - Gate, Low-Power Neural Networks-CMOS Technology and

Models-Design Methodology-Networks-Contrast Sensitive Silicon Retina.UNIT III 9SAMPLED-DATA ANALOG FILTERS, OVER SAMPLED A/D CONVERTERSAND ANALOG INTEGRATED SENSORSFirst-order and Second SC Circuits-Bilinear Transformation - Cascade Design-Switched-Capacitor Ladder Filter-Synthesis of Switched-Current Filter- Nyquist rate A/DConverters-Modulators for Over sampled A/D Conversion-First and Second Order andMultibit Sigma-Delta Modulators-Interpolative Modulators Cascaded Architecture-Decimation Filters-mechanical, Thermal, Humidity and Magnetic Sensors-SensorInterfaces.

UNIT IV 9DESIGN FOR TESTABILITY AND ANALOG VLSI INTERCONNECTSFault modelling and Simulation - Testability-Analysis Technique-Ad Hoc Methods andGeneral Guidelines-Scan Techniques-Boundary Scan-Built-in Self Test-Analog TestBuses-Design for Electron -Beam Testablity-Physics of Interconnects in VLSI-Scaling of Interconnects-A Model for Estimating Wiring Density-A Configurable Architecture forPrototyping Analog Circuits.

UNIT V 9STATISTICAL MODELING AND SIMULATION, ANALOG COMPUTER-AIDEDDESIGN AND ANALOG AND MIXED ANALOG-DIGITAL LAYOUTReview of Statistical Concepts - Statistical Device Modeling- Statistical CircuitSimulation-Automation Analog Circuit Design-automatic Analog Layout-CMOSTransistor Layout-Resistor Layout-Capacitor Layout-Analog Cell Layout-Mixed Analog-Digital Layout.

Total : 45

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TEXT BOOK:

1. Mohammed Ismail, Terri Fiez, Analog VLSI signal and Information Processing ",McGraw-Hill International Editons, 1994.

REFERENCES:

1. Malcom R.Haskard, Lan C.May, Analog VLSI Design - NMOS and CMOS ",Prentice Hall, 1998.

2. Randall L Geiger, Phillip E. Allen, " Noel K.Strader, VLSI Design Techniques forAnalog and Digital Circuits ", Mc Graw Hill International Company, 1990.

3. Jose E.France, Yannis Tsividis, Design of Analog-Digital VLSI Circuits forTelecommunication and signal Processing ", Prentice Hall, 1994

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ANE518 COMPUTER AIDED DESIGN OF VLSI CIRCUITS 3 0 0 3

UNIT I 9 VLSI DESIGN METHODOLOGIESIntroduction to VLSI Design methodologies - Review of Data structures and algorithms -

Review of VLSI Design automation tools - Algorithmic Graph Theory andComputational Complexity - Tractable and Intractable problems - general purposemethods for combinatorial optimization.

UNIT II 9 LAYOUT & PARTITIONINGLayout Compaction - Design rules - problem formulation - algorithms for constraintgraph compaction - placement and partitioning - Circuit representation - Placementalgorithms - partitioning

UNIT III 9

FLOORPLANNING & ROUTINGFloor planning concepts - shape functions and floor plan sizing - Types of local routingproblems - Area routing - channel routing - global routing - algorithms for global routing.

UNIT IV 9SIMULATION & SYNTHESISSimulation - Gate-level modeling and simulation - Switch-level modeling and simulation- Combinational Logic Synthesis - Binary Decision Diagrams - Two Level LogicSynthesis.

UNIT V 9HIGH LEVEL SYNTHESISHigh level Synthesis - Hardware models - Internal representation - Allocation assignmentand scheduling - Simple scheduling algorithm - Assignment problem High leveltransformations.

Total : 45

TEXT BOOK:

1. S.H. Gerez, "Algorithms for VLSI Design Automation", John Wiley & Sons, 2002.

REFERENCES

1. N.A. Sherwani, "Algorithms for VLSI Physical Design Automation", KluwarAcademic Publishers, 2002.

2. Drechsler, R., Evolutionary Algorithms for VLSI CAD, Kluwer AcademicPublishers, Boston, 1998.

3. Hill, D., D. Shugard, J. Fishburn and K. Keutzer, Algorithms and Techniques forVLSI Layout Synthesis, Kluwer Academic Publishers, Boston, 1989.

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MAT507 STOCHASTIC MODELS AND SIMULATION 3 1 0 4

UNIT IINTRODUCTION TO PROBABILITY 9Sample space and events; Probability axiom; Conditional probability; Independent

events, Bayes formula, Simple problems.

UNIT IIRANDOM VARIABLE & DISTRIBUTIONS 9Random Variables, Distribution functions, continuous and discrete random variables,Bernoulli, Binomial, Geometric, Poisson random variables, uniform, exponential, normalrandom variables, jointly distributed random variables, expectations and momentgenerating functions, Properties, simulation samples for the above mentioneddistributions.

UNIT III

MARKOV CHAINS 9Markov chains, Chapman Kolmogorov equations, Classification of states, examples of Markov chains. Gamblers ruin problem, mean time spent in transient states, Branchingprocess.

UNIT IVPOISSON PROCESSES 9Properties of exponential distribution, convolution of exponential random variables,Poisson process. Inter arrival of waiting time distribution, Applications to reliabilityproblems, Estimating software reliability.

UNIT VRENEWAL THEORY, QUEUING THEORY & SIMULATION 9Renewal Theory - examples, distribution of the counting process N(t), alternatingrenewal process, Regenerative process, computing the renewal function, semi Markovprocess, Computation of renewal function, Poisson process as a renewal process. Singleserver exponential queuing system, Queue with finite capacity, Shoe shine shop, network of queues, open and closed systems. Methods of simulation of random variables - Inversetransformation method, Rejection method.

L: 45 T: 15 Total : 60TEXT BOOK:1. Sheldon M. Ross, Introduction to Probability Models, Academic press, 2005.

REFERENCES:

1. Karlin and H.M. Tailor, A First Course in Stochastic Processes, Academic Press,1975.

2. Sheldon M.Ross, A First Course in Probability, Sixth Edition, Prentice Hall, NewJersey, 2002.

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CSE501 DATA STRUCTURES AND ALGORITHMS 3 0 0 3

UNIT ICOMPLEXITY ANALYSIS & ELEMENTARY DATA STRUCTURES 9Asymptotic Notations Properties of Big Oh Notation Asymptotic Notation with

Several Parameters Conditional Asymptotic Notation Amortized Analysis NP-Completeness NP-Hard Recurrence Equations Solving Recurrence Equations Arrays Linked Lists Trees.

UNIT IIHEAP STRUCTURES 9Min-Max Heaps Deaps Leftist Heaps Binomial Heaps Fibonacci Heaps SkewHeaps Lazy- Binomial Heaps.

UNIT IIISEARCH STRUCTURES 9

Optimal Binary Search Trees AVL Trees 2-3 Trees 2-3-4 Trees Red-Black Trees B-Trees Splay Trees Tries.

UNIT IVDESIGN TECHNIQUES - GREEDY, DIVIDE AND CONQUER 9Tree Vertex Splitting Job Sequencing with Deadlines Optimal Storage on Tapes Quick Sort Strassens Matrix Multiplication Convex Hull Problem.

UNIT VDYNAMIC PROGRAMMING AND BACKTRACKING 9Multistage Graphs 0/1 Knapsack using Dynamic Programming Flow ShopScheduling 8-Queens Problem Graph Coloring Knapsack Using Backtracking.

Total : 45

TEXT BOOKS:

1. G.Brassard and P.Bratley, Fundamentals of Algorithmics, Printice Hall, 1996.(Unit I)

2. E. Horowitz, S.Sahni and Dinesh Mehta, Fundamentals of Data structures in C++ , Galgotia , 1999.( Unit II & III )

3. E. Horowitz, S.Sahni and S. Rajasekaran, Fundamentals of Computer Algorithms ,Galgotia, 1999.( Unit IV & V )

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CSE502 ADVANCED COMPUTER ARCHITECTURE 3 0 0 3

UNIT IFUNDAMENTALS OF COMPUTER DESIGN 9Introduction- Classes of Computers- Defining Computer Architecture- Trends in

Technology- Dependability- Measuring, Reporting and Summarizing Performance-Quantitative Principles of Computer Design.Instruction set Principles : Introduction-Classifying Instruction set Architectures- MemoryAddressing- Type and Size of Operands- Operations in the Instruction set - Instructionsfor Control Flow- Encoding an Instruction set.

UNIT IIINSTRUCTION LEVEL PARALLELISM 10Pipelining: Introduction- The Major Hurdle of PipeliningPipeline Hazards.Instruction Level Parallelism: Concepts and Challenges- Basic Compiler Techniques forExposing ILP- Reducing Branch Costs with Prediction - Overcoming Data Hazards with

Dynamic Scheduling- Hardware Based Speculation- Exploiting ILP using Multiple Issueand Static Scheduling- Exploiting ILP using Dynamic Scheduling, Multiple Issues andSpeculation.

UNIT IIILIMITS ON ILP 8Limits on Instruction-Level Parallelism : Introduction- Studies of the Limitations of ILP-Limitations on ILP for Realizable processors- Crosscutting Issues : Hardware versusSoftware speculation- Multithreading : Using ILP Support to exploit Thread-LevelParallelism.

UNIT IVMULTIPROCESSORS AND THREAD -LEVEL PARALLELISM 9Introduction- Symmetric Shared-Memory Architectures- Performance of SymmetricShared- Memory Multiprocessors- Distributed Shared Memory and Directory-BasedCoherence- Synchronization The Basics- Models of Memory consistency anIntroduction- Crosscutting Issues.

UNIT VMEMORY HIERARCHY DESIGN AND I/O 9Memory Hierarchy Design : Introduction - Eleven Advanced Optimizations of CachePerformance Memory Technology and Optimizations- Protection: Virtual Memory andVirtual Machines.Storage Systems : Introduction- Advanced Topics in Disk Storage- Definition andExamples of Real Faults and Failures-I/O Performance, Reliability Measures andBenchmarks.

Total : 45

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TEXT BOOK:

1. John L. Hennessey and David A. Patterson," Computer Architecture: A QuantitativeApproach", Fourth Edition, Morgan Kaufmann, 2007.

REFERENCES:

1. D. Sima, T. Fountain and P. Kacsuk, " Advanced Computer Architectures: A DesignSpace Approach", Addison Wesley, 2000.

2. Kai Hwang Advanced computer architecture Parallelism ScalabilityProgrammability" Tata McGraw Hill Edition 2001.

3. Vincent P.Heuring, Harry F.Jordan, Computer System Design and Architecture,Addison Wesley, 2nd Edition 2004.

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CSE 504 NETWORK ENGINEERING 3 1 0 4UNIT INETWORK ARCHITECTURE AND QUEUING ANALYSIS 12Internet Architecture Link and Medium Access Protocol: Design Issues - Case Study:Ethernet Token Rings Wireless Local Area Networks.

Queuing Analysis- Queuing Models Single Server Queues Multiple Server Queues.UNIT IINETWORK LAYER AND ROUTING TECHNIQUES 7Circuit Switching Packet Switching Switching and Forwarding Bridges and LANSwitches Cell Switching Internetworking Routing Techniques: Distance VectorRouting Link State Routing Routing Information Protocol (RIP) Open Shortest PathFirst (OSPF) Subnetting Classless Inter Domain Routing (CIDR).UNIT IIITCP AND CONGESTION CONTROL 11User Datagram Protocol (UDP) Transmission Control Protocol (TCP) TCP FlowControl - Effects of Congestion Congestion Control Traffic Management

Congestion Control in Packet Switching Networks TCP Congestion Control Retransmission Timer Management Exponential Timer backoff KARNs Algorithm- Congestion Avoidance Mechanisms.UNIT IVNETWORK SECURITY AND APPLICATION 9Cryptographic Algorithms Data Encryption Standard (DES) Rivest, Shamir andAdleman (RSA) Algorithm Message Digest 5 (MD5) Security Mechanisms FireWalls Name Service Traditional Applications Simple Mail Transfer Protocol(SMTP) Hyper Text Transfer Protocol (HTTP)Multimedia Applications: Real Time Transfer Protocol (RTP) Real Time ControlProtocol (RTCP).[

UNIT VNETWORK MANAGEMENT 6Introduction Network Monitoring Network Control Simple Network ManagementProtocol Version I (SNMPV I) Network Management Concepts Information StandardMIBs.

L: 45 T: 15 Total : 60TEXT BOOKS:1. Larry L.Peterson and Brule S.Davie, Computer Networks A System Approach

MarGankangmann Harcourt Asia, Third Edition, 20032. William Stallings, HIGH SPEED NETWORKS AND INTERNET, Pearson

Education, Second Edition, 20023. William Stallings, SNMP, SNMP V2, SNMPV3, RMON 1 and 2, 3 rd Edition.

Addison Wesley, 6 th Indian reprint 2002 (Unit V).

REFERENCES:1. J.F Kurose and K.W. Ross, Computer Networking A top down approach featuring

the internet, Addison Wesley, 2001.2. Mani Subramanian, Network Management: Principles and Practice, Addison

Wesley, 2000.

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CSE505 OBJECT ORIENTED SOFTWARE ENGINEERING 3 0 0 3

UNIT IINTRODUCTION TO SOFTWARE ENGINEERING AND MODELING WITHUML 9

Software Related Problems Software Engineering Concepts Development Models andActivities. Modeling with UML. Project Organization Concepts - Project CommunicationConcepts Organization Activities.

UNIT IIREQUIREMENTS ELICITATION AND ANALYSIS 9Requirements Elicitation - Concepts & Managing Requirements. Analysis Overview Concepts - Activities and Managing Analysis.

UNIT IIISYSTEM DESIGN 9

Design Overview Concepts - Activities and Managing System DesignObject Design Overview Concepts - Activities and Managing Object Design

UNIT IVTESTING AND RATIONALE MANAGEMENT 9Testing Overview Concepts - Activities and Managing Testing.Rationale Overview Concepts - Activities and Managing Rationale.

UNIT VSOFTWARE CONFIGURATION AND PROJECT MANAGEMENT 9Configuration Management Overview Concepts - Activities Managing Changes.Project Management Overview Concepts and Project Management Activities.

Total : 45

TEXT BOOK:

1. Bernd Bruegge and Allen H. Dutoit, Object-Oriented Software Engineering UsingUML, Pattern and Java, Pearson Education, 2 nd Edition, 2004.

REFERENCES:

1. Roger S. Pressman., Software Engineering: A Practitioners Approach (SixthEdition), McGraw Hill, 2005. (UNIT I)

2. Ali Bahrami, Object Oriented System Development, Mc Graw Hill InternationalEdition, 1999.

3. Martin Fowler, UML Distilled, PHI/Pearson Education, 2 nd Edition, 2002.

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CSE506 WEB TECHNOLOGY 3 0 0 3

UNIT IINTRODUCTION 9History of the Internet and World Wide Web Introduction to HTML - Protocols

HTTP, SMTP, POP3, MIME, and IMAP. Introduction to JAVA Script Object BasedScripting for the Web- Control structures Functions Arrays Objects- Client-SideScripting with VB Script

UNIT IICOMMON GATEWAY INTERFACE AND DYNAMIC HTML 9Common Gateway Interface: How CGI works-CGI Script Structure-EnvironmentVariables-Server-Side Includes- DHTML: Introduction Cascading Style Sheets- ObjectModel and Collections-Event Model Filters and Transitions-Data Binding with TabularData Control.

UNIT IIIMULTIMEDIA, ECOMMERCE AND WEB SERVERS 9Audio and Video Speech Synthesis and Recognition - Electronic Commerce E-Business Model E- Marketing Online Payments -Security Web Servers Introduction- HTTP Request Types System Architecture-Client Side Versus Server SideScripting -Accessing Web Servers IIS Apache Web Server.

UNIT IVDATABASE- ASP XML 9Database: Introduction- Relational Database Model Overview - SQL ASP : Workingof ASP Objects File System Objects Session Tracking and Cookies ADO Access a Database from ASP Server Side ActiveX Components XML : Introduction-Structuring Data Name spaces DTD and Schemas DOM XSL-SAX .

UNIT VSERVLETS AND JSP 9Servlet : Introduction Overview and Architecture Handling HTTP Request Get andPost Request Redirecting Request Using JDBC from a Servlet JSP: Overview Implicit Objects Scripting Standard Actions Directives.

Total: 45TEXT BOOK:

1. H.M.Deitel ,P.J.Deitel & A.B.Goldberg , Internet and world wide web How toProgram, Pearson Education Asia, 2006.

REFERENCES:

1. Eric Ladd, Jim O Donnel, Using HTML 4, XML and JAVA, Prentice Hall of India QUE, 1999.

2. Rajkamal, Web Technology, Tata McGraw-Hill, 2001.

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ANE519 MOBILE COMPUTING 3 0 0 3

UNIT IINTRODUCTION 9Medium Access Control : Motivation for Specialized MAC- SDMA- FDMA- TDMA-

CDMA- Comparison of Access mechanisms Tele communications : GSM- DECT-TETRA UMTS- IMT-200 Satellite Systems: Basics- Routing- Localization-Handover- Broadcast Systems: Overview Cyclic Repetition of Data- Digital AudioBroadcasting Digital Video Broadcasting

UNIT IIWIRELESS NETWORKS 9Wireless LAN: Infrared Vs Radio Transmission Infrastructure Networks- Ad hocNetworks- IEEE 802.11 HIPERLAN Bluetooth- Wireless ATM: Working Group-Services- Reference Model Functions Radio Access Layer Handover- LocationManagement- Addressing Mobile Quality of Service- Access Point Control Protocol

UNIT IIIMOBILE NETWORK LAYER 9Mobile IP : Goals Assumptions and Requirement Entities IP packet Delivery-Agent Advertisement and Discovery Registration Tunneling and Encapsulation Optimization Reverse Tunneling IPv6 DHCP- Ad hoc Networks

UNIT IVMOBILE TRANSPORT LAYER 9Traditional TCP- Indirect TCP- Snooping TCP- Mobile TCP- Fast retransmit/ FastRecovery- Transmission/ Timeout Freezing Selective Retransmission- Transaction

Oriented TCP

UNIT VWAP 9Architecture Datagram Protocol- Transport Layer Security- Transaction Protocol-Session Protocol- Application Environment-Wireless Telephony Application


1. J.Schiller, Mobile Communication, Addison Wesley, 2000.REFERENCES:

1. William Stallings, Wireless Communication and Networks, Pearson Education,2003.

2. William C.Y.Lee, Mobile Communication Design Fundamentals, John Wiley,1993.

3. Singhal, WAP-Wireless Application Protocol, Pearson Education, 2003.

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ANE520 CELLULAR AND MOBILE COMMUNICATION 3 0 0 3

UNIT IINTRODUCTION TO WIRELESS MOBILE COMMUNICATIONS 9History and evolution of mobile radio systems. Types of mobile wireless services /

systems - Cellular, WLL, Paging, Satellite systems, Standards, Future trends in personalwireless systems.

UNIT IICELLULAR CONCEPT AND SYSTEM DESIGN FUNDAMENTALS 9 Cellular concept and frequency reuse, Multiple Access Schemes, Channel assignment andhandoff, Interference and system capacity, Trunking and Erlang capacity calculations.

UNIT IIIMOBILE RADIO PROPAGATION 9Radio wave propagation issues in personal wireless systems, Propagation models,

Multipath fading and base band impulse response models, Parameters of mobilemultipath channels, Antenna systems in mobile radio.

UNIT IVMODULATIONS AND SIGNAL PROCESSING 9Analog and digital modulation techniques, Performance of various modulation techniques Spectral efficiency, Error-rate, Power Amplification, Equalization Rake receiverconcepts, Diversity and space-time processing, Speech coding and channel coding.

UNIT VSYSTEM EXAMPLES AND DESIGN ISSUES 9 Multiple Access Techniques FDMA, TDMA and CDMA systems, Operational systems,Wireless networking, design issues in personal wireless systems.

Total : 45

TEXT BOOK:

1. Feher K., Wireless digital communications, PHI, New Delhi, 1995.

REFERENCES:

1. Rappaport T.S., Wireless Communications; Principles and Practice, Prentice Hall,NJ, 1996.

2. Lee W.C.Y., Mobile Communications Engineering: Theory and Applications,Second Edition, McGraw-Hill, New York, 1998.

3. Schiller, Mobile Communications, Pearson Education Asia Ltd., 2000.

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ANE521 E-COMMERCE TECHNOLOGY 3 0 0 3

UNIT IINTRODUCTION 9Infrastructure for Electronic Commerce - Networks - Packet Switched Networks - TCP/IP

Internet protocol - Domain name Services - Web Service Protocols - Internet applications- Utility programs - Markup Languages - Web Clients and Servers - Intranets andExtranets - Virtual private Network.

UNIT IICORE TECHNOLOGY 9Electronic Commerce Models - Shopping Cart Technology - Data Mining IntelligentAgents Internet Marketing - XML and E-Commerce

UNIT IIIELECTRONIC PAYMENT SYSTEMS 9

Real world Payment Systems - Electronic Funds Transfer - Digital Payment -InternetPayment Systems Micro Payments - Credit Card Transactions - Case Studies.

UNIT IVSECURITY 9Threats to Network Security - Public Key Cryptography - Secured Sockets Layer -Secure Electronic Transaction - Network Security Solutions - Firewalls.

UNIT VINTER/INTRA ORGANIZATIONS ELECTRONIC COMMERCE 9EDI - EDI application in business - legal, Security and Privacy issues - EDI andElectronic commerce - Standards - Internal Information Systems - Macro forces - Internalcommerce - Workflow Automation and Coordination - Customization and Internalcommerce - Supply chain Management.

Total : 45

TEXT BOOK:

1. Ravi Kalakota and Andrew B Whinston , Frontiers of Electronic commerce, AddisonWesley, 1996

REFERENCES:

1. Pete Loshin, Paul A Murphy, Electronic Commerce, 2 nd Edition, Jaico Publishers1996.

2. David Whiteley, e - Commerce: Strategy, Technologies and Applications - McGrawHill 2000.

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ANE522 REAL TIME AND EMBEDDED SYSTEMS 3 0 0 3

UNIT IINTRODUCTION 9 Introduction to Embedded systems Processor and memory organization-Devices and

buses for Device Networks Device drivers and Interrupt servicing mechanism.

UNIT IIRTOS 9RTOS Programming tools Case studies- Hardware- software Code design in anEmbedded system

UNIT IIIREAL TIME SYSTEMS 9Basic Real time concepts Computer hardware Language issues Software life Cycle

UNIT IVREAL TIME SPECIFICATIONS 9 Design techniques Real-time kernels Intertask communication and synchronization Real time memory management

UNIT VMULTIPROCESSING SYSTEMS 9Multiprocessing Systems - Hardware/Software integration- Real time Applications

Total : 45

TEXT BOOK:

1. Raj Kamal, Embedded Systems Architecture, Programming and Design, Tata Mc-Graw-Hill, 2003

REFERENCES:

1. Phillip A.Laplante, Real Time Systems Design and Analysis, An EngineersHandbook, Prentice-Hall of India, 2002

2. R.J.A.Buhr, D.L.Bailey, An Introduction to Real Time Systems: Design tonetworking with C/C++, Prentice- Hall, International, 1999.

3. Grehan Moore and Cyliax, Real Time Programming: A guide to 32 Bit EmbeddedDevelopment Reading: Addison- Wisley-Longman, 1998.

4. Haeth, Steve, Embedded systems Design, Newnes, 1997.

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ANE523 VISUALIZATION TECHNIQUES 3 0 0 3

UNIT IFOUNDATIONS FOR DATA VISUALIZATION 9Visualization Stages-Experimental Semiotics based on Perception Gibsons Affordance

theory A Model of Perceptual Processing Types of Data.

UNIT IICOMPUTER VISUALIZATION 9Non-Computer Visualization-Computer Visualization - Exploring Complex InformationSpaces Fisheye Views Applications Comprehensible Fisheye views Fisheye viewsfor 3D data Non Linear Magnification Comparing Visualization of InformationSpaces- Abstraction in computer Graphics- Abstraction in user interfaces.

UNIT IIIMULTIDIMENSIONAL VISUALIZATION 9

1D-2D-3D- Multiple Dimensions-trees-web Works Data Mapping: DocumentVisualization Workspaces.

UNIT IVTEXTUAL METHODS OF ABSTRACTION 9From Graphics to pure Text- Figure Captions in Visual Interfaces Interactive 3Dillustrations with images and text Related Work- Consistency of rendered images andtheir textual labels- Architecture- Zoom techniques for illustration purpose- Interactivehandling of images and text.

UNIT V 9Animating non Photo realistic Computer Graphics Interaction Facilities and High LevelSupport for Animation Design Zoom Navigation in User Interfaces InteractiveMedical Illustrations Rendering Gestural Expressions Animating design forSimulation Tactile Maps for Blind people Synthetic Holography Abstraction VersusRealism Integrating Spatial and Non Spatial Data.

Total : 45

TEXT BOOKS:

1. Colin Ware, Morgen Kaufmen, Information Visualization Perception for Design,2nd Edition, Morgan Kaufmann, 2004.

2. Stuart.K.Card, Jock.D.Mackinley and Ben Shneiderman, Readings in InformationVisualization Using Vision to Think, Morgan Kaufmann Publishers, 1999.

REFERENCE:

1. Thomas Strothotte, Computer Visualization Graphics Abstraction and

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