MCS-012 CO&ALP -1- Loganathan R Bangalore Question 1 a) Perform the following arithmetic operations using binary signed 2’s complement notation for integers. You may assume that the maximum size of integers is of 12 bits including the sign bit. i) Add – 512 and 198 ii) Subtract 400 from – 98 iii) Add 400 and 112 Ans: i) 512 in Binary = 10 0000 0000 2s comp of 512(i.e -512) = 10 0000 0000 198 in Binary = + 00 1100 0110 Addition = Cy10 1100 0110 Since no Carry the result is in 2’s compliment form so sign is –ve and magnitude is 2s compliment of result 10 1100 0110 is 01 0011 1010(314) = -314 No Overflow since Cinto Sign bit & Cout from Sign bit are same. ii) 98 in Binary = 00 0110 0010 2s comp of 98 (ie -98) = 11 1001 1110 2s comp of 400(i.e -400) Addition = + 10 0111 0000 = Cy10 0000 1110 Since Carry is 1, discard the carry and the result is –ve, the magnitude is 2’s compliment of the result 10 0000 1110 = 01 1111 0010 = -498 No Overflow since Cin to Sign bit & Cout from Sign bit is same. iii) 400 in Binary = 01 1001 0000 112 in Binary Addition = + 00 0111 0000 = Cy10 0000 0000 There is No Overflow, since Cin is to Sign bit & Cout is from Sign bit are same. The result is correct b) Convert the hexadecimal number: 21 3A EF into binary, octal and decimal equivalent. Ans: Binary = 0010 0001 0011 1010 1110 1111 Octal = 10235357 Decimal = 2177775 c) Convert the following string into equivalent “UTF 16” code –“Email addresses always use @ sign”. Are these codes same as that used in ASCII? Ans: UTF-16 Code: 0045 006D 0061 0069 006C 0020 0061 0064 0064 0072 0065 0073 0073 0065 0073 0020 0061 006C 0077 0061 0079 0073 0020 0075 0073 0065 0020 0040 0020 0073 0069 0067 006E ASCII Code: 45 6D 61 69 6C 20 61 64 64 72 65 73 73 65 73 20 61 6C 77 61 79 73 20 75 73 65 20 40 20 73 69 67 6E No, these codes are NOT the same. (UTF 16 is 16 bit but ASCII is 8 bit)
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MCS-012 CO&ALP
-1- Loganathan R Bangalore
Question 1
a) Perform the following arithmetic operations using binary signed 2’s complement notation for integers. You may assume that the maximum size of integers is of 12 bits including the sign bit.
i) Add – 512 and 198
ii) Subtract 400 from – 98
iii) Add 400 and 112
Ans:
i) 512 in Binary = 10 0000 0000
2s comp of 512(i.e -512) = 10 0000 0000
198 in Binary = + 00 1100 0110
Addition = Cy10 1100 0110
Since no Carry the result is in 2’s compliment form so sign is –ve and magnitude is 2s compliment of result
10 1100 0110 is 01 0011 1010(314) = -314 No Overflow since Cinto Sign bit & Cout from Sign bit are same.
ii) 98 in Binary = 00 0110 0010
2s comp of 98 (ie -98) = 11 1001 1110
2s comp of 400(i.e -400) Addition
= + 10 0111 0000 = Cy10 0000 1110
Since Carry is 1, discard the carry and the result is –ve, the magnitude is 2’s compliment of the result 10 0000 1110 = 01 1111 0010 = -498 No Overflow since Cin to Sign bit & Cout from Sign bit is same.
iii) 400 in Binary = 01 1001 0000
112 in Binary Addition
= + 00 0111 0000 = Cy10 0000 0000
There is No Overflow, since Cin is to Sign bit & Cout is from Sign bit are same. The result is correct
b) Convert the hexadecimal number: 21 3A EF into binary, octal and decimal equivalent.
Ans:
Binary = 0010 0001 0011 1010 1110 1111
Octal = 10235357
Decimal = 2177775
c) Convert the following string into equivalent “UTF 16” code –“Email addresses always use @ sign”.
Transfer the address bits of instruction to the MAR. MAR←DR(Insmem)
Perform a memory read operation as done in fetch cycle and the desired
address of the operand is obtained in the DR
DR ←(MAR)
Transfer the address part so obtained in DR as the address part of
instruction
IR(Addr)←DR(Addr)
Execution:
Transfer the address portion of the instruction to the MAR MAR← IR (Addrs)
Read the memory and bring the operand in the DR DR←(MAR)
Move the DR to PC. PC← DR
Interrupt Acknowledge: Then check whether there is any pending interrupt request for the interrupts that are enabled. If
interrupt has occurred then that Interrupt may be processed.
MCS-012 CO&ALP
-9- Loganathan R Bangalore
c) Assume that you have a machine as shown in section 3.2.2 of Block 3 having the micro-operations as
given in Figure 10 on page 62 of Block 3. Consider that R1 and R2 both are 8 bit registers and contains
10101010 and 10010110 respectively. What will be the values of select inputs, carry-in input and result
of operation if the following micro-operations are performed? (For each micro-operation you may
assume the initial value of R1 and R2 as defined above)
1) Transfer R1
2) Shift Right R1
3) Add R1 and R2 with carry
4) Complement R1
Ans:
S3 S2 S1 S0 Ci F Micro Operation Result
0 0 0 0 0 F = x R ← R1 10101010
1 1 - - - F = Shr(y) R ← Shr(R1) 01010101
0 0 0 1 1 F = x +y+1 R ← R1 + R2+1 01000001
0 1 1 1 1 F = x’ R ← R’1 01010101
d) Explain the Control Memory Organisation with the help of a diagram. Explain how this control memory
may be used to perform various instruction cycles..
Ans:
Diagram:
Draw Figure 6: Control Memory Organisation in Page 76 of Sec 4.6.2 in Block 3
The simplest ways to organize control memory is to arrange micro-instructions for various sub cycles
of the machine instruction in the memory
Let us give an example of control memory organization. Let us take a machine instruction: Branch on
zero. This instruction causes a branch to a specified main memory address in case the result of the last
ALU operation is zero, that is, the zero flag is set. The pseudocode of the micro-program for this
instruction can be;
Test "zero flag” If SET branch to label ZERO
Unconditional branch to label NON-ZERO
ZERO: (Microcode which causes replacement of program counter with the address provided in the
instruction) Branch to interrupt or fetch cycle.
NON -ZERO: (Microcode which may set flags if desired indicating the branch has not taken place).
Branch to interrupt or fetch cycle. (For Next- Instruction Cycle)
e) What are the advantages of instruction pipeline? Explain with the help of a diagram for a 3 stage
instruction pipeline having cycles IFD (Instruction Fetch and Decode), OF (Operand Fetch) and ES
(Execute and store results). What can be the problems of such an instruction pipeline?
Ans:
It improves the performance of the CPU Considerably. The instruction pipelining involves decomposing
of an instruction execution to a number of pipeline stages. A pipeline allows overlapped execution of
instructions. For example an instruction, during the execution, it may be decomposed in to Instruction
fetch and decode (IFD), Operand Fetch (OF) and Execution & Store result(ES) cycles. The following
diagram shows 3 stage instruction pipeline having cycles IFD, OF and ES.
Time Slot → 1 2 3 4 5 6 7
Instruction 1 IFD OF ES
-10-
Instruction 2 IFD OF ES
Instruction 3 IFD OF ES
Instruction 4 IFD OF ES
Instruction 5 IFD OF ES
The pipeline stages are like steps each to be completed in a time slot. The first instruction execution is
completed on completion of 3rd time slot, but afterwards, in each time slot the next instruction gets executed. So, in ideal conditions one instruction is executed in the pipeline in each time slot. After the
3rd time slot and afterwards the pipe is full.
Diagram for four stage instruction pipeline with following four cycle is:
IF (Instruction Fetch)
IAD(Instruction and Address Decode)
OF (Operand Fetch)
ES (Execute and store results)
Time Slot → 1 2 3 4 5 6 7 8
Instruction 1 IF IAD OF ES
Instruction 2 IF IAD OF ES
Instruction 3 IF IAD OF ES
Instruction 4 IF IAD OF ES
Instruction 5 IF IAD OF ES
f) Assume that a RISC machine has 64 registers out of which 16 registers are reserved for the Global
variables. Assuming that 8 of the registers are to be used for one function, explain how the remaining
registers will be used as overlapped register windows. How will these registers be used for parameter
passing for subroutine calls? Explain with the help of diagram.
Ans:
Register# Used For
0-31
(32 Registers)
Global Variable les
Required by
Function A
Function A
Function B
Function C
32-67 Unused
68-77
(10 Registers)
Used by parameters
of fC that may be passed to next call
Temporary
variables of
function C
78-83 (6 Registers)
Used for local
variable of fC
Local variables
of function C
84-97 (4+10
Registers)
Used by parameters
that were passed
from fB to fC
Temporary
variables of
function B
Parameters of
function C
98-103 (6 Registers)
Local variable of fB Local Variables
of function B
104-117 (4+10
Registers)
Parameters that were
passed from fA to fB
Temporary variables
of function A
Parameters of
function B
118-123 ( 6 Registers)
Local variable of fA Local Variables of
function A
124-127 (4 Registers)
Parameter passed to
fA
Parameters of
function A
-11-
Question 4 a) Write a program in 8086 Assembly Language (with proper comments) to find if the two given strings
of length 5 are reverse of each other. You may assume that both the strings are available in the memory.
Make suitable assumptions, if any.
Ans:
;Program to check if the two given strings of length 5 are reverse of each other.
.model small ;1 ds & 1 CS
.data ;Data Segment
str1 db 'madam'
str2 db 'madam'
slen dw slen-sstr
smsg db 'Both are Reverse of each $'
fmsg db 'Both are NOT Reverse of each $'
.code
start:
mov ax, @data
mov ds, ax ;initialize DS with Data Segment Base
mov es, ax ;initialize ES with Data Segment Base
lea si, str1 ;Offset of main string to SI
lea di, str2 ;Offset of sub string to DI
mov cx, slen ;String Length of strings to CX
repe cmpsb ;compare string1 with main string2
je ldmsg ;Mach found
lea dx, fmsg ;No match so store offset of Fail msg
jmp disp
ldmsg:
lea dx, smsg ;store offset of Success msg
disp:
mov ah, 9
int 21h ;Display message
mov ah, 4ch ;exit to operating system.
int 21h
end start ;stop the assembler.
Output:
Both are Reverse of each
-12-
b) Write a program in 8086 assembly language to convert a two digit unpacked BCD number into
equivalent ASCII digits and a packed BCD number. The packed BCD number is to be stored in BH
register. Your program should print the two ASCII digits. You may assume that the unpacked BCD
numbers are in the AL and BL registers
Ans:
;Unpacked BCD to ASCII & Packed BCD
.model small
.data
msg db 10,13,'Two ASCII Digits are '
asci1 db 30h,' and '
asci2 db 30h, '$'
.code segment
start:
mov ax, @data ;Initializing data Segment register
mov ds, ax
mov al, 2 ;1st Unpacked BCD numbeber
mov bl, 4 ;2nd Unpacked BCD numbeber
add asci1, al ;equalant ascii
add asci2, bl
mov bh, al ;1st Unpacked bcd to bh
mov cl, 4 ;to shift lower 4 bits to higher
shl bh, cl
or bh, bl ;Combine to get packed bcd in bh
lea dx, msg ;Display All
mov ah, 9
int 21h
mov ah, 4ch ; exit to operating system.
int 21h
end start ; stop the assembler.
Output:
Two ASCII Digits are 2 and 4
-13-
c) Write simple near procedure in 8086 assembly language that receives one parameter value in AL register
from the main module and returns sign bit of the input parameter. Make suitable assumptions, if any.