Mcp 3201

MCP32012.7V 12-Bit A/D Converter with SPI Serial Interface

Features

• 12-Bit Resolution

• ±1 LSB max DNL

• ±1 LSB max INL (MCP3201-B)

• ±2 LSB max INL (MCP3201-C)

• On-chip Sample and Hold

• SPI Serial Interface (modes 0,0 and 1,1)

• Single Supply Operation: 2.7V - 5.5V

• 100 ksps Maximum Sampling Rate at VDD = 5V

• 50 ksps Maximum Sampling Rate at VDD = 2.7V

• Low-Power CMOS Technology

• 500 nA Typical Standby Current, 2 µA Maximum

• 400 µA Maximum Active Current at 5V

• Industrial Temp Range: -40°C to +85°C

• 8-pin MSOP, PDIP, SOIC and TSSOP Packages

Applications

• Sensor Interface

• Process Control

• Data Acquisition

• Battery Operated Systems

Functional Block Diagram

Description

The Microchip Technology Inc. MCP3201 device is asuccessive approximation 12-bit Analog-to-Digital(A/D) Converter with on-board sample and holdcircuitry. The device provides a single pseudo-differen-tial input. Differential Nonlinearity (DNL) is specified at±1 LSB, and Integral Nonlinearity (INL) is offered in±1 LSB (MCP3201-B) and ±2 LSB (MCP3201-C)versions. Communication with the device is done usinga simple serial interface compatible with the SPIprotocol. The device is capable of sample rates of up to100 ksps at a clock rate of 1.6 MHz. The MCP3201device operates over a broad voltage range (2.7V-5.5V). Low-current design permits operation withtypical standby and active currents of only 500 nA and300 µA, respectively. The device is offered in 8-pinMSOP, PDIP, TSSOP and 150 mil SOIC packages.

Package Types

Comparator

Sampleand Hold

12-Bit SAR

DAC

Control Logic

CS/SHDN

VREF

IN+

IN-

VSSVDD

CLK DOUT

ShiftRegister

VREF

IN+

IN–

VSS

VDD

CLK

DOUT

CS/SHDN

1

2

3

4

8

7

6

5

MSOP, PDIP, SOIC, TSSOP

MC

P3

201

1998-2011 Microchip Technology Inc. DS21290F-page 1

MCP3201

NOTES:

DS21290F-page 2 1998-2011 Microchip Technology Inc.

MCP3201

1.0 ELECTRICAL CHARACTERISTICS

1.1 Maximum Ratings†

VDD...................................................................................7.0V

All inputs and outputs w.r.t. VSS ................ -0.6V to VDD +0.6V

Storage temperature .....................................-65°C to +150°C

Ambient temp. with power applied ................-65°C to +125°C

ESD protection on all pins (HBM) .................................> 4 kV

†Notice: Stresses above those listed under “Maximumratings” may cause permanent damage to the device. This isa stress rating only and functional operation of the device atthose or any other conditions above those indicated in theoperational listings of this specification is not implied.Exposure to maximum rating conditions for extended periodsmay affect device reliability.

ELECTRICAL CHARACTERISTICSElectrical Specifications: All parameters apply at VDD = 5V, VSS = 0V, VREF = 5V, TA = -40°C to +85°C, fSAMPLE = 100 ksps, and fCLK = 16*fSAMPLE, unless otherwise noted.

Parameter Sym Min Typ Max Units Conditions

Conversion Rate:

Conversion Time tCONV — — 12 clock cycles

Analog Input Sample Time tSAMPLE 1.5 clock cycles

Throughput Rate fSAMPLE — — 10050

kspsksps

VDD = VREF = 5VVDD = VREF = 2.7V

DC Accuracy:

Resolution 12 bits

Integral Nonlinearity INL ——

±0.75±1

±1±2

LSBLSB

MCP3201-BMCP3201-C

Differential Nonlinearity DNL — ±0.5 ±1 LSB No missing codes over temperature

Offset Error — ±1.25 ±3 LSB

Gain Error — ±1.25 ±5 LSB

Dynamic Performance:

Total Harmonic Distortion THD — -82 — dB VIN = 0.1V to 4.9V@1 kHz

Signal to Noise and Distortion (SINAD)

SINAD — 72 — dB VIN = 0.1V to 4.9V@1 kHz

Spurious Free Dynamic Range SFDR — 86 — dB VIN = 0.1V to 4.9V@1 kHz

Reference Input:

Voltage Range 0.25 — VDD V Note 2

Current Drain ——

100.001

1503

µAµA CS = VDD = 5V

Analog Inputs:

Input Voltage Range (IN+) IN+ IN- — VREF+IN- V

Input Voltage Range (IN-) IN- VSS-100 VSS+100 mV

Leakage Current — 0.001 ±1 µA

Switch Resistance RSS — 1K — W See Figure 4-1

Sample Capacitor CSAMPLE — 20 — pF See Figure 4-1

Digital Input/Output:

Data Coding Format Straight Binary

High Level Input Voltage VIH 0.7 VDD — — V

Low Level Input Voltage VIL — — 0.3 VDD V

Note 1: This parameter is established by characterization and not 100% tested.2: See graph that relates linearity performance to VREF level.3: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance,

especially at elevated temperatures. See Section 6.2 “Maintaining Minimum Clock Speed” for more information.


MCP3201

TEMPERATURE CHARACTERISTICS

High Level Output Voltage VOH 4.1 — — V IOH = -1 mA, VDD = 4.5V

Low Level Output Voltage VOL — — 0.4 V IOL = 1 mA, VDD = 4.5V

Input Leakage Current ILI -10 — 10 µA VIN = VSS or VDD

Output Leakage Current ILO -10 — 10 µA VOUT = VSS or VDD

Pin Capacitance(all inputs/outputs)

CIN, COUT — — 10 pF VDD = 5.0V (Note 1)TA = +25°C, f = 1 MHz

Timing Parameters:

Clock Frequency fCLK ——

——

1.60.8

MHzMHz

VDD = 5V (Note 3)VDD = 2.7V (Note 3)

Clock High Time tHI 312 — — ns

Clock Low Time tLO 312 — — ns

CS Fall To First Rising CLK Edge tSUCS 100 — — ns

CLK Fall To Output Data Valid tDO — — 200 ns See Test Circuits, Figure 1-2

CLK Fall To Output Enable tEN — — 200 ns See Test Circuits, Figure 1-2

CS Rise To Output Disable tDIS — — 100 ns See Test Circuits, Figure 1-2 (Note 1)

CS Disable Time tCSH 625 — — ns

DOUT Rise Time tR — — 100 ns See Test Circuits, Figure 1-2 (Note 1)

DOUT Fall Time tF — — 100 ns See Test Circuits, Figure 1-2 (Note 1)

Power Requirements:

Operating Voltage VDD 2.7 — 5.5 V

Operating Current IDD ——

300210

400—

µAµA

VDD = 5.0V, DOUT unloadedVDD = 2.7V, DOUT unloaded

Standby Current IDDS — 0.5 2 µA CS = VDD = 5.0V

Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND.

Parameters Sym Min Typ Max Units Conditions

Temperature Ranges

Specified Temperature Range TA -40 — +85 °C

Operating Temperature Range TA -40 — +85 °C

Storage Temperature Range TA -65 — +150 °C

Thermal Package Resistances

Thermal Resistance, 8L-MSOP JA — 211 — °C/W

Thermal Resistance, 8L-PDIP JA — 89.5 — °C/W

Thermal Resistance, 8L-SOIC JA — 149.5 — °C/W

Thermal Resistance, 8L-TSSOP JA — 139 — °C/W

ELECTRICAL CHARACTERISTICS (CONTINUED)Electrical Specifications: All parameters apply at VDD = 5V, VSS = 0V, VREF = 5V, TA = -40°C to +85°C, fSAMPLE = 100 ksps, and fCLK = 16*fSAMPLE, unless otherwise noted.

Parameter Sym Min Typ Max Units Conditions

Note 1: This parameter is established by characterization and not 100% tested.2: See graph that relates linearity performance to VREF level.3: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance,

especially at elevated temperatures. See Section 6.2 “Maintaining Minimum Clock Speed” for more information.


MCP3201

FIGURE 1-1: Serial Timing.

FIGURE 1-2: Test Circuits.

CS

CLK

tSUCS

tCSH

tHI tLO

DOUT

tEN tDOtR tF

LSBMSB OUT

tDIS

NULL BITHI-Z HI-Z

VIH

tDIS

CS

DOUTWaveform 1*

DOUTWaveform 2†

90%

10%

* Waveform 1 is for an output with internal condi-tions such that the output is high, unless disabledby the output control.

† Waveform 2 is for an output with internal condi-tions such that the output is low, unless disabledby the output control.

Voltage Waveforms for tDIS

Test Point

1.4V

DOUT

Load circuit for tR, tF, tDO

3 kΩ

CL = 30 pF

Test Point

DOUT

Load circuit for tDIS and tEN

3 kΩ

30 pF

tDIS Waveform 2

tDIS Waveform 1

CS

CLK

DOUT

tEN

1 2

B9

Voltage Waveforms for tEN

tEN Waveform

VDD

VDD/2

VSS

3 4

DOUT

tR

Voltage Waveforms for tR, tF

CLK

DOUT

tDO

Voltage Waveforms for tDO

tF

VOHVOL


MCP3201

NOTES:


MCP3201

2.0 TYPICAL PERFORMANCE CHARACTERISTICS

Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 16*fSAMPLE, TA = +25°C.

FIGURE 2-1: Integral Nonlinearity (INL) vs. Sample Rate.

FIGURE 2-2: Integral Nonlinearity (INL) vs. VREF.

FIGURE 2-3: Integral Nonlinearity (INL) vs. Code (Representative Part).

FIGURE 2-4: Integral Nonlinearity (INL) vs. Sample Rate (VDD = 2.7V).

FIGURE 2-5: Integral Nonlinearity (INL) vs. VREF (VDD = 2.7V).

FIGURE 2-6: Integral Nonlinearity (INL) vs. Code (Representative Part, VDD = 2.7V).

Note: The graphs provided following this note are a statistical summary based on a limited number of samplesand are provided for informational purposes only. The performance characteristics listed herein are nottested or guaranteed. In some graphs, the data presented may be outside the specified operating range(e.g., outside specified power supply range) and therefore outside the warranted range.

-1.0-0.8-0.6-0.4-0.20.00.20.40.60.81.0

0 25 50 75 100 125 150Sample Rate (ksps)

INL

(L

SB

)

Positive INL

Negative INL

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

0 1 2 3 4 5VREF (V)

INL

(L

SB

) Positive INL

Negative INL

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

0 512 1024 1536 2048 2560 3072 3584 4096

Digital Code

INL

(L

SB

)

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

0 20 40 60 80 100Sample Rate (ksps)

INL

(L

SB

)

VDD = VREF = 2.7V

Positive INL

Negative INL

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0VREF (V)

IN

L (

LS

B)

Positive INL

Negative INL

VDD = 2.7VFSAMPLE = 50 ksps

-1.0-0.8-0.6-0.4-0.20.00.20.40.60.81.0

0 512 1024 1536 2048 2560 3072 3584 4096Digital Code

INL

(L

SB

)

VDD = VREF = 2.7VFSAMPLE = 50 ksps


MCP3201


FIGURE 2-7: Integral Nonlinearity (INL) vs. Temperature.

FIGURE 2-8: Differential Nonlinearity (DNL) vs. Sample Rate.

FIGURE 2-9: Differential Nonlinearity (DNL) vs. VREF.

FIGURE 2-10: Integral Nonlinearity (INL) vs. Temperature (VDD = 2.7V).

FIGURE 2-11: Differential Nonlinearity (DNL) vs. Sample Rate (VDD = 2.7V).

FIGURE 2-12: Differential Nonlinearity (DNL) vs. VREF (VDD = 2.7V).

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

-50 -25 0 25 50 75 100

Temperature (°C)

INL

(L

SB

)

Positive INL

Negative INL

-1.0-0.8

-0.6-0.4-0.20.0

0.20.40.60.8

1.0

0 25 50 75 100 125 150Sample Rate (ksps)

DN

L (

LS

B) Positive DNL

Negative DNL

-2.0

-1.0

0.0

1.0

2.0

3.0

0 1 2 3 4 5

VREF (V)

DN

L (

LS

B)

Negative DNL

Positive DNL

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

-50 -25 0 25 50 75 100

Temperature (°C)

INL

(L

SB

)

Positive INL

VDD = VREF = 2.7V

FSAMPLE = 50 ksps

Negative INL

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

0 20 40 60 80 100Sample Rate (ksps)

DN

L (

LS

B)

VDD = VREF = 2.7V

Positive DNL

Negative DNL

-3.0

-2.0

-1.0

0.0

1.0

2.0

3.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0

VREF(V)

DN

L (

LS

B)

Positive DNL

Negative DNL

VDD = 2.7V

FSAMPLE = 50 ksps


MCP3201


FIGURE 2-13: Differential Nonlinearity (DNL) vs. Code (Representative Part).

FIGURE 2-14: Differential Nonlinearity (DNL) vs. Temperature.

FIGURE 2-15: Gain Error vs. VREF.

FIGURE 2-16: Differential Nonlinearity (DNL) vs. Code (Representative Part, VDD = 2.7V).

FIGURE 2-17: Differential Nonlinearity (DNL) vs. Temperature (VDD = 2.7V).

FIGURE 2-18: Offset Error vs. VREF.

-1.0-0.8-0.6-0.4-0.20.00.20.40.60.81.0

0 512 1024 1536 2048 2560 3072 3584 4096

Digital Code

DN

L (

LS

B)

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.20.4

0.6

0.81.0

-50 -25 0 25 50 75 100Temperature (°C)

DN

L (

LS

B) Positive DNL

Negative DNL

-2

-1

0

1

2

3

4

5

0 1 2 3 4 5

VREF(V)

Ga

in E

rro

r (L

SB

) VDD = 2.7V

FSAMPLE = 50 ksps

VDD = 5V

FSAMPLE = 100 ksps

-1.0

-0.8-0.6

-0.4

-0.2

0.00.2

0.4

0.6

0.81.0

0 512 1024 1536 2048 2560 3072 3584 4096Digital Code

DN

L (

LS

B)


-1.0

-0.8

-0.6-0.4

-0.20.00.2

0.4

0.6

0.81.0

-50 -25 0 25 50 75 100Temperature (°C)

DN

L (

LS

B) Positive DNL

VDD = 2.7VFSAMPLE = 50ksps

Negative DNL

0

2

4

6

8

10

12

14

16

18

20

0 1 2 3 4 5

VREF (V)

Off

set

Err

or

(LS

B) VDD = 5V

FSAMPLE = 100 ksps

VDD = 2.7V

FSAMPLE = 50ksps


MCP3201


FIGURE 2-19: Gain Error vs. Temperature.

FIGURE 2-20: Signal-to-Noise Ratio (SNR) vs. Input Frequency.

FIGURE 2-21: Total Harmonic Distortion (THD) vs. Input Frequency.

FIGURE 2-22: Offset Error vs. Temperature.

FIGURE 2-23: Signal-to-Noise and Distortion (SINAD) vs. Input Frequency.

FIGURE 2-24: Signal-to-Noise and Distortion (SINAD) vs. Input Signal Level.

-1.0-0.8-0.6-0.4-0.20.00.20.40.60.81.0

-50 -25 0 25 50 75 100Temperature (°C)

Ga

in E

rro

r (L

SB

)

VDD = VREF = 5VFSAMPLE = 100 ksps


0102030405060708090

100

1 10 100Input Frequency (kHz)

SN

R (

dB

)



-100-90

-80

-70

-60

-50

-40-30

-20

-100


TH

D (

dB

)


VDD = VREF = 5V, FSAMPLE = 100 ksps

0.00.2

0.4

0.6

0.81.0

1.2

1.41.6

1.82.0

-50 -25 0 25 50 75 100Temperature (°C)

Off

se

t E

rro

r (L

SB

) VDD = VREF = 5VFSAMPLE = 100 ksps


010

20

30

40

50

60

7080

90

100


SIN

AD

(d

B)



0

10

20

30

40

50

60

70

80

-40 -35 -30 -25 -20 -15 -10 -5 0Input Signal Level (dB)

SIN

AD

(d

B)




MCP3201


FIGURE 2-25: Effective Number of Bits (ENOB) vs. VREF.

FIGURE 2-26: Spurious Free Dynamic Range (SFDR) vs. Input Frequency.

FIGURE 2-27: Frequency Spectrum of 10 kHz input (Representative Part).

FIGURE 2-28: Effective Number of Bits (ENOB) vs. Input Frequency.

FIGURE 2-29: Power Supply Rejection (PSR) vs. Ripple Frequency.

FIGURE 2-30: Frequency Spectrum of 1 kHz input (Representative Part, VDD = 2.7V).

9.009.259.509.75

10.0010.2510.5010.7511.0011.2511.5011.7512.00

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

VREF (V)

EN

OB

(rm

s)

VDD = VREF = 2.7V

FSAMPLE = 50 ksps

VDD = VREF = 5V

FSAMPLE =100 ksps

0102030405060708090

100


SF

DR

(d

B)


VDD = VREF = 5V, FSAMPLE = 100 ksps

-130-120-110-100-90-80-70-60-50-40-30-20-10

0

0 10000 20000 30000 40000 50000Frequency (Hz)

Am

pli

tud

e (

dB

)

VDD = VREF = 5VFSAMPLE = 100 kspsFINPUT = 9.985kHz4096 points

8.0

8.5

9.0

9.5

10.0

10.5

11.0

11.5

12.0

1 10 100

Input Frequency (kHz)

EN

OB

(rm

s)

VDD = 2.7V

FSAMPLE = 50 ksps

VDD = 5V

FSAMPLE = 100 ksps

-80

-70

-60

-50

-40

-30

-20

-10

0

1 10 100 1000 10000

Ripple Frequency (kHz)

Po

wer

Su

pp

ly R

eje

cti

on

(d

B)

-130-120-110-100-90-80-70-60-50-40-30-20-10

0

0 5000 10000 15000 20000 25000Frequency (Hz)

Am

pli

tud

e (

dB

)

VDD = VREF = 2.7VFSAMPLE = 50 kspsFINPUT = 998.76 Hz4096 points


MCP3201


FIGURE 2-31: IDD vs. VDD.

FIGURE 2-32: IDD vs. Clock Frequency.

FIGURE 2-33: IDD vs. Temperature.

FIGURE 2-34: IREF vs. VDD.

FIGURE 2-35: IREF vs. Clock Frequency.

FIGURE 2-36: IREF vs. Temperature.

050

100150200250300350400450500

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V)

I DD (

µA

)

VREF = VDD

All points at FCLK = 1.6 MHz, exceptat VREF = VDD = 2.5V, FCLK = 800 kHz

0

50

100

150

200

250

300

350

400

10 100 1000 10000

Clock Frequency (kHz)

IDD

(µ

A)

VDD = VREF = 5V

VDD = VREF = 2.7V

0

50

100

150

200

250

300

350

400

-50 -25 0 25 50 75 100

Temperature (°C)

I DD (

µA

)

VDD = VREF = 5VFCLK = 1.6 MHz

VDD = VREF = 2.7VFCLK = 800 kHz

010

2030

4050

60

7080

90100

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0VDD (V)

I RE

F (

µA

)

VREF = VDD

All points at FCLK = 1.6 MHz, exceptat VREF = VDD = 2.5V, FCLK = 800 kHz

0

10

20

30

40

50

60

70

80

90

100

10 100 1000 10000

Clock Frequency (kHz)

IRE

F (µ

A)

VDD = VREF = 5V

VDD = VREF = 2.7V

0102030405060

708090

100

-50 -25 0 25 50 75 100Temperature (°C)

I RE

F (

µA

)

VDD = VREF = 5VFCLK = 1.6 MHz

VDD = VREF = 2.7VFCLK = 800 kHz


MCP3201


FIGURE 2-37: IDDS vs. VDD.

FIGURE 2-38: IDDS vs. Temperature.

FIGURE 2-39: Analog Input Leakage Current vs. Temperature.

0

10

20

30

40

50

60

70

80

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V)

I DD

S (

pA

)

VREF = CS = VDD

0.01

0.10

1.00

10.00

100.00

-50 -25 0 25 50 75 100Temperature (°C)

I DD

S (

nA

)

VDD = VREF = CS = 5V

0.00.20.40.60.81.01.21.41.61.82.0

-50 -25 0 25 50 75 100Temperature (°C)

An

alo

g In

pu

t L

eak

ag

e (

nA

) VDD = VREF = 5VFCLK = 1.6 MHz


MCP3201

NOTES:


MCP3201

3.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

Additional descriptions of the device pins follows.

TABLE 3-1: PIN FUNCTION TABLE

3.1 Positive Analog Input (IN+)

Positive analog input. This input can vary from IN- toVREF + IN-.

3.2 Negative Analog Input (IN-)

Negative analog input. This input can vary ±100 mVfrom VSS.

3.3 Chip Select/Shutdown (CS/SHDN)

The CS/SHDN pin is used to initiate communicationwith the device when pulled low and will end aconversion and put the device in low power standbywhen pulled high. The CS/SHDN pin must be pulledhigh between conversions.

3.4 Serial Clock (CLK)

The SPI clock pin is used to initiate a conversion and toclock out each bit of the conversion as it takes place.See Section 6.2 “Maintaining Minimum ClockSpeed” for constraints on clock speed.

3.5 Serial Data Output (DOUT)

The SPI serial data output pin is used to shift out theresults of the A/D conversion. Data will always changeon the falling edge of each clock as the conversiontakes place.

MCP3201

Symbol DescriptionMSOP, PDIP, SOIC, TSSOP

1 VREF Reference Voltage Input

2 IN+ Positive Analog Input

3 IN- Negative Analog Input

4 VSS Ground

5 CS/SHDN Chip Select/Shutdown Input

6 DOUT Serial Data Out

7 CLK Serial Clock

8 VDD +2.7V to 5.5V Power Supply


MCP3201

NOTES:


MCP3201

4.0 DEVICE OPERATION

The MCP3201 A/D Converter employs a conventionalSAR architecture. With this architecture, a sample isacquired on an internal sample/hold capacitor for1.5 clock cycles starting on the first rising edge of theserial clock after CS has been pulled low. Following thissample time, the input switch of the converter opensand the device uses the collected charge on theinternal sample and hold capacitor to produce a serial12-bit digital output code. Conversion rates of 100 kspsare possible on the MCP3201 device. See Section 6.2“Maintaining Minimum Clock Speed” for informationon minimum clock rates. Communication with thedevice is done using a 3-wire SPI-compatible interface.

4.1 Analog Inputs

The MCP3201 device provides a single pseudo-differ-ential input. The IN+ input can range from IN- to VREF(VREF + IN-). The IN- input is limited to ±100 mV fromthe VSS rail. The IN- input can be used to cancel smallsignal common-mode noise which is present on boththe IN+ and IN- inputs.

For the A/D Converter to meet specification, the chargeholding capacitor (CSAMPLE) must be given enoughtime to acquire a 12-bit accurate voltage level duringthe 1.5 clock cycle sampling period. The analog inputmodel is shown in Figure 4-1.

In this diagram, it is shown that the source impedance(RS) adds to the internal sampling switch (RSS)impedance, directly affecting the time that is required tocharge the capacitor (CSAMPLE). Consequently, alarger source impedance increases the offset, gain,and integral linearity errors of the conversion.

Ideally, the impedance of the signal source should benear zero. This is achievable with an operationalamplifier such as the MCP601, which has a closed loopoutput impedance of tens of ohms. The adverse affectsof higher source impedances are shown in Figure 4-2.

If the voltage level of IN+ is equal to or less than IN-, theresultant code will be 000h. If the voltage at IN+ is equalto or greater than [VREF + (IN-)] - 1 LSB, then theoutput code will be FFFh. If the voltage level at IN- ismore than 1 LSB below VSS, then the voltage level atthe IN+ input will have to go below VSS to see the 000houtput code. Conversely, if IN- is more than 1 LSBabove VSS, then the FFFh code will not be seen unlessthe IN+ input level goes above VREF level.

4.2 Reference Input

The reference input (VREF) determines the analog inputvoltage range and the LSB size, as shown below.

EQUATION 4-1:

As the reference input is reduced, the LSB size isreduced accordingly. The theoretical digital output codeproduced by the A/D Converter is a function of theanalog input signal and the reference input as shownbelow.

EQUATION 4-2:

When using an external voltage reference device, thesystem designer should always refer to themanufacturer’s recommendations for circuit layout.Any instability in the operation of the reference devicewill have a direct effect on the operation of theA/D Converter.

LSB SizeVREF4096-------------=

Digital Output Code4096*VIN

VREF-------------------------=

Where:

VIN = Analog Input Voltage = V(IN+) - V(IN-)

VREF = Reference Voltage


MCP3201

FIGURE 4-1: Analog Input Model.

FIGURE 4-2: Maximum Clock Frequency vs. Input Resistance (RS) to maintain less than a 0.1 LSB deviation in INL from nominal conditions.

CPINVA

RSS CHx

7 pF

VT = 0.6V

VT = 0.6VILEAKAGE

SamplingSwitch

SS RS = 1 k

CSAMPLE= DAC capacitance

VSS

VDD

= 20 pF±1 nA

Legend:VA = Signal Source

RSS = Source ImpedanceCHx = Input Channel PadCPIN = Input Pin Capacitance

VT = Threshold VoltageILEAKAGE = Leakage Current At The Pin

Due To Various JunctionsSS = Sampling SwitchRS = Sampling Switch Resistor

CSAMPLE = Sample/hold Capacitance

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

100 1000 10000

Input Resistance (Ohms)

Clo

ck F

req

uen

cy (

MH

z)

VDD = VREF = 5V

VDD = VREF = 2.7V


MCP3201

5.0 SERIAL COMMUNICATIONS

Communication with the device is done using astandard SPI-compatible serial interface. Initiatingcommunication with the MCP3201 device begins withthe CS going low. If the device was powered up with theCS pin low, it must be brought high and back low toinitiate communication. The device will begin to samplethe analog input on the first rising edge after CS goeslow. The sample period will end in the falling edge of thesecond clock, at which time the device will output a lownull bit. The next 12 clocks will output the result of theconversion with MSB first, as shown in Figure 5-1. Datais always output from the device on the falling edge ofthe clock. If all 12 data bits have been transmitted andthe device continues to receive clocks while the CS isheld low, the device will output the conversion resultLSB first, as shown in Figure 5-2. If more clocks areprovided to the device while CS is still low (after theLSB first data has been transmitted), the device willclock out zeros indefinitely.

FIGURE 5-1: Communication with MCP3201 device using MSB first Format.

FIGURE 5-2: Communication with MCP3201 device using LSB first Format.

CS

CLK

DOUT

tCYC

POWERDOWN

TSUCS

TSAMPLE tCONVtDATA**

* After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output LSB first data, followedby zeros indefinitely. See Figure 5-2 below.

** tDATA: during this time, the bias current and the comparator power-down and the reference input becomes a high-impedancenode, leaving the CLK running to clock out the LSB-first data or zeros.

TCSH

NULLBIT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0*

HI-Z HI-ZB11 B10 B9 B8NULL

BIT

CS

CLK

DOUT

tCYC

POWER DOWNtSUCS

tSAMPLE tCONV tDATA**

* After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros indefinitely.

** tDATA: during this time, the bias current and the comparator power-down and the reference input becomes a high-impedancenode, leaving the CLK running to clock out the LSB-first data or zeros.

tCSH

NULLBIT B11B10B9 B8 B7 B6 B5 B4 B3 B2 B1 B0HI-Z B1 B2 B3 B4 B5 B6 B7 B8 B9 B10B11* HI-Z


MCP3201

NOTES:


MCP3201

6.0 APPLICATIONS INFORMATION

6.1 Using the MCP3201 Device with Microcontroller SPI Ports

With most microcontroller SPI ports, it is required toclock out eight bits at a time. If this is the case, it will benecessary to provide more clocks than are required forthe MCP3201. As an example, Figure 6-1 andFigure 6-2 show how the MCP3201 device can beinterfaced to a microcontroller with a standard SPI port.Since the MCP3201 always clocks data out on thefalling edge of clock, the MCU SPI port must beconfigured to match this operation. SPI Mode 0,0 (clockidles low) and SPI Mode 1,1 (clock idles high) are bothcompatible with the MCP3201. Figure 6-1 depicts theoperation shown in SPI Mode 0,0, which requires thatthe CLK from the microcontroller idles in the ‘low’ state.As shown in the diagram, the MSB is clocked out of theA/D Converter on the falling edge of the third clockpulse. After the first eight clocks have been sent to the

device, the microcontroller’s receive buffer will containtwo unknown bits (the output is at high-impedance forthe first two clocks), the null bit and the highest orderfive bits of the conversion. After the second eight clockshave been sent to the device, the MCU receive registerwill contain the lowest-order seven bits and the B1 bitrepeated as the A/D Converter has begun to shift outLSB first data with the extra clock. Typical procedurewould then call for the lower-order byte of data to beshifted right by one bit to remove the extra B1 bit. TheB7 bit is then transferred from the high-order byte to thelower-order byte, and then the higher-order byte isshifted one bit to the right as well. Easier manipulationof the converted data can be obtained by using thismethod.

Figure 6-2 shows the same thing in SPI Mode 1,1which requires that the clock idles in the high state. Aswith mode 0,0, the A/D Converter outputs data on thefalling edge of the clock and the MCU latches data fromthe A/D Converter in on the rising edge of the clock.

FIGURE 6-1: SPI Communication using 8-bit segments (Mode 0,0: SCLK idles low).

FIGURE 6-2: SPI Communication using 8-bit segments (Mode 1,1: SCLK idles high).

CS

CLK 9 10 11 12 13 14 15 16

DOUTNULLBIT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

HI-Z

B7 B6 B5 B4 B3 B2 B1 B0B11 B10 B9 B8? ? 0

MCU latches data from A/D

Data is clocked out of A/DConverter on falling edges

Converter on rising edges of SCLK

1 2 3 4 5 6 7 8

HI-ZB1

B1

LSB first data beginsto come out

B2

Data stored into MCU receive registerafter transmission of first 8 bits

Data stored into MCU receive registerafter transmission of second 8 bits

CS

CLK 9 10 11 12 13 14 15 16

DOUTNULL

BITB11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0HI-Z

B7 B6 B5 B4 B3 B2 B1 B0B11 B10 B9 B8? ? 0

MCU latches data from A/D

Data is clocked out of A/DConverter on falling edges

Converter on rising edges of SCLK

1 2 3 4 5 6 7 8

B1

B1

LSB first data beginsto come out

HI-Z

Data stored into MCU receive registerafter transmission of first 8 bits

Data stored into MCU receive registerafter transmission of second 8 bits


MCP3201

6.2 Maintaining Minimum Clock Speed

When the MCP3201 initiates the sample period, chargeis stored on the sample capacitor. When the sampleperiod is complete, the device converts one bit for eachclock that is received. It is important for the user to notethat a slow clock rate will allow charge to bleed off thesample cap while the conversion is taking place. At85°C (worst-case condition), the part will maintainproper charge on the sample capacitor for at least1.2 ms after the sample period has ended. This meansthat the time between the end of the sample period andthe time that all 12 data bits have been clocked outmust not exceed 1.2 ms (effective clock frequency of10 kHz). Failure to meet this criteria may inducelinearity errors into the conversion outside the ratedspecifications. It should be noted that during the entireconversion cycle, the A/D Converter does not require aconstant clock speed or duty cycle, as long as all timingspecifications are met.

6.3 Buffering/Filtering the Analog Inputs

If the signal source for the A/D Converter is not a low-impedance source, it will have to be bufferedor inaccurate conversion results may occur.See Figure 4-2. It is also recommended that a filter beused to eliminate any signals that may be aliased backinto the conversion results. This is illustrated inFigure 6-3 where an op amp is used to drive the analoginput of the MCP3201 device. This amplifier provides alow-impedance source for the converter input and alow-pass filter, which eliminates unwanted high-frequency noise.

Low-pass (anti-aliasing) filters can be designed usingMicrochip’s interactive FilterLab® software. FilterLabwill calculate capacitor and resistor values, as well asdetermine the number of poles that are required for theapplication. For more information on filtering signals,see application note AN699 “Anti-Aliasing AnalogFilters for Data Acquisition Systems.”

FIGURE 6-3: The MCP601 Operational Amplifier is used to implement a 2nd order anti-aliasing filter for the signal being converted by the MCP3201 device.

MCP3201

VDD

10 µF

IN-

IN+

-

+VIN

C1

C2

VREF

4.096VReference

1 µF

10 µF0.1 µF

MCP601R1

R2

R3R4

MCP1541CL


MCP3201

6.4 Layout Considerations

When laying out a printed circuit board for use withanalog components, care should be taken to reducenoise wherever possible. A bypass capacitor shouldalways be used with this device and should be placedas close as possible to the device pin. A bypasscapacitor value of 1 µF is recommended.

Digital and analog traces should be separated as muchas possible on the board and no traces should rununderneath the device or the bypass capacitor. Extraprecautions should be taken to keep traces with high-frequency signals (such as clock lines) as far aspossible from analog traces.

Use of an analog ground plane is recommended inorder to keep the ground potential the same for alldevices on the board. Providing VDD connections todevices in a “star” configuration can also reduce noiseby eliminating current return paths and associatederrors. See Figure 6-4. For more information on layouttips when using A/D Converter, refer to AN688 “LayoutTips for 12-Bit A/D Converter Applications”.

FIGURE 6-4: VDD traces arranged in a ‘Star’ configuration in order to reduce errors caused by current return paths.

VDD

Connection

Device 1

Device 2

Device 3

Device 4


MCP3201

NOTES:


MCP3201

7.0 PACKAGING INFORMATION

7.1 Package Marking Information

Legend: XX...X Customer-specific informationY Year code (last digit of calendar year)YY Year code (last 2 digits of calendar year)WW Week code (week of January 1 is week ‘01’)NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn)* This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it willbe carried over to the next line, thus limiting the number of availablecharacters for customer-specific information.

3e

3e

8-Lead MSOP (3x3 mm) Example

8-Lead PDIP (300 mil) Example

XXXXXXXXXXXXXNNN

YYWW

8-Lead SOIC (3.90 mm) Example

NNN

8-Lead TSSOP (4.4 mm) Example

3201CI130256

3201-BI/P ^^ 256

11303e

3201-BISN ^^11303e

201CI130256

256


MCP3201

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A1

A2c

L1 L

φ

) /.


MCP3201

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging


MCP3201

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MCP3201



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MCP3201



MCP3201

NOTES:


MCP3201

APPENDIX A: REVISION HISTORY

Revision F (August 2011)

• Updated Product Identification System section.

- Corrected marking drawings for MSOP packages.

- Updated PDIP, SOIC, and TSSOP package specification drawings.

Revision E (November 2008)

The following is the list of modifications:

1. Updated Section 7.0 “Packaging Informa-tion”.

2. Updated Product Identification Systemsection.

Revision D (January 2007)


1. This revision includes updates to the packagingdiagrams.

Revision C (August 2001)


1. This revision includes undocumented changes.

Revision B (August 1999)


1. This revision includes undocumented changes.

Revision A (September 1998)

• Original release of this document.


MCP3201

NOTES:


MCP3201

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Device: MCP3201: 12-Bit A/D Converter w/SPI InterfaceMCP3201T: 12-Bit A/D Converter w/SPI Interface

(Tape and Reel)

Grade: B: = ± LSB max INL (MSOP and TSSOP not available)C: = ± LSB max INL

Temperature Range:

I = -40°C to+85°C(Industrial)

Package: MS = Plastic Micro Small Outline (MSOP), 8-leadP = Plastic DIP (300 mil Body), 8-leadSN = Plastic SOIC (150 mil Body), 8-leadST = Plastic TSSOP (4.4 mm), 8-lead

Examples:

a) MCP3201-BI/P: B Grade,Industrial Temperature,8LD PDIP package.

b) MCP3201-BI/SN: B Grade,Industrial Temperature,8LD SOIC package.

c) MCP3201-CI/P: C Grade,Industrial Temperature,8LD PDIP package.

d) MCP3201-CI/MS: C Grade,Industrial Temperature,8LD MSOP package.

e) MCP3201-CI/SN: C Grade,Industrial Temperature,8LD SOIC package.

f) MCP3201-CI/ST: C Grade,Industrial Temperature,8LD TSSOP package.

g) MCP3201T-BI/SN: Tape and Reel, B Grade,Industrial Temperature,8LD SOIC package.

h) MCP3201T-CI/MS: Tape and Reel, C Grade,Industrial Temperature,8LD MSOP package.

i) MCP3201T-CI/SN: Tape and Reel, C Grade,Industrial Temperature,8LD SOIC package.

j) MCP3201T-CI/ST: Tape and Reel, C Grade,Industrial Temperature,8LD TSSOP package.

PART NO. X /XXX

Grade PackageTemperatureRange

Device


MCP3201

NOTES:


Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED, WRITTEN OR ORAL, STATUTORY OROTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY, PERFORMANCE, MERCHANTABILITY ORFITNESS FOR PURPOSE. Microchip disclaims all liabilityarising from this information and its use. Use of Microchipdevices in life support and/or safety applications is entirely atthe buyer’s risk, and the buyer agrees to defend, indemnify andhold harmless Microchip from any and all damages, claims,suits, or expenses resulting from such use. No licenses areconveyed, implicitly or otherwise, under any Microchipintellectual property rights.

1998-2011 Microchip Technology Inc.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

© 1998-2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.

Printed on recycled paper.

ISBN: 978-1-61341-572-6

DS21290F-page 39

Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.


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Mcp 3201

Documents

affect linearity

relates linearity

current package

power supply

free jedec

eventually

include mold

0mcu latches