MCA2050

Computer Organization And Architecture(MCA2050)

1. The ___________ model refers to both the style and method of problem description.

a) Problem description b) Utilized parallelism

c) Procedural style d) Data-driven

2. In a ___________ , the algorithm for solving the problem is stated.



3. ___________ execution is characterized by the rule that an operation is activated as soon as all the needed input data is available.



4. _________ was the first mechanical device, invented by Blaise Pascal.

a) Procedural style b) Data-driven c) Pascaline d) IAS machine

5. ___________ was a new version of the EDVAC, which was built by von Neumann.

a) Procedural style b) Data-driven c) Pascaline d) IAS machine

6. The fourth generation of computers was marked by use of Integrated Circuits (ICs) in place of transistors.

a) True b) False c) Cant determined

7. Personal Computers (PCs), also called as Microcomputers.


8. All threads of a process share its virtual address space and system resources.


9. When the scheduler selects a process for execution, its state is changed from ready-to-run to the wait state.


10. Concurrent execution is the temporal behavior of the _______ Model.

a)N-client 1-server b)1-client N-server c) N-client N-server d)N-client M-server

11. During selection, the ranks of all competing clients are computed and the client with the highest rank is scheduled for service.


12. In ___________ all processing units execute the same instruction at any given clock cycle.

a) Single Instruction Multiple Data b) Multiple Instruction Single Data

c) Multiple Instruction Multiple Data d) None of the above

13. In which system a single data stream is fed into multiple processing units?



14. ___________ is the most common type of parallel computer.



15. Parallel computers offer the potential to concentrate computational resources on important computational problems


16. Advances in instruction-level parallelism dominated computer architecture from the mid-1990s until the mid-2000s .


17. Parallelism occurring during execution is called –––––––––––––.



18. Parallelism at the instruction level is also called middle-grained parallelism.


19. Data parallelism is regular, whereas functional parallelism, with the execution of loop-level parallelism, is usually irregular. (True/


20. The computational model consists of the subsequent three abstractions:

1. The basic items of computations 2. The problem description model 3. The execution model

a) Only 1 b) Only 2 c) Only1,2 d) All1,2,3

21. The Turing machine architecture operates by manipulating symbols on a tape.

a) Neumann b) Turing c) Both d) None

22. Match the following

1. Messages i) applicative model2. Arguments ii) predicate-logic-based model3. Elements iii) objects-based modela)1-I,2-ii,3-iii b)1-iii,2-ii,3-I c)1-iii,2-I,3-ii d)1-ii,2-I,3-iii

23. Every ________presents the resources required to execute a program.

a) Process b) Threads c) Both d) None

24. A _________is the entity within a process that can be scheduled for execution.

a) Process b) Threads c) Both d) None

25. A _______contains all the information relevant to the whole life cycle of a process.

a) Process b) Thread c) PCB d) None of the above

26. EDSAC

a) Electronic Delay Storage Automatic Calculator

b) Electronic Discrete Storage Automatic Computer

c) Electric Discrete Storage Automatic Computer

d) Electric Discrete Storage Automatic Calculator

27. The ____________ had the ability to integrate the functions of a computer’s Central Processing Unit (CPU) on a single-integrated circuit.

a) Processor b) Microprocessor c) Supercomputerd) Mainframe

28. _______________ computers used to support typical applications like business data support and large-scale scientific computing.

a) Processor b) Microprocessor c) Supercomputer d) Mainframe

29. The performance requirement in an embedded application is real-time execution. (True/False)

30. ________________ is the chief objective of embedded computers.

a) Maximum Cost b) Minimum cost c) Minimum Resource d) Both b,c

31. The world’s first designer was __________________.

a) F.W Jordan b) Charles Babbage c) Neuron d) None

32. ___________________ acts as the boundary between software and hardware.

a) ISA b) CISC c) RISC d) Both b,c

33. ISA has ___________________ general-purpose registers.

a)8 b)16 c)32 d)64

34. CISC stands for ___________________.

a) Complex instruction set computer b) Complete instruction set computer

c) Complicate instruction set computer d) Complex instruction set control

35. The designer should never plan for the technology changes that would lead to the success of the computer. (True/False)

36. _______________ are electronic circuits manufactured by forming interconnections between semiconductor devices.

a) Integrated circuits b) microchips c) Both d) None

37. Performance of the computer is improved by ____________________.

a) Adopting parallelism b) microchips c) Both d) None

38. The ability of the servers to expand its processors and disks is known as _________________.

a) Adopting parallelism b) Scalability c) Pipelining d) Temporal Locality

39. The main objective of ____________________ is to extend beyond the instruction implementation to cut the total time taken to complete the instruction series.


40. ____________________ declares that the item referred in the recent times has potential to be accessed in the near future.


41. ____________________ states that the items nearby the location of the recently used items may also be referred close together in time.

a) Scalability b) Pipelining c) Temporal Locality d) Spatial Locality

42. ____________________ can normally be dealt for performance or cost benefits.

a) Cost Efficiency b) Power Efficiency c) Both d) None

43. ____________________ is the product of the transistor switching and the switching rate.

a) Spatial Locality b) Temporal Locality c) Powerd) Dynamic Power

44. The number of switching transistor rate is proportional to ___________ and the performance is proportional to ______________.

a)High issue ratesb) sustained performance c) Both d) None


1. Dependability i) the standard time for a particular job is constrained and the number of occurrences when the maximum time is exceeded

2. Scalability ii) Speed, though in varying degrees, is an important factor in all architectures

3. Real-time performance iii) Servers are highly scalable in terms of the increasing demand or requirements

4. Soft real-time iv) Breakdown of this type of a server is extremely more disastrous than the breakdown of a single independent system

a)1-I,2-ii,3-iii,4-iv b)1-Ii,2-i,3-iii,4-iv c)1-Iv,2-iii,3-ii,4-i d)1-I,2-iii,3-ii,4-iv

46. (RISC)

a) Reduced instruction set computer b) Related instruction set computer

c) Reduced instruction set controller d) Reduced instruction subset computer

47. _____ uses a capacitor to store each bit of data, and the level of charge on each capacitor determines whether that bit is a logical 1 or 0.

a) SRAM b) Semi conductor DRAM c) DRAM d) Semiconductor SRAM

48. The bits of the instruction are divided into groups called ___________.

a) Fields b) Records c) Value d) All of the above

49. ______________ uses an implied accumulator (AC) register for all data manipulation.

a)Two-address instructions b)One-address instructions

c) Three-address instructions d)Four-address instructions

50. Selection of operands during program execution does not depend on the addressing mode of the instruction. (True/ False)

51. Hardware-accessible units of memory larger than one cell are called words. (True/ False)

52. ______________ instructions are implied mode instructions.

a)Two-address instructions b)One-address instructions

c) Three-address instructions d)Zero-address instructions

53. Relative Address Mode is applied often with ___________ instruction.

a) Jump Mode b) Register Mode c) Branch Mode d) Indirect Mode

54. The _______________ is a special CPU register that contains an index value.

a) Branch Register b) Direct Registerc) Index Register c) None

55. In an improved instruction execution cycle, we can introduce a third cycle known as the _____.

a) Branch Cycle b) Interrupt Cycle c) Both d) None

56. MAR

a) Memory area Register b) Minimized area Register

c) Memory Address Register d) Minimized Address Register

57. MBR

a) Memory Buffer Register b) Minimized Buffer Register

c) Memory Break Register d) Maximized Buffer Register

58. When processed in the CPU, the instructions are fetched from ______________ locations and implemented.

a) Consecutive Memory b) Sequenced Memory c) Both d) None

59. The ______________ and ______________ are identical in their use but sometimes they are used to denote different addressing modes.

a) Branch b) jump c) Both d) None

60. One of the key features of the MIPS architecture is the ____________.

a) Irregular register set b) Regular register set c) Both d) None

61. Two separate 32-bit registers called ____________ and ___________ are provided for the integer multiplication and division instructions.

a)HI, LO b) PC,IR c)HI,PC d) IR,LO

62. The instruction format is generally represented in a _______ box denoting the bits of the instruction as they appear in memory words or in a control register.

a) Diamond b) Square c) Rectangular d) None

The bits of the instruction are separated into groups called fields.


1. Operation Code i) Specifies the way the operand or the effective address is determined.2. Address Field ii) designates a memory address or a processor register3. Mode Field iii) Specifies the operation to be performed. a) 1-I,2-ii,3-iii b)1-ii,2-iii,3-I c) 1-iii,2-ii,3-I d)1-iii,2-I,3-ii

64. LIFO implies that the last item placed on the stack is the first item to be taken out of the stack.(TRUE/FALSE)

65. The operands in this mode are specified implicitly in the explanation of the instruction.

A) Data Mode b) Implied Modec) Register Mode d) None

66. The principal features of the MIPS architecture are as follows:

i) It has a five-stage execution pipeline: fetch, decode, execute, memory-access, write-result.

ii) It has a regular instruction set where all instructions are 32-bit.

iii) There are three-operand arithmetical and logical instructions.

iv) It consists of 16 general-purpose registers of 32-bits each.

a) All true b) All False c) Only I,ii,iii d) Only iv


1 MIPS-I i) This is the original 32-bit instruction set; and is still common2. MIPS-II ii) It is an improved instruction set with dozens of new instructions3. MIPS-III iii) It has a 64-bit instruction set used by the R4000 series4 MIPS-IV iv) It is an upgrade of the MIPS III a)1-I,2-ii,3-iii,4-iv b)1-ii,2-iii,3-I,4-iv c) 1-iii,2-ii,3-I,4-iv d)1-iii,2-I,3-ii,4-iv

68. An implementation technique by which the execution of multiple instructions can be overlapped is called _________.

a) Pipelining b) Virtual parallelism c) Load Memory Data d) None

69. Pipelining is also called _______________.

a) Pipelining b) Virtual parallelism c) Load Memory Data d) None

70. LMD is the short for ___________________.

a) Lead Memory Data b) Load Merge Data c) Load Memory Data d) None

71. The instruction fetch segment can be implemented by means of a _____________.

a) Encoder b) Multiplexer c ) Decoder d) FIFO Buffer

72. ____________ pipelines perform only one pre-defined fixed functions at specific times in a forward direction from one stage to next stage.

a)Linear b) Non Linear c) Scalard) None

73. ________________ pipelines can perform more than one operation at a time as they have the provision to be reconfigured to execute variable functions at different times.

a)Linear b) Non Linear c) Scalard) None

74. Non-Linear pipelines are also called ____________________ .

a) Dynamic pipelines b) Static Pipelines c) Both d) None

75. _______________ are the situations that stop the next instruction in the instruction stream from being executed during its designated clock cycle.

a)Scaled b)Hazards c) Dynamic d) None

76. Structural Hazards are also called ________________ .

a)Hazards b) Resource conflicts c) Data dependency d) Branch difficulties

77. Data Hazards are also called ____________________ .


78. Control Hazards are also called _______________.


79. Pipelining has a major effect on changing the relative timing of instructions by overlapping their execution. (True/False).

80. The register read of XOR instruction occurs in clock cycle ________________ .

a)1 b)4 c)6 d)10

81. __________ cause a greater performance failure for a pipeline than ______________.

a)Control Hazards, data hazards b) data hazards, Control Hazards d) None

82. If the PC is changed by the branch to its target address, then it is known as ______________ branch; else it is known as ___________.

a)Taken, not taken b)Taken,untaken c) Both d) None

83. The problem posed due to data hazards can be solved with a simple hardware technique called ___________________ .

a) Forwarding b) Backspacing c) Booth d) None

84. Forwarding is also called _________.

a) Bypassing b) short-circuiting c) Both d) None

85. ______________ is the method of holding or deleting any instructions after the branch until the branch destination is known.

a) Freeze the pipeline b) flush the pipeline c) Both d) None

86. Assume each branch as __________________ technique simply allows the hardware to continue as if the branch were not executed.

a) Taken b) not-taken c) Both d) None

87. _____________ states the number of cycles lost to load-use stalls.

a) Load-stall count b) Lead Stall count c) Both d) None

88. _____________ instruction takes a source label and stores its address into the destination register.

a) LD b) HD c) SD d) None

89. ____________ stores the source register’s value plus an immediate value offset and stores it in the destination register.

a) LDR b) HDR c) SDR d) None

90. A ___________ hazard causes the pipeline performance to degrade the ideal performance.

a) Control b) Data c) Stall d) All

91. CPI is the abbreviation for _____________.

a) Cycles per Instruction c) Complexity per Instruction

c) Covered per Instruction d) created per Instruction

92. The full form of MIPS is ___________________.

a) Microprocessor with Interlocked Pipeline Stages

b) Microprocessor without Interlocked Pipeline Stages

c) Microprocessor without Inter Pipeline Stages

d) Microprocessor without Intel Pipeline Stages

93. In recent processors dependencies are resolved ______________, by extra hardware.

a) Dynamically b) Directc) Static d) None

94. In ________________ the result into the register file is written or stored into the memory.

a) Read Back Operand b) Write Beck Operand

c) R/w’ Back Operand d) Write Back Operand

95. In Decode Instruction/Register Fetch operation, the _______________ and the __________ are determined and the register file is accessed to read the registers.

a)Opcode, operand specifiers b) operand specifiers, Opcode

96. While processing operates instructions, RISC pipelines have to cope only with ________.

a) Memory Operands b) Register Operands

c) Both d) None

97. In RISC architecture, instructions are of a uniform length (True/ False).

98. Microprocessors which follow the CISC philosophy.

a) Intel 80x86 b) Motorola 68K series c) Both d) None

99. ______________ adds two numbers and produces an arithmetic sum.

a) Carry-propagation adder a) Half Adder b) Full Adder d) None

100. In traditional pipeline implementations, load and store instructions are processed by the ______.

a) Slave b) Master Pipeline c) Pipeline d) None

101. The consistency of instruction completion with that of sequential instruction execution is specified b _______________.

a) Processed consistency b) Processor consistency d) None

102. Reordering of memory accesses is not allowed by the processor which endorses weak memory consistency does not allow (True/False).

103. _____________ is not needed in single queue method.

a) Pipelining b) Renaming c) Both d) None

104. In reservation stations, the instruction issue does not follow the FIFO order. (True/ False).

105. The number of pipeline stages used to perform a given task are:,

1. Specification of the subtasks to be performed in each of the pipeline stages,

2. Layout of the stage sequence, that is, whether the stages are used in a strict sequential manner or some stages are recycled,

3. Use of bypassing

4. Timing of the pipeline operations, that is, whether pipeline operations are controlled synchronously or asynchronously.

a)TTTT b)FFFF c)TTFF d)FFTT

106. Intel processor (i860) which has

a)VLIW b)scalar c) Both d) None

107. The design space of pipelines can be sub divided into

a) basic layout of a pipeline b)dependency resolution c) Both d) None

108.___________________ adds three input numbers and produces one sum output.

a)CPA b)CSA c)LMD d) RISC

109. The methodology, which involves separation of dependent instructions, minimizes data/structural hazards and consequential stalls is termed as__________________.

A) Static scheduling B) Dynamic scheduling c) Memory scheduling d) none

110. To commence with the execution of the SUBD, we need to separatethe issue method into 2 parts: firstly ___________ and secondly___________.

a) Check the system hazards, wait for the system absence of a data hazardsb) Check the structural hazards, wait for the absence of a data hazardsc) Check the structural ID cable, wait for the instruction of a system d) None of these

111. _______________ stage precedes the issue phase.

a) An of system b) An instruction of system admin c) An instruction fetch

112. The ________________ stage follows the read operands stage similarto the DLX pipeline.

a) EX b) PX C) EX D) XT

113. When the pipeline executes ____________________ before ADDD, it violates the interdependence between instructions leading to wrong execution.

a) MULTB, DIV b) SUMC, DIVC c) SUBD, ADDD d) ADDB, ADDC

114. The objective of scoreboard is achieved with ______________ or______________________ functional units or both.

a) Flag, instruction b) Pipelined, multiple c) pipelined, single 115. The source operand for ADDD is ____________, and is similar to destination register of SUBD.

a) F6 B) F1 C) F9 d) F8

116. The FU status ____________________ shows whether it is busy or idle.

a) Busy b) Free c) Wait d) none of these

117.Tumasulo scheme was invented by ______________.

a) Harbor Tomasulo b) Robert Tomasulo c) Tarboro Tomasulo 118. The ________________ could hold 3 operations for the FP adder and 2 for the FPmultiplier.

a) IBM 340/876 B) IBM 324/87 c) IBM 360/91 d) IBM 213/90

119. The ____________ and ______________ are used to store the data/addresses that come from or go to memory.

a) Load buffers, store buffers b) Load instruction, store buffer c) Load operating system, load buffers d) none of these

120. The branch-prediction buffer is accessed during the ______ stage.

a) ID b) EID c) EIID d) none of these

121. The ______ field helps check the addresses of the known branch instructions

a) Data b) system c) Lookup d) none

122. Buffering the actual Target-Instructions allow ____________.

a)Branch Folding b) software Folding c) data Folding d) none of these

123. ____________ makes use of dynamic data dependences to select when to carry out instructions.

a) Software-based speculation b) Hardware-based speculationc) ID based speculation d) none of these 124. Hardware-based speculation is more beneficial whenever the hardware-based branch prediction is higher-up to software___________________ performed at time of compilation

a) Software-based branch prediction b) Hardware-based branch predictionc) Flag-based branch prediction d) none of these

125. Hardware-based speculation helps to maintain an entirely accurate exception model for ____________.

a) User instruction b) Speculated instructions c) administrator instruction d) none of these

126. Hardware-based speculation demands neither ______________ nor____________.

a) Computation, cookies code b) Compensation, bookkeeping codec) None of these

127. Branch instruction like Pentium is also known as.............................

a) Wait instruction b) jump instruction c) access instruction d) none of these 128. It is possible to have Re-locatable code in case of absolute addresses (True/False).

a) True b) False

129. ________ is a flow altering instruction that is required to be handled ina special manner in pipelined processorsa) Instruction b) Flag c) Branch d) none of these

130. Wasteful work done by pipeline for a considerable time is called the_______________.

a) Branch services b) Branch information c) Branch penalty d) Branch system

131. A number of processors such as _________ and __________ make use of delayed execution for procedure calls as well as branching.

a) SPRAC, MTIP b) SPARC, MIPS c) STRP, TIMPS d) SVRC, MTIPS

132. If any valuable instruction cannot be moved into delay slot, ___________ is placed.

a) NO operation (NOP) b) DO operations c) Information d) none of these

133. Branch processing has two aspects ________ and ________. a) Layout, micro-system b) Layout, micro-architectural implementationc) Layout, mini- architectural implementation d) none these 134. Name the major sub tasks of branch processing.

a) Detecting system b) Detecting instruction c) Detecting branchesd) None of these

135. In case of Fixed Branch Prediction, the branch is presumed to be either_________ or ________________.

a) Never taken, always taken b) always taken, Never takenc) Instruction taken, always taken d) none of these

136. Static strategy makes use of _______________ for predicting whether the branch is taken.

a) Instruction code b) Instruction opcode c) data instruction d) none

137. IA-64 architecture is considered as a load/store architecture having 64-bit ____________ as well as 64-bit broad ___________ .

a) data address, system b) system information c) addresses, registers d) none

138. IA-64 model is also called _______________ .

a) Explicitly Parallel Instruction Computing (EPIC)b) Explicitly Permanent Instruction Computing (EPIC)c) Explicitly Parallel Information Computing (EPIC)d) None of these

139. Trimedia processor may be the closest existing processor to a____________________________.a) “Classic” VLLW Processor b) “Classic” VLIW Processor c) “Classic” VIIW Processor c) “Classic” LLIW Processor

140. State two uses of Trimedia TM32 CPU.

a) Set top boxes and advanced televisions b) cable televisions and d-TVc) None of these

141. _______________ directly deals with the processor.

a) Main memory b) secondary memory c) primary memory d) none

142. ____________ is a high-speed memory which provides backup storage

a) Auxiliary memory b) system memory c) primary memory d) none

143. A ___________ memory is an intermediate memory between two memories having large difference between their speeds of operation.

a) Cache b) register c) Flag d) none of these

144. If the processor detects a word in cache, while referring that word in main memory is known to produce a _________________.

a) Hit b) cool c) RJ-45 d) none of these

145. When both instructions and data are stored into the same cache, the design is called the ______________ cache design.

a) Architecture b) unified c) un-unified d) none of these

146. TLB stands for ____________________.

a) Translation dataside Buffer b) Translation system Buffer c) Translation register buffer d) Translation Lookside Buffer

147. The translation of main memory address to the cache memory address is known as _________________.

a) Sowing b) mapping c) swooping d) none of these

148. _________________ memories are expensive compared to RAMs.

a) Non-Associative b) Associative c) Auxiliary d) none

149. A design where instructions and data are stored in different caches for execution conveniences is called ______________ cache design.

a) Split b) Aux c) Flag d) none of these

150. I-Cache denotes _________________________.a) Instruction Cache b) Information of Cache c) Instruction of Flag d) Instruction register

151. ______________ affects the clock cycle rate of the processor.

a) Instruction time b) Hit Time c) System Time d) none of these

152. Average memory access time = Hit time + Miss rate x _____________.

a) Miss data b) Miss Information c) Miss Penalty d) none

153. ILP stands for _______________________.

a) Instruction-Level Palmist b) Instruction-Level Parallelismc) Infraction-Level Parallelism d) none of these

154. TLP is the abbreviation for _____________________.

a) Thread-Level Parallelism b) Thad-Level Parallelismc) Thread-Level palmist d) none of these

155. __________________ is a technique aimed at enhancing the efficiency of memory usages in a system

a) Interleaved Memory Organisation b) data Memory organisationc) Instruction Memory Organisation d) none of these

156. __________________ share common data and address buses.

a) MARs and MRD b) CARTs and MRS c) MARs and MDRs d) none

157. The memory bandwidth is upper-bounded by ____________ and lower-bounded by __________________.

a) m,6 b) m,3 c) m,9 d) m,1

158. __________________ are assigned in the high-order interleaved memory in each memory Module.

a) Sequential information b) Sequential addresses c) Sequential instruction d) none of these

159. ___________ model is a contract between processes and a data store.

a) Consistency b) system memory c) inconsistency d) none

160. The two categories of consistency models are ______ and _________.

a) Strong, Weak b) GTI,FTI c) Structure model d) none of these

161.____________ is able to function on one whole vector in a single instruction.

a) Data processors b) Vector processors c) Multiple processors

162. They also take advantage of ____________ in huge scientific as well as multimedia applications.

a) Data parallelism b) strip parallelism c) single parallelism d) none

163. The memory-memory vector processors can prove to be much efficient in case the vectors are sufficiently long. (True/False).

a) True b) False

165. The scalar registers are linked to the functional units with the help of a pair of ________.

a) Crossbars b) stretchbar c) rollbar d) none of these

166. ______________ correspond to vector load or vector store.

A) Simple-memory instruction b) Multiple-memory instructionc) vector-memory instructions d) none of these

167. Functional hazards are the conflicts in register accesses (True/False).

a) True b) False

168. The instance of larger vectors is dealt with by a method called_______________.

a) Strip memory b) Strip operation c) Strip mining d) none of these

169. Vector elements are saved in the form of ______________ in memory.

a) Horizontal words b) parallel words c) Sequential words d) none of these 170. List two factors which enable a program to run successfully in vector mode.

a) System program & system capability b) User information & system capabilityc) Structure of the program & capability of the compiler

171. There does not exist any variation in the capability of compilers to decide if a loop can be vectorised (True/False).

a) True b) False

172. ______________it can pack 10 to 20 transistors in a single chip.

a) Large Scale integration b) Small scale integration c) none of these

173. The various types of vector instructions for a register-register vector these are

(a) Vector-scalar instructions (b) Vector-vector instructions (c) Vector-memory instructions (d) Gather and scatter instructions (e) Masking instructions (f) Vector reduction instructions

I) A,c,d,e II) a,d,e,f III) b,c,e,f IV) none of thesev) All of these

174. _______________Using these instructions, one or two vector operands are fetched from respective vector registers and produce results in another vector register.

a) Vector-scalar instructions b) Gather and scatter instructions c) Masking instruction d) vector-vector instructions

175.A problem is broken into a discrete series of ______________ .

a) Instructions b) Information c) Flag d) register

176. _______________ provides facilities for simultaneous processing of various set of data or simultaneous execution of multiple instructions.

a) Micro Computer b) Mini Computer c) Parallel Computer d) none of these

177. Parallel processing in uni-processor computer is said to_____________ parallel processing.

a) Manual or systematic b) simulated or virtual c) none of these

178. SIMD stands for ________________.

a) Single-Instruction, Multiple Data b) signal- information, Manual datac) Single-Instruction, Manual data d) none of these

179. Flynn classified computing architectures into SISD, MISD, SIMD and_______________________ .

a) RMIE B) CRTI c) MIMD d) RDIE

180. SIMD is known as ____________ because its basic unit of organisation is the vector.

a) Data processing b) vector processing c) vector-vector processing

181. Superscalar SISD machines use one property of the instruction stream by the name of ___________.

a) instruction-level parallelism b) Resister-level parallelismc) system-level parallelism d) none of these

182. MPP is the acronym for ____________.

a) Massively Parallel Processor b) Master Parallel Processor c) Massively Parallel Program d) Master parallel process

183. All highly parallel computers have problems concerned with______________________.

a) Input data b) output of data c) Input and output of data d) none of these

184. The two parallel computers manufacturers of coarse-grained architecture are ____________________.

a) Nrube and Thinking Machines Inc b) ncube and Thinking Machines Incc) Ntube and Thinking Machines Inc d) none of these

185. SPMD is the acronym for ____________________.

a) Single program multiple data b) signal process multiple datac) serial program multiple data d) server process multiple data

186. _____________________ is the first of the CRAY family.

a) CM2 b) CM6 c) CM1 d) CM8

187. The latest system in the CRAY family is _________________.

a) CM5 b) CM3 c) CM7 d) CM9

188.The first vector machine was _____________.

a) CDC Star 200 b) CDC Star 100 c) CDC Star 400 d) CDC Star 150

189.________ Operations get the scalar inputs present in scalar registers.

a) System b) RID c) Vector d) none of these

190._____________ specifies the count of instructions completed per unit time.

a) Instruction throughput b) Data throughputc) Operator throughput d) none of these

191. Pipelining is also called ________________ as it provides an essence of parallelism only at the instruction level.

a) Virtual Parallelism b) Vector Parallelismc) Instruction Parallelism d) none of these

192. Linear pipelines perform only one pre-defined fixed functions at specific times in a forward direction. (True/False)

a)True b) False

193.All multiprocessing computers are ______________ computers.

a) MIID b) MIME c) EIDE d) MIMD194. In UMA machines, each memory word cannot be read as quickly as other memory word. (True/ False).

a) True b) False

195. NUMA stands for _____________________.

a) Non Uniform Memory Access b) No Uniform Memory Accessc) Non Uric Memory Access d) Non Uniform machine Access

196. _______________ was a key problem in the data-parallel architectures since they aimed at massively parallel systems

a) Remote loads b) software loads c) data load d) none of these

197. _______________Systems with multiple CPUs, which are capable of independently executing different tasks in parallel.

a) Processor b) microprocessor c) Multiprocessor d) none

198._________________is associated with each segment in the pipeline to provide isolation between each segment.

a) Flag b) Register c) Memory d) none of these

199. The main design issues in scalable parallel computers are as follows a) Processor design b) Interconnection network design c) Memory system design d) I/O system design

I) A,c,d only II) b,c,d only III) a,b,c only IV) all of these

200. ____________ signifies those systems attributes which are visible to a developer.

a) System Architecture b) software Architecture c) Computer architecture

201. _______________ signifies operational units in addition to the connection between them that recognize the specification of architecture.

a) Computer system b) Computer application c) Computer organization d) none of these

202. RAM stands for ________________.

a) Random Access machine b) Resources access machine c) Random Access memory d) none of these

203. Physical components on which data is stored are called __________.

a) Register b) disk c) Storage Media d) none of these

204. RPM is the acronym for ______________.

a) Revolutions per machine b) Reservation per machine c) Reservation per minute d) Revolutions per minute

205. To read data from ______________ , a laser beam is directed on the surface of a spinning disk.

a) CD-RAM b) DVD-ROM c) CD-ROM d) DVD-RAM

206. __________ is used in computers for backup storage.

a) Magnetic devices b) Magic disk c) Magic devices d) Magnetic tape

207. __________ from the processor is attached to all peripheral interfaces.

a) I/O register b) I/O instruction c) I/O data d) I/O bus

208. A____________ is issued to test various status conditions in the interface and the peripheral.

a) Sustained Command b) system Command c) Status command d) none 209. ______________ refers to consistent reporting when information is lost because of failure.

a) Software integrity b) Data integrity c) system integrity d) none of these

210. _____________ is an innovation that improves both availability and performance of storage systems

a) Disk array b) Data array c) system array d) none of these

211. RAID is the acronym for _____________.

a) Redundant array of inexpensive disks b) Reduces array of inexpensive disksc) Redundant array of inexpensive data d) Redundant array of index data

212. ______________ uses twice as many disks.

a) Mirroring or shadowing b) Mirroring or monitoring b) Shadowing or monitoring d) none of these213. _________ is also known as bandwidth.

a) Throughout b) Thoroughpin c) Throughput d) none of these

214. __________________ is sometimes called latency.a) Request time b) Response Time c) Redundant Time d ) none of these

215. Multithreading is the capability of a processor to do multiple things at one time. (T,F)216. A thread has the following features

a) A state of thread executionb) The saved thread context when not runningc) A stack tracing the execution pathd) Some space for local variablese) All the above

217. Traditional operatin systems such as DOS and UNIX support the concept of singleThreading. (T,F)218. A Java Virtual Machine (JVM) is also an example of multithreading system. (T,F)219. The multithreading system has a concept of priorities and therefore, isalso called ___________ or ___________.220. It takes much more time to create a new thread in an existing processthan to create a brand-new process (True/False).221. The number of switches is proportional to the number of remote reads(True/ False).222. ________ typically refers to a thread of a few to tens of instructions.223. _________parallelism is the 'conventional' parallelism while _________ parallelism isthe means by which threads can correspond with other threads existing in other processors.224. The number of instructions in a thread is known as ________225. ________usually is a thread of a few to tens of instructions. It is basically forinstructionlevel multithreading.

a) Fine-grain threading b) Medium-grain threading c) Coarse-grain threading226. ________ is considered as a looplevel or function-level threading, and itconsists of hundreds of instructions.

a) Fine-grain threading b) Medium-grain threading c) Coarse-grain threading227. ________is treated as a task-level threading, where each thread consistsof thousands of instructions

Fine-grain threading b) Medium-grain threading c) Coarse-grain threading228. A computer architecture that is designed to execute more than oneProcessor is called a ________.

a) scalable architecture b) Scaling up c) Scaling out229. _________is achieved by adding extra resources to a single machine to allow anApplication to service more requests. The most common ways to do this areby adding memory (RAM) or to use a faster CPU.

a) scalable architecture b) Scaling up c) Scaling out230. _________is achieved by adding servers to a server group to make applications scale byscattering the processing among multiple computers.

a) scalable architecture b) Scaling up c) Scaling out231. Almost all business applications are __________________.232. When an application is run, each of the processes contains at least one _________ .233. There are basically three types of computational models as follows

a) Von Neumann model b) Dataflow model c) Hybrid multithreaded model d) all234. The combination of languages and the computer architecture in acommon foundation or paradigm is called ____________.235. Computational model uses mathematical language to describe a

system (True/ False)236. Clock rates of today's processors are in the range of 2 to 3.4 GHz and theyallow up to 600 million basic operations (T,F)238. The instruction set together with the resources needed for theirexecution is called the ________.239. The memory is a collection of storage cells, each of which can be inone of two different states (True/False).240. There are four possible ways of executing instructions (T,F)241. In this mechanism, an instruction is executed when the previous one in a definedSequence has been executed. This is the traditional way.

a) Control-flow Method b) Demand-driven Method c) Pattern-driven Method d) Dataflow Method242. In this mechanism, an instruction is executed when the results of the instruction areRequired by other instruction

a) Control-flow Method b) Demand-driven Method c) Pattern-driven Method d) Dataflow Method243. In this mechanism, an instruction is executed when particular data patterns appear.

a) Control-flow Method b) Demand-driven Method c) Pattern-driven Method d) Dataflow Method244. In dataflow method, an instruction is executed when the operands required becomeAvailable

a) Control-flow Method b) Demand-driven Method c) Pattern-driven Method d) Dataflow Method245. The heart of the Von Neumann computer architecture is the Central Processing Unit(CPU), consisting of the control unit and the ALU (Arithmetic and Logic Unit). (T,F)246. Dataflow architecture does not have a program counter and the execution of instructionsis solely determined based on the availability of input arguments to the instructions (T,F)247. ___________ combined dataflow ideas with sequential thread execution to define a hybrid computation model248. P-RISC explores the possibility of constructing a multithreaded architecture around a CISC processor (True/ False).

Answers

1 A 2 C 3 D 4 C5 D 6 B 7 A 8 A9 B 10 A 11 A 12 A13 B 14 A 15 A 16 B17 B 18 B 19 A 20 D21 B 22 C 23 A 24 B25 C 26 A 27 B 28 C29 T 30 B 31 B 32 A33 B 34 A 35 F 36 C37 A 38 B 39 C 40 D41 D 42 B 43 D 44 C45 C 46 A 47 C 48 A49 B 50 F 51 T 52 D53 D 54 C 55 C 56 B57 A 58 A 59 C 60 B61 A 62 C 63 C 64 T65 B 66 C 67 A 68 A69 B 70 C 71 D 72 A73 B 74 A 75 B 76 B77 C 78 D 79 T 80 C81 A 82 C 83 A 84 C85 C 86 B 87 A 88 A89 A 90 C 91 A 92 B93 A 94 D 95 A 96 B97 T 98 C 99 C 100 B

101 B 102 F 103 B 104 T105 A 106 C 107 C 108 B109 A 110 B 111 C 112 A113 C 114 B 115 D 116 A117 B 118 C 119 A 120 A121 C 122 A 123 B 124 A125 B 126 B 127 B 128 B129 C 130 C 131 B 132 A133 B 134 D 135 A 136 B137 C 138 A 139 B 140 A141 A 142 A 143 A 144 A145 B 146 D 147 B 148 B149 A 150 A 151 B 152 C153 B 154 B 155 A 156 C157 D 158 B 159 A 160 A161 B 162 D 163 A 164 A165 C 166 B 167 B 168 C169 C 170 C 171 B 172 B173 E 174 D 175 A 176 C177 B 178 A 179 C 180 B181 A 182 A 183 C 184 B185 A 186 C 187 A 188 B189 C 190 A 191 A 192 B193 D 194 B 195 A 196 A197 C 198 B 199 D 200 C201 C 202 C 203 C 204 D205 C 206 D 207 D 208 C209 B 210 A 211 A 212 A213 C 214 B 215 216 T217 E 218 T 219 T 220 Background processing,

pre-emptive multitasking221 F 222 T 223 FINE GRAIN

THREADING224 COMPUTATION AND

COMMUNICATION225 THREAD

GRANAULITY226 A 227 B 228 C

229 A 230 B 231 C 232 Scalable233 Thread 234 D 235 Computational

Model236 T

237 T 238 (ISA) 239 T 240 T241 A 242 B 243 C 244 D245 T 246 T 247 Iannucci 248 F

MCA2050

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