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Analog Multiplexers/DemultiplexersHigh−Performance Silicon−Gate CMOS
MC74HC4051A,MC74HC4052A,MC74HC4053A
The MC74HC4051A, MC74HC4052A and MC74HC4053A utilizesilicon−gate CMOS technology to achieve fast propagation delays,low ON resistances, and low OFF leakage currents. These analogmultiplexers/demultiplexers control analog voltages that may varyacross the complete power supply range (from VCC to VEE).
The HC4051A, HC4052A and HC4053A are identical in pinout tothe metal−gate MC14051AB, MC14052AB and MC14053AB. TheChannel−Select inputs determine which one of the AnalogInputs/Outputs is to be connected, by means of an analog switch, to theCommon Output/Input. When the Enable pin is HIGH, all analogswitches are turned off.
The Channel−Select and Enable inputs are compatible with standardCMOS outputs; with pullup resistors they are compatible with LSTTLoutputs.
These devices have been designed so that the ON resistance (Ron) ismore linear over input voltage than Ron of metal−gate CMOS analogswitches.
For a multiplexer/demultiplexer with injection current protection,see HC4851A and HC4852A.
Features• Fast Switching and Propagation Speeds
• Low Crosstalk Between Switches
• Diode Protection on All Inputs/Outputs
• Analog Power Supply Range (VCC − VEE) = 2.0 to 12.0 V
• Digital (Control) Power Supply Range (VCC − GND) = 2.0 to 6.0 V
• Improved Linearity and Lower ON Resistance Than Metal−GateCounterparts
• Low Noise
• In Compliance with the Requirements of JEDEC Standard No. 7A
• Chip Complexity: HC4051A − 184 FETs or 46 Equivalent GatesHC4052A − 168 FETs or 42 Equivalent GatesHC4053A − 156 FETs or 39 Equivalent Gates
• NLV Prefix for Automotive and Other Applications RequiringUnique Site and Control Change Requirements; AEC−Q100Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR−Free and are RoHSCompliant
This document contains information on some products that are still under development.ON Semiconductor reserves the right to change or discontinue these products withoutnotice.
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MARKING DIAGRAMS
SOIC−16
TSSOP−16
1
16
HC405xAGAWLYWW
HC405xA
ALYW�
�
1
16
SOIC−16 WIDE1
16
HC405xAAWLYWWG
See detailed ordering and shipping information on page 13 ofthis data sheet.
ORDERING INFORMATION
x = 1, 2 or 3A = Assembly LocationWL, L = Wafer LotYY, Y = YearWW, W = Work WeekG or � = Pb−Free Package
Triple Single−Pole, Double−Position Plus Common Off
X012
X113
A11
B10
C9
ENABLE6
X SWITCH
Y SWITCH
X14
ANALOGINPUTS/OUTPUTS
CHANNEL‐SELECTINPUTS
PIN 16 = VCCPIN 7 = VEEPIN 8 = GND
COMMONOUTPUTS/INPUTS
LLLLHHHHX
LLHHLLHHX
LHLHLHLHX
FUNCTION TABLE − MC74HC4053A
Control Inputs
ON ChannelsEnableSelect
C B A
LLLLLLLLH
X = Don’t Care
Pinout: MC74HC4053A (Top View)
1516 14 13 12 11 10
21 3 4 5 6 7
VCC
9
8
Y X X1 X0 A B C
Y1 Y0 Z1 Z Z0 Enable VEE GND
Z0Z0Z0Z0Z1Z1Z1Z1
Y0Y0Y1Y1Y0Y0Y1Y1
X0X1X0X1X0X1X0X1
NONE
Y02
Y11 Y
15
Z05
Z13 Z
4Z SWITCH
NOTE: This device allows independent control of each switch.Channel−Select Input A controls the X−Switch, Input B controlsthe Y−Switch and Input C controls the Z−Switch
MAXIMUM RATINGS
Symbol Parameter Value Unit
VCC Positive DC Supply Voltage (Referenced to GND)(Referenced to VEE)
–0.5 to +7.0–0.5 to +14.0
V
VEE Negative DC Supply Voltage (Referenced to GND) –7.0 to +5.0 V
VIS Analog Input Voltage VEE − 0.5 toVCC + 0.5
V
Vin Digital Input Voltage (Referenced to GND) –0.5 to VCC + 0.5 V
I DC Current, Into or Out of Any Pin ±25 mA
PD Power Dissipation in Still Air, SOIC Package†TSSOP Package†
500450
mW
Tstg Storage Temperature Range –65 to +150 �C
TL Lead Temperature, 1 mm from Case for 10 SecondsSOIC or TSSOP Package 260
�C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any ofthese limits are exceeded, device functionality should not be assumed, damage may occur andreliability may be affected.†Derating: SOIC Package: –7 mW/�C from 65� to 125�C
TSSOP Package: −6.1 mW/�C from 65� to 125�C
This device contains protectioncircuitry to guard against damagedue to high static voltages or electricfields. However, precautions mustbe taken to avoid applications of anyvoltage higher than maximum ratedvoltages to this high−impedance cir-cuit. For proper operation, Vin andVout should be constrained to therange GND � (Vin or Vout) � VCC.
Unused inputs must always betied to an appropriate logic voltagelevel (e.g., either GND or VCC).Unused outputs must be left open.
VCC Positive DC Supply Voltage (Referenced to GND)(Referenced to VEE)
2.02.0
6.012.0
V
VEE Negative DC Supply Voltage, Output (Referenced to GND) −6.0 GND V
VIS Analog Input Voltage VEE VCC V
Vin Digital Input Voltage (Referenced to GND) GND VCC V
VIO* Static or Dynamic Voltage Across Switch 1.2 V
TA Operating Temperature Range, All Package Types –55 +125 �C
tr, tf Input Rise/Fall Time VCC = 2.0 V(Channel Select or Enable Inputs) VCC = 3.0 V
VCC = 4.5 VVCC = 6.0 V
0000
1000600500400
ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyondthe Recommended Operating Ranges limits may affect device reliability.*For voltage drops across switch greater than 1.2 V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may
contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
DC CHARACTERISTICS — Digital Section (Voltages Referenced to GND) VEE = GND, Except Where Noted
Symbol Parameter ConditionVCC
V
Guaranteed Limit
Unit−55 to 25°C ≤85°C ≤125°C
VIH Minimum High−Level Input Voltage,Channel−Select or Enable Inputs
Ron = Per Spec 2.03.04.56.0
1.502.103.154.20
1.502.103.154.20
1.502.103.154.20
V
VIL Maximum Low−Level Input Voltage,Channel−Select or Enable Inputs
Ron = Per Spec 2.03.04.56.0
0.50.91.351.8
0.50.91.351.8
0.50.91.351.8
V
Iin Maximum Input Leakage Current,Channel−Select or Enable Inputs
Vin = VCC or GND,VEE = − 6.0 V
6.0 ± 0.1 ± 1.0 ± 1.0 �A
ICC Maximum Quiescent SupplyCurrent (per Package)
Channel Select, Enable andVIS = VCC or GND; VEE = GNDVIO = 0 V VEE = − 6.0
Figure 12. Crosstalk Between Any TwoSwitches, Test Set−Up
Figure 13. Power Dissipation Capacitance, Test Set−Up
Figure 14a. Total Harmonic Distortion, Test Set−Up Figure 14b. Plot, Harmonic Distortion
0
-�10
-�20
-�30
-�40
-�50
- 1001.0 2.0 3.125
FREQUENCY (kHz)
dB
-�60
-�70
-�80
-�90
FUNDAMENTAL FREQUENCY
DEVICE
SOURCE
ON
678
16
VEE CL*
*Includes all probe and jig capacitance
OFF
RL
RL
VIS
RL CL*
VOSfin
0.1�F
ON/OFF
678
16
VCC
CHANNEL SELECT
NCCOMMON O/I
OFF/ONANALOG I/O
VCC
A
11
VCC
VEE
ON
678
16
VCC
VEE
0.1�F
CL*
finRL
TODISTORTION
METER
*Includes all probe and jig capacitance
VOS
VIS
APPLICATIONS INFORMATION
The Channel Select and Enable control pins should be atVCC or GND logic levels. VCC being recognized as a logichigh and GND being recognized as a logic low. In thisexample:
VCC = +5V = logic highGND = 0V = logic low
The maximum analog voltage swings are determined bythe supply voltages VCC and VEE. The positive peak analogvoltage should not exceed VCC. Similarly, the negative peakanalog voltage should not go below VEE. In this example,the difference between VCC and VEE is ten volts. Therefore,using the configuration of Figure 15, a maximum analogsignal of ten volts peak−to−peak can be controlled. Unusedanalog inputs/outputs may be left floating (i.e., notconnected). However, tying unused analog inputs and
outputs to VCC or GND through a low value resistor helpsminimize crosstalk and feed−through noise that may bepicked up by an unused switch.
Although used here, balanced supplies are not arequirement. The only constraints on the power supplies arethat:
VCC − GND = 2 to 6 voltsVEE − GND = 0 to −6 voltsVCC − VEE = 2 to 12 volts
and VEE ≤ GND
When voltage transients above VCC and/or below VEE areanticipated on the analog channels, external Germanium orSchottky diodes (Dx) are recommended as shown in Figure16. These diodes should be able to absorb the maximumanticipated current surges during clipping.
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel PackagingSpecifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAPCapable.
ASME Y14.5M, 1994.2. CONTROLLING DIMENSION: MILLIMETERS.3. DIMENSIONS b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN0.15 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSEDPAD AS WELL AS THE TERMINALS.
0.20 REF
b
D2
L
PIN ONE
E2
1
8
15
10
D
E
BA
C0.15
C0.15
2X
2X
e
2
16X
16X
0.10 C
0.05 C
A B
NOTE 3
A
16X
K
A1
(A3)
SEATINGPLANE
C0.08
C0.10
0.80 1.00
L 0.35 0.45
1.85 2.15
SCALE 2:1
GENERIC MARKINGDIAGRAM*
XXXX = Specific Device CodeA = Assembly LocationL = Wafer LotY = YearW = Work Week� = Pb−Free Package
XXXXALYW�
�
1
*This information is generic. Please refer todevice data sheet for actual part marking.Pb−Free indicator, “G” or microdot “ �”,may or may not be present.
L1
DETAIL A
L
ALTERNATE TERMINALCONSTRUCTIONS
L
ÇÇÇÇÇÇÉÉÉÉÉÉDETAIL B
MOLD CMPDEXPOSED Cu
ALTERNATECONSTRUCTIONSDETAIL B
*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
2.80
3.80
1.10
0.50
0.6016X
0.3016X
DIMENSIONS: MILLIMETERS
1
REFERENCE
TOP VIEW
SIDE VIEW
NOTE 4
C
0.15 C A B
0.15 C A BDETAIL A
BOTTOM VIEW
e/2
L1 --- 0.15
(Note: Microdot may be in either location)
2.10
PITCH
PACKAGEOUTLINE
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.
98AON36347EDOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
2. COMMON DRAIN (OUTPUT)3. COMMON DRAIN (OUTPUT)4. GATE P‐CH5. COMMON DRAIN (OUTPUT)6. COMMON DRAIN (OUTPUT)7. COMMON DRAIN (OUTPUT)8. SOURCE P‐CH9. SOURCE P‐CH
10. COMMON DRAIN (OUTPUT)11. COMMON DRAIN (OUTPUT)12. COMMON DRAIN (OUTPUT)13. GATE N‐CH14. COMMON DRAIN (OUTPUT)15. COMMON DRAIN (OUTPUT)16. SOURCE N‐CH
16
8 9
8X
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.
98ASB42566BDOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
XXXXX = Specific Device CodeA = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekG = Pb−Free Package
GENERICMARKING DIAGRAM*
16
1
XXXXXXXXXXXXXXXXXXXXXX
AWLYYWWG
1
*This information is generic. Please refer todevice data sheet for actual part marking.Pb−Free indicator, “G” or microdot “ �”,may or may not be present.
11.00
16X 0.58
16X1.62 1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.
98ASB42567BDOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
ANSI Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.MOLD FLASH OR GATE BURRS SHALL NOTEXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDEINTERLEAD FLASH OR PROTRUSION.INTERLEAD FLASH OR PROTRUSION SHALLNOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.08 (0.003) TOTALIN EXCESS OF THE K DIMENSION ATMAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FORREFERENCE ONLY.
7. DIMENSION A AND B ARE TO BEDETERMINED AT DATUM PLANE −W−.
� � � �
SECTION N−N
SEATINGPLANE
IDENT.PIN 1
1 8
16 9
DETAIL E
J
J1
B
C
D
A
K
K1
HG
ÉÉÉÉÉÉ
DETAIL E
F
M
L
2X L/2
−U−
SU0.15 (0.006) T
SU0.15 (0.006) T
SUM0.10 (0.004) V ST
0.10 (0.004)−T−
−V−
−W−
0.25 (0.010)
16X REFK
N
N
1
16
GENERICMARKING DIAGRAM*
XXXXXXXXALYW
1
16
*This information is generic. Please refer todevice data sheet for actual part marking.Pb−Free indicator, “G” or microdot “ �”,may or may not be present.
XXXX = Specific Device CodeA = Assembly LocationL = Wafer LotY = YearW = Work WeekG or � = Pb−Free Package
7.06
16X0.36
16X
1.26
0.65
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.
98ASH70247ADOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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