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Quality bipolar fabrication with innovative design concepts areemployed for the MC33071/72/74, MC34071/72/74, NCV33072/74Aseries of monolithic operational amplifiers. This series of operationalamplifiers offer 4.5 MHz of gain bandwidth product, 13 V/�s slew rateand fast settling time without the use of JFET device technology.Although this series can be operated from split supplies, it isparticularly suited for single supply operation, since the commonmode input voltage range includes ground potential (VEE). With aDarlington input stage, this series exhibits high input resistance, lowinput offset voltage and high gain. The all NPN output stage,characterized by no deadband crossover distortion and large outputvoltage swing, provides high capacitance drive capability, excellentphase and gain margins, low open loop high frequency outputimpedance and symmetrical source/sink AC frequency response.
The MC33071/72/74, MC34071/72/74, NCV33072/74,A series ofdevices are available in standard or prime performance (A Suffix)grades and are specified over the commercial, industrial/vehicular ormilitary temperature ranges. The complete series of single, dual andquad operational amplifiers are available in plastic DIP, SOIC, QFNand TSSOP surface mount packages.
Features• Wide Bandwidth: 4.5 MHz
• High Slew Rate: 13 V/�s
• Fast Settling Time: 1.1 �s to 0.1%
• Wide Single Supply Operation: 3.0 V to 44 V
• Wide Input Common Mode Voltage Range: Includes Ground (VEE)
• Low Input Offset Voltage: 3.0 mV Maximum (A Suffix)
• Large Output Voltage Swing: −14.7 V to +14 V (with ±15 VSupplies)
• Large Capacitance Drive Capability: 0 pF to 10,000 pF
• Low Total Harmonic Distortion: 0.02%
• Excellent Phase Margin: 60°• Excellent Gain Margin: 12 dB
• Output Short Circuit Protection
• ESD Diodes/Clamps Provide Input Protection for Dual and Quad
• NCV Prefix for Automotive and Other Applications RequiringUnique Site and Control Change Requirements; AEC−Q100Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHSCompliant
See detailed ordering and shipping information on page 18 ofthis data sheet.
ORDERING INFORMATION
PDIP−8P SUFFIXCASE 626
18
SOIC−8D SUFFIXCASE 7511
8
PDIP−14P SUFFIXCASE 646
1
14
SOIC−14D SUFFIX
CASE 751A1
14
TSSOP−14DTB SUFFIXCASE 948G
114
See general marking information in the device markingsection on page 21 of this data sheet.
Output Short Circuit Duration (Note 2) tSC Indefinite Sec
Operating Junction Temperature TJ +150 °CStorage Temperature Range Tstg −60 to +150 °CESD Capability, Dual and Quad (Note 3)
Human Body ModelMachine Model
ESDHBMESDMM
2000200
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionalityshould not be assumed, damage may occur and reliability may be affected.1. Either or both input voltages should not exceed the magnitude of VCC or VEE.2. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded (see Figure 2).3. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (JEDEC standard: JESD22−A114)ESD Machine Model tested per AEC−Q100−003 (JEDEC standard: JESD22−A115)
ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, RL = connected to ground, unless otherwise noted. See Note 4 forTA = Tlow to Thigh)
A Suffix Non−Suffix
Characteristics Symbol Min Typ Max Min Typ Max Unit
Input Offset Voltage (RS = 100 �, VCM = 0 V, VO = 0 V)VCC = +15 V, VEE = −15 V, TA = +25°CVCC = +5.0 V, VEE = 0 V, TA = +25°CVCC = +15 V, VEE = −15 V, TA = Tlow to Thigh
VIO
−−
− 0.50.5−
3.03.05.0
−−
−1.01.5−
5.05.07.0
mV
Average Temperature Coefficient of Input OffsetVoltageRS = 10 �, VCM = 0 V, VO = 0 V, TA = Tlow to Thigh
�VIO/�T − 10 − − 10 − �V/°C
Input Bias Current (VCM = 0 V, VO = 0 V)TA = +25°CTA = Tlow to Thigh
IIB−−
100−
500700
−−
100−
500700
nA
Input Offset Current (VCM = 0 V, VO = 0V)TA = +25°CTA = Tlow to Thigh
IIO−−
6.0−
50300
−−
6.0−
75300
nA
Input Common Mode Voltage RangeTA = +25°CTA = Tlow to Thigh
VICRVEE to (VCC −1.8)VEE to (VCC −2.2)
VEE to (VCC −1.8)VEE to (VCC −2.2)
V
Large Signal Voltage Gain (VO = ±10 V, RL = 2.0 k�)TA = +25°CTA = Tlow to Thigh
AVOL5025
100−
−−
2520
100−
−−
V/mV
Output Voltage Swing (VID = ±1.0 V)VCC = +5.0 V, VEE = 0 V, RL = 2.0 k�, TA = +25°CVCC = +15 V, VEE = −15 V, RL = 10 k�, TA = +25°CVCC = +15 V, VEE = −15 V, RL = 2.0 k�,
TA = Tlow to Thigh
VOH3.713.613.4
4.014−
−−−
3.713.613.4
4.014−
−−−
V
VCC = +5.0 V, VEE = 0 V, RL = 2.0 k�, TA = +25°CVCC = +15 V, VEE = −15 V, RL = 10 k�, TA = +25°CVCC = +15 V, VEE = −15 V, RL = 2.0 k�,
TA = Tlow to Thigh
VOL −−−
0.1−14.7−
0.3−14.3−13.5
−−−
0.1−14.7−
0.3−14.3−13.5
V
Output Short Circuit Current (VID = 1.0 V, VO = 0 V,TA = 25°C)
SourceSink
ISC
1020
3030
−−
1020
3030
−−
mA
Common Mode RejectionRS ≤ 10 k�, VCM = VICR, TA = 25°C
CMR 80 97 − 70 97 − dB
Power Supply Rejection (RS = 100 �)VCC/VEE = +16.5 V/−16.5 V to +13.5 V/−13.5 V,
TA = 25°C
PSR 80 97 − 70 97 − dB
Power Supply Current (Per Amplifier, No Load)VCC = +5.0 V, VEE = 0 V, VO = +2.5 V, TA = +25°CVCC = +15 V, VEE = −15 V, VO = 0 V, TA = +25°CVCC = +15 V, VEE = −15 V, VO = 0 V,
TA = Tlow to Thigh
ID−−−
1.61.9−
2.02.52.8
−−−
1.61.9−
2.02.52.8
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Productperformance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Tlow = −40°C for MC33071,2,4,/A, NCV33074/A Thigh = +85°C for MC33071,2,4,/A, NCV33074/A= 0°C for MC34071,2,4,/A = +70°C for MC34071,2,4,/A= −40°C for MC34072,4/V, NCV33072,4A = +125°C for MC34072,4/V, NCV33072,4A, NCV34074VCase 510AJ Tlow/Thigh guaranteed by product characterization.
Figure 35. Power Supply Rejectionversus Temperature
Figure 36. Channel Separation versus Frequency Figure 37. Input Noise versus Frequency
VCC, |VEE|, SUPPLY VOLTAGE (V)
CC
I�� ,
SU
PPLY
CU
RR
ENT
(mA)
0 5.0 10 15 20 25
TA = 25°C
TA = 125°C
TA = -55°C
TA, AMBIENT TEMPERATURE (°C)
PSR
, PO
WER
SU
PPLY
REJ
ECTI
ON
(dB)
-55 -25 0 25 50 75 100 125
VCC = +15 VVEE = -15 V
(�VCC = +1.5 V)
(�VEE = +1.5 V)
+PSR
-PSR
f, FREQUENCY (kHz)
CH
ANN
EL S
EPAR
ATIO
N (d
B)
10 20 30 50 70 100 200 300
VCC = +15 VVEE = -15 VTA = 25°C
f, FREQUENCY (kHz)
ne���,
INPU
T N
OIC
E VO
LTAG
E (
i�, I
NPU
T N
OIS
E C
UR
REN
T (p
A
)
10 100 1.0 k 10 k 100 k
nVH
z�)
√ Hz
√n
Voltage
Current
9.0
8.0
7.0
6.0
5.0
4.0
105
95
85
75
65
120
100
80
60
40
20
0
70
60
50
40
30
20
10
0
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0
�VOADM+
-�VCC
�VEE
�VO/ADM
�VCC+PSR = 20 Log
�VO/ADM
�VEE-PSR = 20 Log
VCC = +15 VVEE = -15 VVCM = 0TA = 25°C
Quad device
APPLICATIONS INFORMATIONCIRCUIT DESCRIPTION/PERFORMANCE FEATURES
Although the bandwidth, slew rate, and settling time of theMC34071 amplifier series are similar to op amp productsutilizing JFET input devices, these amplifiers offer otheradditional distinct advantages as a result of the PNPtransistor differential input stage and an all NPN transistoroutput stage.
Since the input common mode voltage range of this inputstage includes the VEE potential, single supply operation isfeasible to as low as 3.0 V with the common mode inputvoltage at ground potential.
The input stage also allows differential input voltages upto ±44 V, provided the maximum input voltage range is notexceeded. Specifically, the input voltages must rangebetween VEE and VCC supply voltages as shown by themaximum rating table. In practice, although notrecommended, the input voltages can exceed the VCCvoltage by approximately 3.0 V and decrease below the VEEvoltage by 0.3 V without causing product damage, althoughoutput phase reversal may occur. It is also possible to source
up to approximately 5.0 mA of current from VEE througheither inputs clamping diode without damage or latching,although phase reversal may again occur.
If one or both inputs exceed the upper common modevoltage limit, the amplifier output is readily predictable andmay be in a low or high state depending on the existing inputbias conditions.
Since the input capacitance associated with the smallgeometry input device is substantially lower (2.5 pF) thanthe typical JFET input gate capacitance (5.0 pF), betterfrequency response for a given input source resistance canbe achieved using the MC34071 series of amplifiers. Thisperformance feature becomes evident, for example, in fastsettling D−to−A current to voltage conversion applicationswhere the feedback resistance can form an input pole withthe input capacitance of the op amp. This input pole createsa 2nd order system with the single pole op amp and istherefore detrimental to its settling time. In this context,lower input capacitance is desirable especially for higher
values of feedback resistances (lower current DACs). Thisinput pole can be compensated for by creating a feedbackzero with a capacitance across the feedback resistance, ifnecessary, to reduce overshoot. For 2.0 k� of feedbackresistance, the MC34071 series can settle to within 1/2 LSBof 8−bits in 1.0 �s, and within 1/2 LSB of 12−bits in 2.2 �sfor a 10 V step. In a inverting unity gain fast settlingconfiguration, the symmetrical slew rate is ±13 V/�s. In theclassic noninverting unity gain configuration, the outputpositive slew rate is +10 V/�s, and the correspondingnegative slew rate will exceed the positive slew rate as afunction of the fall time of the input waveform.
Since the bipolar input device matching characteristicsare superior to that of JFETs, a low untrimmed maximumoffset voltage of 3.0 mV prime and 5.0 mV downgrade canbe economically offered with high frequency performancecharacteristics. This combination is ideal for low costprecision, high speed quad op amp applications.
The all NPN output stage, shown in its basic form on theequivalent circuit schematic, offers unique advantages overthe more conventional NPN/PNP transistor Class AB outputstage. A 10 k� load resistance can swing within 1.0 V of thepositive rail (VCC), and within 0.3 V of the negative rail(VEE), providing a 28.7 Vpp swing from ±15 V supplies.This large output swing becomes most noticeable at lowersupply voltages.
The positive swing is limited by the saturation voltage ofthe current source transistor Q7, and VBE of the NPN pull uptransistor Q17, and the voltage drop associated with the shortcircuit resistance, R7. The negative swing is limited by thesaturation voltage of the pull−down transistor Q16, thevoltage drop ILR6, and the voltage drop associated withresistance R7, where IL is the sink load current. For smallvalued sink currents, the above voltage drops are negligible,allowing the negative swing voltage to approach withinmillivolts of VEE. For large valued sink currents (>5.0 mA),diode D3 clamps the voltage across R6, thus limiting thenegative swing to the saturation voltage of Q16, plus theforward diode drop of D3 (≈VEE +1.0 V). Thus for a givensupply voltage, unprecedented peak−to−peak output voltageswing is possible as indicated by the output swingspecifications.
If the load resistance is referenced to VCC instead ofground for single supply applications, the maximumpossible output swing can be achieved for a given supplyvoltage. For light load currents, the load resistance will pullthe output to VCC during the positive swing and the outputwill pull the load resistance near ground during the negativeswing. The load resistance value should be much less thanthat of the feedback resistance to maximize pull upcapability.
Because the PNP output emitter−follower transistor hasbeen eliminated, the MC34071 series offers a 20 mAminimum current sink capability, typically to an outputvoltage of (VEE +1.8 V). In single supply applications theoutput can directly source or sink base current from acommon emitter NPN transistor for fast high currentswitching applications.
In addition, the all NPN transistor output stage isinherently fast, contributing to the bipolar amplifier’s highgain bandwidth product and fast settling capability. Theassociated high frequency low output impedance (30 � typ@ 1.0 MHz) allows capacitive drive capability from 0 pF to10,000 pF without oscillation in the unity closed loop gainconfiguration. The 60° phase margin and 12 dB gain marginas well as the general gain and phase characteristics arevirtually independent of the source/sink output swingconditions. This allows easier system phase compensation,since output swing will not be a phase consideration. Thehigh frequency characteristics of the MC34071 series alsoallow excellent high frequency active filter capability,especially for low voltage single supply applications.
Although the single supply specifications is defined at5.0 V, these amplifiers are functional to 3.0 V @ 25°Calthough slight changes in parametrics such as bandwidth,slew rate, and DC gain may occur.
If power to this integrated circuit is applied in reversepolarity or if the IC is installed backwards in a socket, largeunlimited current surges will occur through the device thatmay result in device destruction.
Special static precautions are not necessary for thesebipolar amplifiers since there are no MOS transistors on thedie.
As with most high frequency amplifiers, proper leaddress, component placement, and PC board layout should beexercised for optimum frequency performance. Forexample, long unshielded input or output leads may result inunwanted input−output coupling. In order to preserve therelatively low input capacitance associated with theseamplifiers, resistors connected to the inputs should beimmediately adjacent to the input pin to minimize additionalstray input capacitance. This not only minimizes the inputpole for optimum frequency response, but also minimizesextraneous “pick up” at this node. Supply decoupling withadequate capacitance immediately adjacent to the supply pinis also important, particularly over temperature, since manytypes of decoupling capacitors exhibit great impedancechanges over temperature.
The output of any one amplifier is current limited and thusprotected from a direct short to ground. However, undersuch conditions, it is important not to allow the device toexceed the maximum junction temperature rating. Typicallyfor ±15 V supplies, any one output can be shortedcontinuously to ground without exceeding the maximumtemperature rating.
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel PackagingSpecifications Brochure, BRD8011/D.
*NCV prefix for automotive and other applications requiring unique site and control change requirements; AEC−Q100 qualified and PPAPcapable.
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel PackagingSpecifications Brochure, BRD8011/D.
*NCV prefix for automotive and other applications requiring unique site and control change requirements; AEC−Q100 qualified and PPAPcapable.
*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
2.90
2.90
0.73
0.50
0.3010X
DIMENSIONS: MILLIMETERS
TOP VIEW
SIDE VIEW
BOTTOM VIEW
B
L1
DETAIL A
L
ALTERNATE TERMINALCONSTRUCTIONS
L
ÉÉÉÉÉÉDETAIL B
MOLD CMPDEXPOSED Cu
ALTERNATECONSTRUCTIONS
A
DETAIL B
DETAIL A
1
0.00 0.15L1
XXXX = Specific Device CodeAA = Assembly LocationY = YearW = Work Week� = Pb−Free Package
*This information is generic. Please refer todevice data sheet for actual part marking.Pb−Free indicator, “G” or microdot “ �”,may or may not be present.
GENERICMARKING DIAGRAM*
XXXXAAYW
�
9
5
L2
PITCH
10X
NOTE 3
NOTE 4
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.
98AON38696EDOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
XXXX = Specific Device CodeA = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekG = Pb−Free Package
*This information is generic. Please refer todevice data sheet for actual part marking.Pb−Free indicator, “G” or microdot “ �”,may or may not be present.
A
TOP VIEW
C
SEATINGPLANE
0.010 C ASIDE VIEW
END VIEW
END VIEW
WITH LEADS CONSTRAINED
DIM MIN MAXINCHES
A −−−− 0.210A1 0.015 −−−−
b 0.014 0.022
C 0.008 0.014D 0.355 0.400D1 0.005 −−−−
e 0.100 BSC
E 0.300 0.325
M −−−− 10
−−− 5.330.38 −−−
0.35 0.56
0.20 0.369.02 10.160.13 −−−
2.54 BSC
7.62 8.26
−−− 10
MIN MAXMILLIMETERS
NOTES:1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.2. CONTROLLING DIMENSION: INCHES.3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK-
AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARENOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUMPLANE H WITH THE LEADS CONSTRAINED PERPENDICULARTO DATUM C.
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THELEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THELEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARECORNERS).
E1 0.240 0.280 6.10 7.11
b2
eB −−−− 0.430 −−− 10.92
0.060 TYP 1.52 TYP
E1
M
8X
c
D1
B
A2 0.115 0.195 2.92 4.95
L 0.115 0.150 2.92 3.81°°
H
NOTE 5
e
e/2A2
NOTE 3
M B M NOTE 6
M
STYLE 1:PIN 1. AC IN
2. DC + IN3. DC − IN4. AC IN5. GROUND6. OUTPUT7. AUXILIARY8. VCC
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.
98ASB42420BDOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
XXXXX = Specific Device CodeA = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekG = Pb−Free Package
XXXXXXXXXXXXXXXXXXXXXXXX
AWLYYWWG
1STYLES ON PAGE 2
1
14
*This information is generic. Please refer todevice data sheet for actual part marking.Pb−Free indicator, “G” or microdot “ �”,may or may not be present.
b2NOTE 8
D A
TOP VIEW
E1
B
b
L
A1
A
C
SEATINGPLANE
0.010 C ASIDE VIEW M
14X
D1e
A2
NOTE 3
M B M
eB
E
END VIEW
END VIEW
WITH LEADS CONSTRAINED
DIM MIN MAXINCHES
A −−−− 0.210A1 0.015 −−−−
b 0.014 0.022
C 0.008 0.014D 0.735 0.775D1 0.005 −−−−
e 0.100 BSC
E 0.300 0.325
M −−−− 10
−−− 5.330.38 −−−
0.35 0.56
0.20 0.3618.67 19.690.13 −−−
2.54 BSC
7.62 8.26
−−− 10
MIN MAXMILLIMETERS
NOTES:1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.2. CONTROLLING DIMENSION: INCHES.3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK-
AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARENOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUMPLANE H WITH THE LEADS CONSTRAINED PERPENDICULARTO DATUM C.
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THELEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THELEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARECORNERS).
E1 0.240 0.280 6.10 7.11
b2
eB −−−− 0.430 −−− 10.92
0.060 TYP 1.52 TYP
c
A2 0.115 0.195 2.92 4.95
L 0.115 0.150 2.92 3.81°°
H
NOTE 5
NOTE 6
M
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.
98ASB42428BDOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
2. DRAIN3. SOURCE4. NO CONNECTION5. SOURCE6. DRAIN7. GATE8. GATE9. DRAIN
10. SOURCE11. NO CONNECTION12. SOURCE13. DRAIN14. GATE
STYLE 9:PIN 1. COMMON CATHODE
2. ANODE/CATHODE3. ANODE/CATHODE4. NO CONNECTION5. ANODE/CATHODE6. ANODE/CATHODE7. COMMON ANODE8. COMMON ANODE9. ANODE/CATHODE
10. ANODE/CATHODE11. NO CONNECTION12. ANODE/CATHODE13. ANODE/CATHODE14. COMMON CATHODE
PDIP−14CASE 646−06
ISSUE SDATE 22 APR 2015
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.
98ASB42428BDOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
XXXXX = Specific Device CodeA = Assembly LocationL = Wafer LotY = YearW = Work Week� = Pb−Free Package
GENERICMARKING DIAGRAM*
1
8
XXXXXALYWX
1
8
IC Discrete
XXXXXXAYWW
�1
8
1.520.060
7.00.275
0.60.024
1.2700.050
4.00.155
� mminches
�SCALE 6:1
*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
Discrete
XXXXXXAYWW
1
8
(Pb−Free)
XXXXXALYWX
�1
8
IC(Pb−Free)
XXXXXX = Specific Device CodeA = Assembly LocationY = YearWW = Work Week� = Pb−Free Package
*This information is generic. Please refer todevice data sheet for actual part marking.Pb−Free indicator, “G” or microdot “�”, mayor may not be present. Some products maynot follow the Generic Marking.
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.
98ASB42564BDOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.
98ASB42564BDOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
XXXXX = Specific Device CodeA = Assembly LocationWL = Wafer LotY = YearWW = Work WeekG = Pb−Free Package
*This information is generic. Please refer todevice data sheet for actual part marking.Pb−Free indicator, “G” or microdot “ �”,may or may not be present.
STYLES ON PAGE 2
NOTES:1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.2. CONTROLLING DIMENSION: MILLIMETERS.3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSIONSHALL BE 0.13 TOTAL IN EXCESS OF ATMAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDEMOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PERSIDE.
H
14 8
71
M0.25 B M
C
hX 45
SEATINGPLANE
A1
A
M
�
SAM0.25 B SC
b13X
BA
E
D
e
DETAIL A
L
A3
DETAIL A
DIM MIN MAX MIN MAXINCHESMILLIMETERS
D 8.55 8.75 0.337 0.344E 3.80 4.00 0.150 0.157
A 1.35 1.75 0.054 0.068
b 0.35 0.49 0.014 0.019
L 0.40 1.25 0.016 0.049
e 1.27 BSC 0.050 BSC
A3 0.19 0.25 0.008 0.010A1 0.10 0.25 0.004 0.010
M 0 7 0 7
H 5.80 6.20 0.228 0.244h 0.25 0.50 0.010 0.019
� � � �
6.50
14X0.58
14X
1.18
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT*
*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.
0.10
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.
98ASB42565BDOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
2. ANODE/CATHODE3. ANODE/CATHODE4. NO CONNECTION5. ANODE/CATHODE6. NO CONNECTION7. ANODE/CATHODE8. ANODE/CATHODE9. ANODE/CATHODE
10. NO CONNECTION11. ANODE/CATHODE12. ANODE/CATHODE13. NO CONNECTION14. COMMON ANODE
STYLE 3:PIN 1. NO CONNECTION
2. ANODE3. ANODE4. NO CONNECTION5. ANODE6. NO CONNECTION7. ANODE8. ANODE9. ANODE
10. NO CONNECTION11. ANODE12. ANODE13. NO CONNECTION14. COMMON CATHODE
STYLE 4:PIN 1. NO CONNECTION
2. CATHODE3. CATHODE4. NO CONNECTION5. CATHODE6. NO CONNECTION7. CATHODE8. CATHODE9. CATHODE
10. NO CONNECTION11. CATHODE12. CATHODE13. NO CONNECTION14. COMMON ANODE
STYLE 8:PIN 1. COMMON CATHODE
2. ANODE/CATHODE3. ANODE/CATHODE4. NO CONNECTION5. ANODE/CATHODE6. ANODE/CATHODE7. COMMON ANODE8. COMMON ANODE9. ANODE/CATHODE
10. ANODE/CATHODE11. NO CONNECTION12. ANODE/CATHODE13. ANODE/CATHODE14. COMMON CATHODE
STYLE 2:CANCELLED
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.
98ASB42565BDOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
*This information is generic. Please refer todevice data sheet for actual part marking.Pb−Free indicator, “G” or microdot “ �”,may or may not be present.
ANSI Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.MOLD FLASH OR GATE BURRS SHALL NOTEXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDEINTERLEAD FLASH OR PROTRUSION.INTERLEAD FLASH OR PROTRUSION SHALLNOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.08 (0.003) TOTALIN EXCESS OF THE K DIMENSION ATMAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FORREFERENCE ONLY.
7. DIMENSION A AND B ARE TO BEDETERMINED AT DATUM PLANE −W−.
� � � �
SU0.15 (0.006) T
2X L/2
SUM0.10 (0.004) V ST
L−U−
SEATINGPLANE
0.10 (0.004)−T−
ÇÇÇÇÇÇSECTION N−N
DETAIL E
J J1
K
K1
ÉÉÉÉÉÉ
DETAIL E
F
M
−W−
0.25 (0.010)814
71
PIN 1IDENT.
HG
A
D
C
B
SU0.15 (0.006) T
−V−
14X REFK
N
N
GENERICMARKING DIAGRAM*
XXXXXXXXALYW�
�
1
14
A = Assembly LocationL = Wafer LotY = YearW = Work Week� = Pb−Free Package
7.06
14X0.36
14X
1.26
0.65
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
(Note: Microdot may be in either location)
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.
98ASH70246ADOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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