MC13111AFB MC13111AFTA MC13111BFB MC13111BFTA UNIVERSAL NARROWBAND FM RECEIVER INTEGRATED CIRCUIT FB SUFFIX PLASTIC PACKAGE CASE 848B (QFP–52) 52 Order this document by MC13110A/D 1 Device Tested Operating Temperature Range Package ORDERING INFORMATION MC13110AFB T A = – 40° to +85°C QFP–52 FTA SUFFIX PLASTIC PACKAGE CASE 932 (LQFP–48) 48 1 MC13110AFTA LQFP–48 MC13110BFB QFP–52 MC13110BFTA LQFP–48 QFP–52 LQFP–48 QFP–52 LQFP–48 1 MOTOROLA ANALOG IC DEVICE DATA The MC13110A/B and MC13111A/B integrates several of the functions required for a cordless telephone into a single integrated circuit. This significantly reduces component count, board space requirements, external adjustments, and lowers overall costs. It is designed for use in both the handset and the base. • MC13110A and MC13111A: Fully Programmable in all Power Modes • MC13110B and MC13111B: MPU Clk Out and Second Local Oscillator are “Always On”. There is No Inactive Mode • Dual Conversion FM Receiver – Complete Dual Conversion Receiver – Antenna Input to Audio Out 80 MHz Maximum Carrier Frequency – RSSI Output – Carrier Detect Output with Programmable Threshold – Comparator for Data Recovery – Operates with Either a Quad Coil or Ceramic Discriminator • Compander – Expander Includes Mute, Digital Volume Control, Speaker Driver, Programmable Low Pass Filter, and Gain Block – Compressor Includes Mute, Programmable Low Pass Filter, Limiter, and Gain Block • MC13110A/B only: Frequency Inversion Scrambler – Function Controlled via MPU Interface – Programmable Carrier Modulation Frequency • Dual Universal Programmable PLL – Supports New 25 Channel U.S. Standard with No External Switches – Universal Design for Domestic and Foreign Cordless Telephone Standards – Digitally Controlled Via a Serial Interface Port – Receive Side Includes 1st LO VCO, Phase Detector, and 14–Bit Programmable Counter and 2nd LO with 12–Bit Counter – Transmit Section Contains Phase Detector and 14–Bit Counter – MPU Clock Outputs Eliminates Need for MPU Crystal • Low Battery Detect – Provides Two Levels of Monitoring with Separate Outputs – Separate, Adjustable Trip Points • 2.7 to 5.5 V Operation (15 μA Current Consumption in Inactive Mode) • AN1575: Refer to this Application Note for a List of the “Worldwide Cordless Telephone Frequencies R x Phase Detector T x Phase Detector Low Battery Detect Simplified Block Diagram This device contains 8262 active transistors. Expander 1st Mixer Data Out R x In 2nd Mixer T x PD Out T x Out Limiting IF Amplifier Detector R x Out T x In Low Battery Indicator R x PD In R x PD Out 1st LO 2nd LO Carrier Detect Out SPI RSSI RSSI μP Serial Interface Compressor Scrambler Scrambler = MC13110A/B Only NOTE: MPU Clock Out 2nd LO This document contains information on a new product. Specifications and information herein are subject to change without notice. Motorola, Inc. 1997 Rev 0
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MC13111AFB
MC13111AFTA
MC13111BFB
MC13111BFTA
UNIVERSALNARROWBAND FM RECEIVER
INTEGRATED CIRCUIT
FB SUFFIXPLASTIC PACKAGE
CASE 848B(QFP–52)
52
Order this document by MC13110A/D
1
DeviceTested Operating
Temperature Range Package
ORDERING INFORMATION
MC13110AFB
TA = – 40° to +85°C
QFP–52
FTA SUFFIXPLASTIC PACKAGE
CASE 932(LQFP–48)
48 1
MC13110AFTA LQFP–48
MC13110BFB QFP–52
MC13110BFTA LQFP–48
QFP–52
LQFP–48
QFP–52
LQFP–48
1MOTOROLA ANALOG IC DEVICE DATA
The MC13110A/B and MC13111A/B integrates several of the functions
required for a cordless telephone into a single integrated circuit. Thissignificantly reduces component count, board space requirements, externaladjustments, and lowers overall costs. It is designed for use in both thehandset and the base.
• MC13110A and MC13111A: Fully Programmable in all Power Modes
• MC13110B and MC13111B: MPU Clk Out and Second Local Oscillatorare “Always On”. There is No Inactive Mode
• Dual Conversion FM Receiver
– Complete Dual Conversion Receiver – Antenna Input to Audio Out80 MHz Maximum Carrier Frequency
– RSSI Output– Carrier Detect Output with Programmable Threshold– Comparator for Data Recovery– Operates with Either a Quad Coil or Ceramic Discriminator
• Compander
– Expander Includes Mute, Digital Volume Control, Speaker Driver,Programmable Low Pass Filter, and Gain Block
– Compressor Includes Mute, Programmable Low Pass Filter, Limiter,and Gain Block
• MC13110A/B only: Frequency Inversion Scrambler
– Function Controlled via MPU Interface– Programmable Carrier Modulation Frequency
• Dual Universal Programmable PLL
– Supports New 25 Channel U.S. Standard with No External Switches– Universal Design for Domestic and Foreign Cordless Telephone
Standards– Digitally Controlled Via a Serial Interface Port– Receive Side Includes 1st LO VCO, Phase Detector, and 14–Bit
Programmable Counter and 2nd LO with 12–Bit Counter– Transmit Section Contains Phase Detector and 14–Bit Counter– MPU Clock Outputs Eliminates Need for MPU Crystal
• Low Battery Detect
– Provides Two Levels of Monitoring with Separate Outputs– Separate, Adjustable Trip Points
• 2.7 to 5.5 V Operation (15 µA Current Consumption in Inactive Mode)
• AN1575: Refer to this Application Note for a List of the “WorldwideCordless Telephone Frequencies
Rx PhaseDetector
Tx PhaseDetector
Low BatteryDetect
Simplified Block Diagram
This device contains 8262 active transistors.
Expander
1stMixer
Data Out
Rx In2ndMixer
Tx PD Out
Tx Out
Limiting IFAmplifier
Detector
Rx Out
Tx In
Low BatteryIndicator
Rx PD In
Rx PD Out
1st LO 2nd LOCarrier Detect Out
SPI
RSSIRSSI
µP SerialInterface
Compressor
Scrambler
Scrambler
= MC13110A/B Only
NOTE:
MPU Clock Out2nd LO
This document contains information on a new product. Specifications and information hereinare subject to change without notice.
Motorola, Inc. 1997 Rev 0
MC13110A/B MC13111A/B
2 MOTOROLA ANALOG IC DEVICE DATA
14
15
16
17
18
19
20
21
22
23
24
25
26
52
51
50
49
48
47
46
45
44
43
42
41
40
13121110987654321
27282930313233343536373839
BD1 Out
DA Out
BD2 Out
T
C Cap
C In
Amp Out
T
DA In
V
R
Det Out
RSSI
x Out
x In
CCAudio
x Audio In
LO
LO
V
Gnd Audio
SA Out
SA In
E Out
E
E In
Scr Out
Ref
Ref
VB
1
2
cap
capCtrl
1Out
1In
Q C
oil
Lim
Out
VLim
C2
Lim
C1
Lim
In
SGnd
RF
Mix
Gnd
RF
CC
RF
2In
Mix 2
Out
Mix 1
Out
Mix 1
In
Mix 1
In1 2
Out
Vag
PD ref
Gnd
PLL
T Dat
a
EN Clk
Clk
Out
CD
Out
xPD
T xVC
O
PLL
V
Rx
LO2
InLO
2
1st Mix 2nd Mix
2nd LO
1st LO
1st LOVCO
IF Amp/Limiter Detector
RSSI
LPF AALPF
÷2
2nd LO
SC FilterClock Mic Amp
Tx GainAdjust
LPF
ALC
C CapCompressor
LimiterTx
Mute
Ref2
Ref1
Low BatteryDetect
DataAmp
CarrierDetect
Rx GainAdjustRxMute
SpeakerAmp
SpeakerMute
Expander
VolControl
1st LO VB
÷25÷4÷1
12 b ProgRef Ctr
2nd LO
14 b ProgRx Ctr Vref
Reg 2.5 V
14 b ProgTx Ctr µP Serial
Interface
ProgClk Ctr
Tx PhaseDetect
Rx PhaseDetect
2nd LO10.240
PIN CONNECTIONS
QFP–52
121110987654321
Vag
PD ref
Gnd
PLL
T Dat
a
EN Clk
Clk
Out
xPD
T xVC
O
PLL
V
RxO
utLO
2
13
14
15
16
17
18
19
20
21
22
23
24
DA Out
BD Out
T
C Cap
C In
Amp Out
T
DA In
V
R
Det Out
Q Coil
x Out
x In
CCAudio
x Audio In
252627282930313233343536
Lim
Out
VLim
C2
Lim
C1
Lim
In
RSS
I
Mix
Gnd
RF
CC
RF
2In
Mix 2
Out
Mix 1
Out
Mix 1
In
Mix 1
In1 2
48
47
46
45
44
43
42
41
40
39
38
37LO
LO
V
Gnd Audio
SA Out
SA In
E Out
E
E In
Scr Out
LO2
VB
cap
capCtrl
1Out
1In
1st Mix 2nd Mix
2nd LO
LPF AALPF
CarrierDetect
DataAmp
VCC Audio
µP SerialInterface
ProgClk Ctr
Tx PhaseDetect
Rx PhaseDetect
Reg 2.5 V
14 b ProgTx Ctr
Mic Amp
SpeakerAmp
SpeakerMute
Expander
VolControl
÷25÷4÷1
12 b ProgRef Ctr
VB1st LO
ProgrammableLow Battery
DetectIn
CD
Out
LQFP–48
6 b ProgSC Clk Ctr
1st LO
Detector
RSSI
IF Amp/Limiter
2nd LO
1st LOVCO
14 b ProgRx Ctr Vref
2nd LO10.240
LPF
LPF
4.129 kHz
Bypass
Bypass
4.129 kHz
÷40ScramblerModulating Clock
= MC13110A/B Only
Scrambler
NOTE:
Rx GainAdjustRxMute
÷2SC FilterClock
Tx GainAdjust
LPF
ALC
C CapCompressor
LimiterTx
Mute
6 b ProgSC Clk Ctr
LPF
LPF
4.129 kHz
Bypass
Bypass
4.129 kHz
÷40ScramblerModulating Clock
Scrambler
2nd LO
MC13110A/B MC13111A/B
3MOTOROLA ANALOG IC DEVICE DATA
MAXIMUM RATINGS
Characteristic Symbol Value UnitÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Power Supply Voltage ÁÁÁÁÁÁÁÁ
VCCÁÁÁÁÁÁÁÁÁÁ
–0.5 to +6.0ÁÁÁÁÁÁ
Vdc
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Junction Temperature ÁÁÁÁÁÁÁÁ
TJÁÁÁÁÁÁÁÁÁÁ
–65 to +150ÁÁÁÁÁÁ
°C
Maximum Power Dissipation, TA = 25°C PD 70 mW
NOTES: 1. Devices should not be operated at these limits. The “Recommended Operating Conditions” provide for actual device operation.
2. ESD data available upon request.
RECOMMENDED OPERATING CONDITIONS
Characteristic Symbol Min Typ Max Unit
Supply Voltage VCC 2.7 3.6 5.5 Vdc
Operating Ambient Temperature TA –40 – 85 °C
Input Voltage Low (Data, Clk, EN) VIL – – 0.3 V
Input Voltage High (Data, Clk, EN) VIH PLL Vref –0.3
– – V
Bandgap Reference Voltage VB – 1.5 – V
NOTE: 3. All limits are not necessarily functional concurrently.
DC ELECTRICAL CHARACTERISTICS (VCC = 3.6 V, TA = 25°C, unless otherwise specified, IP3 = 0;Test Circuit Figure 1.)
Tx High Frequency Corner [Note 7](VTx In = –10 dBV, Mic Amp = Unity Gain)
1 Tx In Tx Out Tx fc 3.6 3.7 3.8 kHz
NOTE: 7. The filter specification is based on a 10.24 MHz 2nd LO, and a switched–capacitor (SC) filter counter divider ratio of 31. If other 2nd LO frequencies and/or SC filter counter divider ratios are used, the filter corner frequency will be proportional to the resulting SC filter clock frequency.
MC13110A/B MC13111A/B
8 MOTOROLA ANALOG IC DEVICE DATA
ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.6 V, VB = 1.5 V, TA = 25°C, Active or Rx Mode, unless otherwise specified;Test Circuit Figure 1.)
Characteristic UnitMaxTypMinSymbolMeasure
PinInput
PinFigure
Tx AUDIO PATH (fin = 1.0 kHz, Tx Gain Adj = (01111); ALC, Limiter, and Mutes Disabled; Active Mode, scrambler bypassed)
Low Pass Filter Passband Ripple (Vin = –10 dBV) 1, 84 Tx In Tx Out Ripple – 0.7 1.2 dB
Maximum Compressor Gain (Vin = –70 dBV) – C In Tx Out AVmax – 23 – dB
Tx Gain Adjust Range (Programmable throughMPU Interface)
125 C In Tx Out Tx Range – –9.0 to10
– dB
Tx Gain Adjust Steps – Number of ProgrammableLevels
125 C In Tx Out Tx n – 20 – –
Rx AND Tx SCRAMBLER (2nd LO = 10.24 MHz, Tx Gain Adj = (01111), Rx Gain Adj = (01111), Volume Control = (0 dB Default Levels),SCF Clock Divider = 31. Total is divide by 62 for SCF clock frequency of 165.16 kHz)
Rx High Frequency Corner (Note 8)Rx Path, f = 479 Hz, V Rx Audio In = –20 dBV
– Rx Audio In Scr Out Rx fch 3.55 3.65 3.75 kHz
Tx High Frequency Corner (Note 8)Tx Path, f = 300 Hz, V Tx In = –10 dBV, Mic Amp = Unity Gain
Group DelayRx + Tx Path – 1.0 µF from Tx Out to Rx Audio In, fin = 1.0 kHz
– C In E Out GD – 1.0 –ms
x , infin = low corner frequency to high cornerfrequency
– C In E Out GD – 4.0 –
Carrier BreakthroughRx + Tx Path – 1.0 µF from Tx Out to Rx Audio In
– C In E Out CBT – –60 – dB
Baseband BreakthroughRx + Tx Path – 1.0 µF from Tx Out to Rx Audio In, fin = 1.0 kHz, fmeas = 3.192 kHz
– C In E Out BBT – –50 – dB
LOW BATTERY DETECT
Average ThresholdVoltage Before Electronic Adjustment(Vref_Adj = (0111))
1, 131 Ref1Ref2
BD1 OutBD2 Out
VTi 1.38 1.48 1.58 V
Average ThresholdVoltage After Electronic Adjustment(Vref_Adj = (adjusted value))
1 Ref1Ref2
BD1 OutBD2 Out
VTf 1.475 1.5 1.525 V
Hysteresis – Ref1Ref2
BD1 OutBD2 Out
Hys – 4.0 – mV
Input Current (Vin = 1.0 and 2.0 V) 1 – Ref1Ref2
Iin –50 – 50 nA
Output High Voltage (Vin = 2.0 V) 1 Ref1Ref2
BD1 OutBD2 Out
VOH VCC –0.1
3.6 – V
NOTE: 8. The filter specification is based on a 10.24 MHz 2nd LO, and a switch–capacitor (SC) filter counter divider ratio of 31. If other 2nd LO frequencies and/or SC filter counter divider ratios are used, the filter corner frequency will be proportional to the resulting SC filter clock frequency.
MC13110A/B MC13111A/B
9MOTOROLA ANALOG IC DEVICE DATA
ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.6 V, VB = 1.5 V, TA = 25°C, Active or Rx Mode, unless otherwise specified;Test Circuit Figure 1.)
Characteristic UnitMaxTypMinSymbolMeasure
PinInput
PinFigure
LOW BATTERY DETECT
Output Low Voltage (Vin = 1.0 V) 1 Ref1Ref2
BD1 OutBD2 Out
VOL – 0.2 0.4 V
BATTERY DETECT INTERNAL THRESHOLD
After Electronic Adjustment of VB Voltage 1, 128 VCC Audio BD2 Out VBD Select = (111)
These pins form the PLL reference oscillator whenconnected to an external parallel–resonant crystal(10.24 MHz typical). The reference oscillator isalso the second Local Oscillator (LO2) for the RFreceiver. “LO2 In” may also serve as an input foran externally generated reference signal which istypically ac–coupled.
When the IC is set to the inactive mode, LO2 In isinternally pulled low to disable the oscillator. Theinput capacitance to ground at each pin (LO2 In/LO2 Out) is 3.0 pF.
This pin is a tri–state voltage output of the Rx andTx Phase Detector. It is either “high”, “low”, or “highimpedance,” depending on the phase difference ofthe phase detector input signals. During lock, verynarrow pulses with a frequency equal to theÁÁÁÁ
narrow pulses with a frequency equal to thereference frequency are present. This pin drivesthe external Rx and Tx PLL loop filters. Rx and TxPD outputs can sink or source 1.0 mA.
PLL Vref is a PLL voltage regulator output pin. Aninternal voltage regulator provides a stable powersupply voltage for the Rx and Tx PLL’s and canalso be used as a regulated supply voltage forother IC’s. It can source up to 1.0 mA externally.Proper supply filtering is a must on this pin. PLLVref is pulled up to VCC audio for the standby andinactive modes (Note 1).
ÁÁÁÁÁÁÁÁ6
ÁÁÁÁÁÁÁÁ7
ÁÁÁÁÁÁÁÁÁÁGnd PLL
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁGround pin for digital PLL section of IC.ÁÁÁÁ
Tx VCO is the transmit divide counter input whichis driven by an ac–coupled external transmit loopVCO. The minimum signal level is 200 mVpp @60.0 MHz. This pin also functions as the test modeinput for the counter tests.
Microprocessor serial interface input pins are forprogramming various counters and controlfunctions. The switching thresholds are referencedto PLL Vref and Gnd PLL. The inputs operate up toVCC. These pins have 1.0 µA internal pull–downcurrents.
The microprocessor clock output is derived fromthe 2nd LO crystal oscillator and a programmabledivider with divide ratios of 2 to 312.5. It can beused to drive a microprocessor and therebyreduce the number of crystals required in thesystem design. The driver has an internal resistorin series with the output which can be combinedwith an external capacitor to form a low pass filterto reduce radiated noise on the PCB. This outputalso functions as the output for the counter testmodes.
1) For the MC13110A/B and MC13111A/B the ClkOut can be disabled via the MPU interface.
2) For the MC13110B and MC13111B this output isalways active (on) (Note 2).ÁÁÁÁ
Tx Out is the Tx path audio output. Internally thispin has a low–pass filter circuitry with –3 dBbandwidth of 4.0 kHz. Tx gain and mute areprogrammable through the MPU interface. This pinis sensitive to load capacitance.
C Cap is the compressor rectifier filter capacitorpin. It is recommended that an external filtercapacitor to VCC audio be used. A practicalcapacitor range is 0.1 to 1.0 µF. 0.47 µF is therecommended value.
Tx In is the Tx path input to the microphoneamplifier (Mic Amp). An external resistor isconnected to this pin to set the Mic Amp gain andinput impedance. Tx In must be ac–coupled, too.
RSSI is the receive signal strength indicator. Thispin must be filtered through a capacitor to ground.The capacitance value range should be 0.01 to0.1 µF. This is also the input to the Carrier Detectcomparator. An external R to ground shifts theRSSI voltage.
A quad coil or ceramic discriminator connects thispin as part of the FM demodulator circuit.DC–couple this pin to VCC RF through the quadcoil or the external resistor.
ÁÁÁÁÁÁÁÁÁÁÁÁ
26 ÁÁÁÁÁÁÁÁÁÁÁÁ
29 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
VCC RF ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
VCC supply for RF receiver section (1st LO, mixer,limiter, demodulator). Proper supply filtering isneeded on this pin too.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
25 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
28 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Lim Out ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
A quad coil or ceramic discriminator are connectedto these pins as part of the FM demodulator circuit.A coupling capacitor connects this pin to the quadcoil or ceramic discriminator as part of the FMdemodulator circuit. This pin can drive couplingcapacitors up to 47 pF with no deterioration inperformance.
Mix2 In is the second mixer input. Signals are to beac–coupled to this pin, which is biased internally toVCC RF. The input impedance is2.8 kΩ at 455 kHz. The input impedance can bereduced by connecting an external resistor toVCC RF.
Mix2 Out is the second mixer output. The secondmixer has a 3 dB bandwidth of 2.5 MHz and anoutput impedance of 1.5 kΩ. The output currentdrive is 50 µA.
ÁÁÁÁÁÁÁÁ
33 ÁÁÁÁÁÁÁÁ
36 ÁÁÁÁÁÁÁÁÁÁ
Gnd RF ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Ground pin for RF section of the IC.ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Signals should be ac–coupled to this pin, which isbiased internally to VCC – 1.6 V. The single–endedand differential input impedance are about 1.6 and1.8 kΩ at 46 MHz, respectively.
Tank Elements, an internal varactor and capacitormatrix for 1st LO multivibrator oscillator areconnected to these pins. The oscillator is useableup to 80 MHz.
Vcap Ctrl is the 1st LO varactor control pin. Thevoltage at this pin is referenced to Gnd Audio andvaries the capacitance between LO1 In andLO2 Out. An increase in voltage will decreasecapacitance.
The speaker amplifier gain is set with an externalfeedback resistor. It should be less than 200 kΩ.The speaker amplifier can be muted through theMPU interface.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
42 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
45 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
SA In(Input)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
SA Out
VB
SA In ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
An external resistor is connected to the speakeramplifier input (SA In). This will set the gain andinput impedance and must be ac–coupled.
E Cap is the expander rectifier filter capacitor pin.Connect an external filter capacitor between VCCaudio and E Cap. The recommended capacitancerange is 0.1 to 1.0 µF. 0.47 µF is the suggestedvalue.
VB is the internal half supply analog groundreference. This pin must be filtered with acapacitor to ground. A typical capacitor range of0.5 to 10 µF is desired to reduce crosstalk andnoise. It is important to keep this capacitor valueequal to the PLL Vref capacitor due to logic timing(Note 9).
NOTE: 9. A capacitor range of 0.5 to 10 µF is recommended. The capacitor value should be the same used on the VB pin (Pin 52). An additional highquality parallel capacitor of 0.01 µF is essential to filter out spikes originating from the PLL logic circuitry.
MC13110A/B MC13111A/B
17MOTOROLA ANALOG IC DEVICE DATA
DEVICE DESCRIPTION AND APPLICATION INFORMATION
The following text, graphics, tables and schematics areprovided to the user as a source of valuable technicalinformation about the Universal Cordless Telephone IC. Thisinformation originates from thorough evaluation of the deviceperformance for the US and French applications. This datawas obtained by using units from typical wafer lots. It isimportant to note that the forgoing data and information wasfrom a limited number of units. By no means is the user toassume that the data following is a guaranteed parametric.Only the minimum and maximum limits identified in theelectrical characteristics tables found earlier in this spec areguaranteed.
General Circuit DescriptionThe MC13110A/B and MC13111A/B are a low power dual
conversion narrowband FM receiver designed forapplications up to 80 MHz carrier frequency. This device isprimarily designated to be used for the 49 MHz cordlessphone (CT–0), but has other applications such as low datarate narrowband data links and as a backend device for 900MHz systems where baseband analog processing isrequired. This device contains a first and second mixer,limiter, demodulator, extended range receive signal strength(RSSI), receive and transmit baseband processing, dualprogrammable PLL, low battery detect, and serial interfacefor microprocessor control. The FM receiver can also beused with either a quadrature coil or ceramic resonator.Refer to the Pin Function Description table for the simplifiedinternal circuit schematic and description of this device.
DC Current and Battery DetectFigures 3 through 6 are the current consumption for
Inactive, Standby, Receive, and Active modes versus supplyvoltages. Figures 7 and 8 show the typical behavior of currentconsumption in relation to temperature. The relationship ofadditional current draw due to IP3 bit set to <1> and supplyvoltage are shown in Figures 9 and 10.
For the Low Battery Detect, the user has the option tooperate the IC in the programmable or non–programmablemodes. Note that the 48 pin package can only be used in theprogrammable mode. Figure 128 describes this operation(refer to the Serial Interface section under Clock DividerRegister).
In the programmable mode several different internalthreshold levels are available (Figure 2). The bits are setthrough the SCF Clock Divider Register as shown in Figures108 and 126. The reference for the internal divider network isVCC Audio. The voltages on the internal divider network arecompared to the Internal Reference Voltage, VB, generatedby an internal source. Since the internal comparator used isnon–inverting, a high at VCC Audio will yield a high at the
battery detect output, and vice versa for VCC Audio set to alow level. For the 52 pin package option, the Ref 1 and Ref 2pins need to be tied to VCC when used in the programmablemode. It is essential to keep the external reference pinsabove Gnd to prevent any possible power–on reset to beactivated.
When considering the non–programmable mode (bits setto <000>) for the 52 pin package, the Ref 1 and Ref 2 pinsbecome the comparators reference. An internal switch isactivated when the non–programmable mode is chosenconnecting Ref 1 and Ref 2. Here, two external precisionresistor dividers are used to set independent thresholds fortwo battery detect hysteresis comparators. The voltages onRef 1 and Ref 2 are again compared to the internallygenerated 1.5 V reference voltage (VB).
The Low Battery Detect threshold tolerance can beimproved by adjusting a trim–pot in the external resistordivider (user designed). The initial tolerance of the internalreference voltage (VB) is ±6.0%. Alternately, the tolerance ofthe internal reference voltage can be improved to ±1.5%through MPU serial interface programming (refer to the SerialInterface section, Figure 131). The internal reference can bemeasured directly at the “VB” pin. During final test of thetelephone, the VB internal reference voltage is measured.Then, the internal reference voltage value is adjustedelectronically through the MPU serial interface to achieve thedesired accuracy level. The voltage reference register valueshould be stored in ROM during final test so that it can bereloaded each time the combo IC is powered up. The LowBattery Detect outputs are open collector. The battery detectlevels will depend on the accuracy of the VB voltage. Figure12 indicates that the VB voltage is fairly flat over temperature.ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Supply Current Consumption versus Temperature Normalized to 25 °C
–20
–15
–10
–5
0
5
10
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90
TA, TEMPERATURE (°C)
DEL
TA C
UR
REN
T D
RAI
N (%
FR
OM
25
C)
°
ÁÁÁÁÁÁÁÁÁÁ
Receive/Active ÁÁÁÁÁÁÁÁ
Receive/Active
650
500
Figure 11. Current StandbyMode versus MCU Clock Output
300
350
400
450
550
600
700
750
800
1.0 10 100 1000
MCU CLK OUT DIVIDE VALUE
No load
MCU clock off
10 pF load
STD
I
, S
UPP
LY C
UR
REN
T (m
A)C
C
Figure 12. VB Voltage versus TemperatureNormalized to 1.5 V at 25 °C
1.4925
1.4950
1.4975
1.5000
1.5025
1.5050
1.5075
–20 –10 0 10 20 30 40 50 60 70 80 90
TA, TEMPERATURE (°C)
V ,
NO
RM
ALIZ
ED V
B VO
LTAG
E (V
)s
MC13110A/B MC13111A/B
20 MOTOROLA ANALOG IC DEVICE DATA
FIRST AND SECOND MIXER
Mixer Description
The 1st and 2nd mixers are similar in design. Both aredouble balanced to suppress the LO and the inputfrequencies to give only the sum and difference frequenciesat the mixer output. Typically the LO is suppressed betterthan –50 dB for the first mixer and better than –40 dB for thesecond mixer. The gain of the 1st mixer has a –3.0 dB cornerat approximately 13 MHz and is used at a 10.7 MHz IF. It hasan output impedance of 300 Ω and matches to a typical10.7 MHz ceramic filter with a source and load impedance of330 Ω. A series resistor may be used to raise the impedancefor use with crystal filters. They typically have an inputimpedance much greater than 330 Ω.
First Mixer
Figures 17 through 20 show the first mixer transfer curvesfor the voltage conversion gain, output level, andintermodulation. Notice that there is approximately 10 dBlinearity improvement when the “IP3 Increase” bit is set to<1>. The “IP3 Increase” bit is a programmable bit as shown inthe Serial Programmable Interface section under the RxCounter Latch Register. The IP3 = <1> option will increasethe supply current demand by 1.3 mA.
Figure 13. First Mixer Input and Output ImpedanceSchematic
1st Mixer
Mix1 In Mix1 OutRPI CPI RPOCPO
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁFigure 14. First Mixer Output ImpedanceÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁUnit
Figures 13, 14, and 16 represent the input and outputimpedance for the first mixer. Notice that the inputsingle–ended and differential impedances are basically thesame. The output impedance as described in Figure 14 willbe used to match to a ceramic or crystal filter’s inputimpedance. A typical ceramic filter input impedance is 330 Ωwhile crystal filter input impedance is usually 1500 Ω. Exactimpedance matching to ceramic filters are not critical,however, more attention needs to be given to the filtercharacteristics of a crystal filter. Crystal filters are muchnarrower. It is important to accurately match to these filters toguaranty a reasonable response.
To find the IF bandwidth response of the first mixer refer toFigure 22. The –3.0 dB bandwidth point is approximately 13MHz. Figure 15 is a summary of the first mixer feedthroughparameters.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 15. First Mixer Feedthrough ParametersÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Parameter ÁÁÁÁÁÁÁÁÁÁ
(dBm)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ1st LO Feedthrough @ Mix1 In1
ÁÁÁÁÁÁÁÁÁÁ
–70.0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ1st LO Feedthrough @ Mix1 Out ÁÁÁÁÁ
ÁÁÁÁÁ–55.5
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁRF Feedthrough @ Mix1 Out with –30 dBm ÁÁÁÁÁ
Note: 11. Single–Ended data is from measured results. Differential data is from simulated results.
MC13110A/B MC13111A/B
21MOTOROLA ANALOG IC DEVICE DATA
Mix
1O
ut, M
IXER
OU
TPU
T (d
Bm)
1.0
15
–40
0
–40
14
2.7
–10
–40
0
–40
14
f, IF FREQUENCY (MHz)
Mix1 In, MIXER INPUT LEVEL (dBm)
Mix1 In, MIXER INPUT LEVEL (dBm)
V O1.
0 dB
Mix
VCC Audio, AUDIO SUPPLY VOLTAGE (V)
Mix
1O
ut, M
IXER
OU
TPU
T (d
Bm)
Mix1 In, MIXER INPUT LEVEL (dBm)
MX g
ain1
, VO
LTAG
E
Figure 17. First Mixer Voltage ConversionGain, IP3_bit = 0
Mix1 In, MIXER INPUT LEVEL (dBm)
Figure 18. First Mixer Voltage ConversionGain, IP3_bit = 1
Figure 19. First Mixer Output Level andIntermodulation, IP3_bit = 0
Figure 20. First Mixer Output Level andIntermodulation, IP3_bit = 1
Figure 21. First Mixer Compression versus Supply Voltage
Figure 22. First IF Bandwidth
Fundamental Level
3rd OrderIntermodulation
Fundamental Level
3rd OrderIntermodulation
CO
NVE
RSI
ON
GAI
N (d
B) 12
–20
10
–20
12
–40
8.0
–40
10
–60–60
8.0
4.0
–80–80
2.0
–100–100
10–12
5.0–14
0–16
–5.0–18
–10–20
–15–22
–35–35 –30–30 –25–25 –20–20 –15–15 –10–10
10
–35
3.3
–35 –30–30 –25–25 –20
4.2
–20 –15
4.8
–15 –10
5.4
–10
1003.6 3.9 4.53.0 5.1
IP3_bit = 1
1, 1.0
dB
VOLT
AGE
CO
MPR
ESSI
ON
(dBm
)
6.0
6.0
IP3_bit = 0
MX g
ain1
, VO
LTAG
E
CO
NVE
RSI
ON
GAI
N (d
B)
MX g
ain1
, VO
LTAG
E
CO
NVE
RSI
ON
GAI
N (d
B)
VCC = 3.6 VIF = 10.695 MHz, 330 Ω
VCC = 3.6 VIF = 10.695 MHz, 330 Ω
VCC = 3.6 VIF = 10.695 MHz, 330 Ω
VCC = 3.6 VIF = 10.695 MHz, 330 Ω
FIRST MIXER
IF = 10.695 MHz, 330 Ω
VCC = 3.6 VRL = 330 ΩLO = 36.075 MHz
MC13110A/B MC13111A/B
22 MOTOROLA ANALOG IC DEVICE DATA
Second Mixer
Figures 26 through 29 represents the second mixertransfer characteristics for the voltage conversion gain,output level, and intermodulation. There is a slightimprovement in gain when the “IP3 bit” is set to <1> for thesecond mixer. (Note: This is the same programmable bitdiscussed earlier in the section.)
Figure 23. Second Mixer Input and OutputImpedance Schematic
Figure 24. Second Mixer Input and OutputImpedances
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Unit
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Input ImpedanceRPI // CPI
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
OutputImpedanceRPO // CPO
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
IP3 = <0> (Set Low)ÁÁÁÁÁÁÁÁÁÁÁÁ
2817 Ω // 3.6 pF ÁÁÁÁÁÁÁÁÁÁÁÁ
1493 Ω // 6.1 pF
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
IP3 = <1> (Set High)ÁÁÁÁÁÁÁÁÁÁÁÁ
2817 Ω // 3.6 pF ÁÁÁÁÁÁÁÁÁÁÁÁ
1435 Ω // 6.2 pF
The 2nd mixer input impedance is typically 2.8 kΩ. Itrequires an external 360 Ω parallel resistor for use with astandard 330 Ω, 10.7 MHz ceramic filter. The second mixeroutput impedance is 1.5 kΩ making it suitable to matchstandard 455 kHz ceramic filters.
The IF bandwidth response of the second mixer is shownin Figure 31. The –3.0 dB corner is 2.5 MHz. The feedthroughparameters are summarized in Figure 25.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 25. Second Mixer Feedthrough ParametersÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ParameterÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(dBm)ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
2nd LO Feedthrough @ Mix2 OutÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
–42.9ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁIF Feedthrough @ Mix2 Out with –30 dBm
ÁÁÁÁÁÁÁÁÁÁ–61.7
MC13110A/B MC13111A/B
23MOTOROLA ANALOG IC DEVICE DATA
0.12.7
Mix
2O
ut, M
IXER
OU
TPU
T (d
Bm)
V O1.
0 dB
Mix
2, 1.0
dB
MX
gain
2, V
OLT
AGE
CO
NVE
RSI
ON
GAI
N (d
B)
25
10
–10
–40
10
22
f, IF FREQUENCY (MHz)
Mix2 In, MIXER INPUT LEVEL (dBm)
Mix2 In, MIXER INPUT LEVEL (dBm)
VCC Audio, AUDIO SUPPLY VOLTAGE (V)
Mix2 In, MIXER INPUT LEVEL (dBm)
Figure 26. Second Mixer Conversion Gain,IP3_bit = 0
Mix2 In, MIXER INPUT LEVEL (dBm)
Figure 27. Second Mixer Conversion Gain, IP3_bit = 1
Figure 28. Second Mixer Output Level andIntermodulation, IP3_bit = 0
Figure 29. Second Mixer Output Level andIntermodulation, IP3_bit = 1
Figure 30. Second Mixer Compressionversus Supply Voltage
Figure 31. Second IF Bandwidth
Mix
2O
ut, M
IXER
OU
TPU
T (d
Bm)
VOLT
AGE
CO
MPR
ESSI
ON
(dBm
)
Fundamental Level
3rd OrderIntermodulation
IP3_bit = 1
IP3_bit = 0
Fundamental Level
3rd OrderIntermodulation
–10
20
–30
18
–50
16
–70
–90
–12
–14
–16
–18
–20
–22
12
14
22
20
–10
18
–30
16
–50
14
–70
–90
20
15
10
5.0
0
–40
–40–40 –35–35 –30–30 –25–25 –20–20 –15–15 –10–10
1.0
–35
3.3
–35 –30–30 –25–25 –20
4.2
–20 –15
4.8
–15 –10
5.4
–10
103.6 3.9 4.53.0 5.1
MX
gain
2, V
OLT
AGE
CO
NVE
RSI
ON
GAI
N (d
B)
MX
gain
2, V
OLT
AGE
CO
NVE
RSI
ON
GAI
N (d
B)
VCC = 3.6 VIF = 455 kHzRL = 1500 Ω
SECOND MIXER
VCC = 3.6 VIF = 455 kHzRL = 1500 Ω
VCC = 3.6 VIF = 455 kHzRL = 1500 Ω
VCC = 3.6 VIF = 455 kHzRL = 1500 Ω
IF = 455 kHzRL = 1500 Ω
VCC = 3.6 VRL = 1500 Ω
MC13110A/B MC13111A/B
24 MOTOROLA ANALOG IC DEVICE DATA
First Local Oscillator
The 1st LO is a multi–vibrator oscillator. The tank circuit iscomposed of a parallel external capacitance and inductance,internal programmable capacitor matrix, and internalvaractor. The local oscillator requires a voltage controlledinput to the internal varactor and an external loop filter drivenby on–board phase–lock control loop (PLL). The 1st LOinternal component values have a tolerance of ±15%. Atypical dc bias level on the LO Input and LO Output is 0.45Vdc. The temperature coefficient of the varactor is+0.08%/°C. The curve in Figure 33 is the varactor controlvoltage range as it relates to varactor capacitance. Itrepresents the expected internal capacitance for a givencontrol voltage (VcapCtrl) of the MC13110A/B andMC13111A/B. Figure 32 shows a representative schematic ofthe first LO function.
LO1 In
LO1 Out
Vcap Ctrl
ProgrammableInternalCapacitor
1st LO
Varactor
VaractorCext
Lext
Figure 32. First Local Oscillator Schematic
To select the proper Lext and Cext we can do the followinganalysis. From Figure 34 it is observed that an inductor willhave a significant affect on first LO performance, especiallyover frequency. The overall minimum Q required for first LOto function as it relates to the LO frequency is also given inFigure 34.
Choose an inductor value, say 470 nH. From Figure 34,the minimum operating Q is approximately 25. From thefollowing equation:
Q Coil = Rp/X Coil
where: Rp = parallel equivalent impedance (Figure 35).
Figure 34 clearly indicates that for lower coil values, higherquality factors (Q) are required for the first LO to functionproperly. Also, lower LO frequencies need higher Q’s. InFigure 35 the internal programmable capacitor selectionrelative to the first LO frequency and the parallel impedanceis shown. This information will help the user to decide whatinductor (Lext) to choose for best performance in terms of Q.
Refer to the Auxiliary Register in the Serial InterfaceSection for further discussion on LO programmability.
MC13110A/B MC13111A/B
25MOTOROLA ANALOG IC DEVICE DATA
100
120
0
100O
VER
ALL
MIN
IMU
M Q
VAL
UE
LO INDUCTOR VALUE (nH)
RP, R
EPR
ESEN
TATI
VE P
ARAL
LEL
Ω
C1–C15, CAPACITANCE SELECT
Figure 33. First LO Varicap Capacitanceversus Control Voltage
Figure 34. First LO Minimum Required OverallQ Value versus Inductor Value
Figure 36. Varicap Value at V CV = 1.0 V Over Temperature
Figure 37. Control Voltage versusChannel Number, U.S. Handset Application
Figure 38. Control Voltage versusChannel Number, U.S. Baseset Application
30 MHz
40 MHz
50 MHz
30 MHz
40 MHz
50 MHz
IMPE
DAN
CE
(k
)
100
80
60
40
20
0
10
1000
1 6 4 3 8 9 10 11 12 13 14 152 5 7
FIRST LOCAL OSCILLATOR
0
15
, CAP
ACIT
ANC
E (p
F)
VcapCtrl, CONTROL VOLTAGE (V)
14
12
13
11
10
9.0
8.0
7.00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
V cap
10.2
V cap, C
APAC
ITAN
CE
(pF)
TA, AMBIENT TEMPERATURE (°C)
9.8
9.4
9.8–20 0 25 70 8555
10.6
11
1
1.7
CH1–CH25, U.S. HANDSET CHANNEL APPLICATION
Cap 11
Cap 10
Cap 9
Cap 61.6
1.5
1.4
1.3
1.2
1.1
1.0
0.93 5 7 9 11 13 15 17 19 21 23 25
1.8
Ctrl
, CO
NTR
OL
VOLT
AGE
(V) 1.7
CH1–CH25, U.S. BASESET CHANNEL APPLICATION
Cap 8Cap 3
Cap 4
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.81 3 5 7 9 11 13 15 17 19 21 23 25
V cap
1.8
Ctrl
, CO
NTR
OL
VOLT
AGE
(V)
V cap
MC13110A/B MC13111A/B
26 MOTOROLA ANALOG IC DEVICE DATA
Second Local Oscillator
The 2nd LO is a CMOS oscillator. It is used as the PLLreference oscillator and local oscillator for the secondfrequency conversion in the RF receiver. It is designed toutilize an external parallel resonant crystal. See schematic inFigure 39.
Figure 40. Second Local OscillatorInput and Output Impedance
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Input Impedance (RPI // CPI) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
11.6 kΩ // 2.9 pF
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Output Impedance (RPO // CPO)ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
9.6 kΩ // 2.7 pF
Figure 41 shows a typical gain/phase response of thesecond local oscillator. Load capacitance (CL), equivalentseries resistance (ESR), and even supply voltage will haveand affect on the 2nd LO response as shown in Figures 45and 46. Except for the standby mode open loop gain is fairlyconstant as supply voltage increases from 2.5 V. This is dueto the regulated voltage of 2.5 V on PLL Vref. From the graphsit can seen that optimum performance is achieved when C1equals C2 (C1/C2 = 1).
Figure 46 represents the ESR versus crystal loadcapacitance for the 2nd LO. This relationship was defined byusing a 6.0 dB minimum loop gain margin at 3.6 V. This isconsidered the minimum gain margin to guarantee oscillatorstart–up.
Oscillator start–up is also significantly affected by thecrystal load capacitance selection. In Figures 42 and 43 therelationship between crystal load capacitance, supplyvoltage, and external load capacitance ratio (C2/C1), can beseen. The lower the load capacitance the better theperformance.
Given the desired crystal load capacitance, C1 and C2can be determined from Figure 47. It is also interesting topoint out that current consumption increases when C1 ≠ C2,as shown in Figure 44.
Be careful not to overdrive the crystal. This could cause anoise problem. An external series resistor on the crystaloutput can be added to reduce the drive level, if necessary.
V gain
2, LO
VO
LTAG
E G
AIN
(dB)
0
6.0
10.235
15
STAR
T–U
P TI
ME
(ms)
CAPACITOR RATIO (C2:C1)
Figure 41. Second LO Gain/Phase @ –10 dBm
f, FREQUENCY (MHz)
Figure 42. Start–Up Time versus CapacitorRatio, Inactive to R x Mode
Figure 43. Start–Up Time versus CapacitorRatio, Inactive to R x Mode
Figure 44. Second LO Current Consumptionversus Capacitor Ratio
Figure 45. Maximum Open Loop Gain versus Capacitor Ratio
10
1000Ω
ESR
, EQ
UIV
ALEN
T R
ESIS
TAN
CE
( )
CRYSTAL LOAD CAPACITANCE (pF)
Figure 46. Maximum AllowableEquivalent Series Resistance (ESR)
versus Crystal Load Capacitance
10
100
12 14 16 18 20 22 24 26 28 30 32
Curve Valid for fosc in the Range of 10 MHz to 12 MHz
0
70
OPT
IMU
M C
1 AN
D C
2 VA
LUE
(pF)
REQUIRED PARALLEL CRYSTAL LOAD CAPACITANCE (pF)
Figure 47. Optimum Value for C1 and C2versus Equivalent Required Parallel
Capacitance of the Crystal
50
60
40
30
20
10
05.0 10 15 20 30 3525
C1 = C2
MC13110A/B MC13111A/B
28 MOTOROLA ANALOG IC DEVICE DATA
IF Limiter and Demodulator
The limiting IF amplifier typically has about 110 dB of gain;the frequency response starts rolling off at 1.0 MHz.Decoupling capacitors should be placed close to Pins 31 and32 to ensure low noise and stable operation. The IF inputimpedance is 1.5 kΩ. This is a suitable match to 455 kHzceramic filters.
The quadrature detector is coupled to the IF with anexternal capacitor between Pins 27 and 28. Thus, therecovered signal level output is increased for a givenbandwidth by increasing the capacitor. The externalquadrature component may be either a LCR resonant circuit,which may be adjustable, or a ceramic resonator which isusually fixed tuned. (More on ceramic resonators later.)
The bandwidth performance of the detector is controlledby the loaded Q of the LC tank circuit (Figure 50). Thefollowing equation defines the components which set thedetector circuit’s bandwidth:
(1) RT = Q XL,
where RT is the equivalent shunt resistance across the LCtank. XL is the reactance of the quadrature inductor at the IFfrequency (XL= 2π f L).
The 455 kHz IF center frequency is calculated by:
(2) fc = [2π (L Cp)1/2] – 1
where L is the parallel tank inductor. Cp is the equivalentparallel capacitance of the parallel resonant tank circuit.
The following is a design example for a detector at 455kHz and a specific loaded Q:
The loaded Q of the quadrature detector is chosensomewhat less than the Q of the IF bandpass for margin. Foran IF frequency of 455 kHz and an IF bandpass of 20 kHz,
the IF bandpass Q is approximately 23; the loaded Q of thequadrature tank is chosen slightly lower at 15.
Example:
Let the total external C = 180 pF. (Note: the capacitance isthe typical capacitance for the quad coil.) Since the externalcapacitance is much greater than the internal device andPCB parasitic capacitance, the parasitic capacitance may beneglected.
Rewrite equation (2) and solve for L:
L = (0.159)2/(C fc2 )L = 678 µH ; Thus, a standard value is chosen:L = 680 µH (surface mount inductor)
The value of the total damping resistor to obtain therequired loaded Q of 15 can be calculated from equation (1):
RT = Q(2π f L)RT = 15(2π)(0.455)(680) = 29.5 kΩ
The internal resistance, Rint at the quadrature tank Pin 27is approximately 100 kΩ and is considered in determining theexternal resistance, Rext which is calculated from:
Rext = ((RT)(Rint))/(Rint – RT)Rext = 41.8 kΩ;Thus, choose a standard value:Rext = 39 kΩ
In Figure 50, the Rext is chosen to be 22.1 kΩ. Anadjustable quadrature coil is selected. This tank circuitrepresents one popular network used to match to the455 kHz carrier frequency. The output of the detector isrepresented as a “S–curve” as shown in Figure 52. The goalis to tune the inductor in the area that is most linear on the“S–curve” (minimum distortion) to optimize the performancein terms of dc output level. The slope of the curve can also beadjusted by choosing higher or lower values of Rext . This willhave an affect on the audio output level and bandwidth. AsRext is increased the detector output slope will decrease.The maximum audio output swing and distortion will bereduced and the bandwidth increased. Of course, just theopposite is true for smaller Rext.
A ceramic discriminator is recommended for thequadrature circuit in applications where fixed tuning isdesired. The ceramic discriminator and a 5.6 kΩ resistor areplaced from Pin 27 to VCC . A 22 pF capacitor is placed fromPin 28 to 27 to properly drive the discriminator. MuRata Eriehas designed a resonator for this part (CDBM455C48 forUSA & A/P regions and CDBM450C48 for Europe). Thisresonator has been designed specifically for theMC13110/111 family. Figure 51 shows the schematic used togenerate the “S–curve” and waveform shown in Figure 54and 55.
MC13110A/B MC13111A/B
29MOTOROLA ANALOG IC DEVICE DATA
Figure 51. Ceramic Resonator DemodulatorSchematic with Murata CDBM450C48
C28390 p
Rext2.7 k
Ceramic ResonatorMurataCDBM450C34
Lim Out1 Q Coil
(CDBM455C48 US; CDBM450C48 France)
The “S–curve” for the ceramic discriminator shown inFigure 54 is centered around 450 kHz. It is for the Frenchapplication. The same resonator is also used for the USapplication and is centered around 455 kHz. Clearly, the“S–curves” for the resonator and quad coil have very similarlimiter outputs. As discussed previously, the slope of the“S–curve” centered around the center frequency can becontrolled by the parallel resistor, Rext. Distortion, bandwidth,and audio output level will be affected.
Figure 52. S–Curve of LimiterDiscriminator with Quadrature Coil
0.2
0.6
1.0
1.4
2.2
425 435 445 485
Lim In, INPUT FREQUENCY (kHz)
1.8
455 465 475
Det
Out
, DC
VO
LTAG
E (V
) Toko 7MCS–8128Z
Figure 53. Typical Limiter OutputWaveform with Quadrature Coil
IF LIMITER AND DEMODULATION
Figure 54. S–Curve of LimiterDiscriminator with Ceramic Resonator
0.60.7
0.80.9
1.01.1
1.21.3
1.7
440 442 444 446 448 460
Lim In, INPUT FREQUENCY (kHz)
1.4
1.5
450 452 454 456 458
Det
Out
, DC
VO
LTAG
E (V
) Murata CDBM450C48
1.6
Figure 55. Typical Limiter OutputWaveform with Ceramic Resonator
AC V
OLT
AGE
LEVE
L (V
)
f = 455 kHzVpptyp = 344 mV
0
1.0
t, TIME (ms)
600
400
200
800
AC V
OLT
AGE
LEVE
L (V
)
f = 450 kHzVpptyp = 370 mV
0
1.0
t, TIME (ms)
600
400
200
800
MC13110A/B MC13111A/B
30 MOTOROLA ANALOG IC DEVICE DATA
RSSI and Carrier Detect
The Received Signal Strength Indicator (RSSI) indicatesthe strength of the IF level. The output is proportional to thelogarithm of the IF input signal magnitude. RSSI dynamicrange is typically 80 dB. A 187 kΩ resistor to ground isprovided internally to the IC. This internal resistor convertsthe RSSI current to a voltage level at the “RSSI” pin. Toimprove the RSSI accuracy over temperature an internalcompensated reference is used. Figure 56 shows the RSSIversus RF input. The slope of the curve is 16.5 mV/dB.
The Carrier Detect Output (CD Out) is an open–collectortransistor output. An external pull–up resistor of 100 kΩ willbe required to bias this device. To form a carrier detect filter acapacitor needs to be connected from the RSSI pin toground. The carrier detect threshold is programmablethrough the MPU interface (see “Carrier Detect ThresholdProgramming” in the serial interface section). The range canbe scaled by connecting additional external resistance from
the RSSI pin to ground in parallel with the capacitor. FromFigure 57, the affect of an external resistor at RSSI on thecarrier detect level can be noticed. Since there is hysteresisin the carrier detect comparator, one trip level can be foundwhen the input signal is increased while the another one canbe found when the signal is decreased.
Figure 58 represents the RSSI ripple in relation to the RFinput for different filtering capacitors at RSSI. Clearly, thehigher the capacitor, the less the ripple. However, at lowcarrier detect thresholds, the ripple might supersede thehysteresis of the carrier detect. The carrier detect output mayappear to be unstable. Using a large capacitor will help tostabilize the RSSI level, but RSSI charge time will beaffected. Figure 59 shows this relationship.
The user must decide on a compromise between the RSSIripple and RSSI start–up time. Choose a 0.01 µf capacitor asa starting point. For low carrier detect threshold settings, a0.047 µf capacitor is recommended.
–60
RSSI AND CARRIER DETECT
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
–120 –100 –80 –60 –40 –20 0
Mix1 In, RF INPUT (dBm)
Figure 56. Typical RSSI VoltageLevel versus RF Input
The sensitivity of the IC is typically 0.4 µVrms matched(single ended or differential) with no preamp. To achievesuitable system performance, a preamp and passiveduplexer may be used. In production final test, each sectionof the IC is separately tested to guarantee its systemperformance in the specific application. The preamp andduplexer (differential, matched input) yields typically–115 dBm @ 12 dB SINAD sensitivity performance under fullduplex operation. See Figure 45 and 48.
The duplexer is important to achieve full duplex operationwithout significant “de–sensing” of the receiver by thetransmitter. The combination of the duplexer and preampcircuit should attenuate the transmitter power to the receiverby over 60 dB. This will improve the receiver system noisefigure without giving up too much IMD performance.
The duplexer may be a two piece unit offered by Shimida,Sansui, or Toko products (designed for 25 channel CT–0cordless phone). The duplexer frequency response at thereceiver port has a notch at the transmitter frequency band ofabout 35 to 40 dB with a 2.0 to 3.0 dB insertion loss at thereceiver frequency band.
The preamp circuit utilizes a tuned transformer at theoutput side of the amplifier. This transformer is designed tobandpass filter at the receiver input frequency while rejectingthe transmitter frequency. The tuned preamp also improvesthe noise performance by reducing the bandwidth of the passband and by reducing the second stage contribution of the1st mixer. The preamp is biased such that it yields suitablenoise figure and gain.
The following matching networks have been used toobtain 12 dB SINAD sensitivity numbers:
1:5 15
1:5 15
Figure 60. Matching Input Networks
Differential Match
Single–ended Match
Single–ended 50 Ω
Mix1 In1
Mix1 In2
Mix1 In1
Mix1 In2
Mix1 In1
Mix1 In2
RF In1
RF In1
RF In1
360
680
39
39
49.9 Ω
0.01
0.01
The exact impedance looking into the RF In1 pin isdisplayed in the following table along with the sensitivitylevels.
The graphs in Figures 64 to 69 are performance resultsbased on Evaluation Board Schematic (Figure 138). Thisevaluation board did not use a duplexer or preamp stage.Figure 62 is a summary of the RF performance and Figure 63contains the French RF Performance Summary.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 62. RF Performance Summaryfor US Applications
Figure 68. 12 dB SINAD Sensitivity OverUS Handset Application Channels
Figure 69. 12 dB SINAD Sensitivity OverUS Baseset Application Channels
–102
–101
–100
–99
–98
–97
–96
1 5 9 13 17 21 25
12 d
B SI
NAD
(dBm
)
US CHANNEL NUMBERS
MC13110A/B MC13111A/B
33MOTOROLA ANALOG IC DEVICE DATA
Receive Audio Path
The Rx Audio signal path begins at “Rx Audio In” and goesthrough the IC to “E Out”. The “Rx Audio In”, “Scr Out”, and“E In” pins are all ac–coupled. This signal path consists offilters; programmable Rx gain adjust, Rx mute, and volumecontrol, and finally the expander. The typical maximumoutput voltage at “E Out” should be approximately 0 dBV @THD = 5.0% .
Figures 71 to 73 represent the receive audio path filterresponse. The filter response attenuation is very sharp above3900 Hz, which is the cutoff frequency. Inband (audio),out–of–band, and ripple characteristics are also shown inthese graphs.
The group delay (Figure 75) has a peak around 6.5 kHz.This spike is formed by rapid change in the phase at thefrequency. In practice this does not cause a problem sincethe signal is attenuated by at least 50 dB.
The output capability at “Scr Out” and “E Out” are shown inFigures 76, 77, and 78. The results were obtained byincreasing the input level for 2.0% distortion at the outputs.
In Figure 70, noise data for the Rx audio path is shown.At Scr Out, the noise level clearly rises when the scrambler is
enabled. However, assuming a nominal output level of –20dBV (100 mVrms) at the 0 dB gain setting, the noise floor ismore than 56 dB below the audio signal. However, the noisedata at E Out and SA Out is much more improved.
Speaker AmpThe Speaker Amp is an inverting rail–to–rail operational
amplifier. The noninverting input is connected to the internalVB reference. External resistors and capacitors are used toset the gain and frequency response. The “SA In” input pinmust be ac–coupled. The typical output voltage at “SA Out” is2.6 Vpp with a 130 Ω load. The speaker amp response isshown in Figures 79 and 80.
Data Amp ComparatorThe data amp comparator is an inverting hysteresis
comparator. Its open collector output has an internal 100 kΩpull–up resistor. A band pass filter is connected between the“Det Out” pin and the “DA In” pin with component values asshown in the Application Circuit schematic. The “DA In” inputsignal needs to be ac–coupled, too.
Figure 73. R x Audio Ripple Response Figure 74. R x Audio Inband Phase Response
Figure 75. R x Audio Inband Group Delay Figure 76. R x Audio Expander Response
135
–5.0
90
–15
0.3
45
0
–25
0.1
–45
–90
–0.1
–0.3–135
–180
–55
–0.5
–110
–5.0
1.0–15
–25
–450.1
–55
–650
10001000 10000 100000 100001000000
–20
10001000
1000
10000
10000
10000
0
GR
OU
P D
ELAY
(ms)
–35
Expander Transfer
Distortion
–10
–30
–50
–90
–70
–45
f, FREQUENCY (Hz)
–35
–35 –30 –25 –15 –10 –5.0
DIS
TORT
ION
(%)
28
24
20
16
8.0
4.0
0
12
Rx Audio Into Scr OutVin = –20 dBV
Rx Audio Into Scr OutVin = –20 dBV
Rx Audio Into Scr OutVin = –20 dBV
Rx Audio Into Scr OutVin = –20 dBV
V
,
gain
VOLT
AGE
GAI
N (d
B)V
,ga
in
Rx Audio Into Scr OutVin = –20 dBV
VOLT
AGE
GAI
N (d
B)V
,ga
inRx AUDIO
MC13110A/B MC13111A/B
35MOTOROLA ANALOG IC DEVICE DATA
Scr O
ut, O
UTP
UT
VOLT
AGE
LEVE
L (d
BV)
–9.0
Rx PROGRAMMABLE VOLUME LEVEL SETTINGRx PROGRAMMABLE GAIN CONTROL SETTING
Figure 77. R x Audio Maximum Output Voltage versus Gain Control Setting
Figure 78. R x Audio Maximum Output Voltage versus Volume Setting
–4.0
–8.0
–10
–12
–16
–20–7.0 –5.0 –3.0 –1.0 1.0 3.0 5.0 7.0 9.0
1.4
1.2
1.0
0.8
0.6
0.4
0–14 –10 –6.0 –2.0 2.0 6.0 10 14
VCC = 3.6 VTHD = 2%
Eou
t, OU
TPU
T VO
LTAG
E LE
VEL
(dBV
)
–6.0
–14
–18 0.2
VCC = 3.6 VTHD = 2%
SA O
ut, O
UTP
UT
VOLT
AGE
LEVE
L(dB
V)
SA O
ut, O
UTP
UT
VOLT
AGE
LEVE
L (d
BV) 1.8
SA In, INPUT VOLTAGE LEVEL (dBV)
Figure 79. R x Audio Speaker Amplifier Drive
SA In, INPUT VOLTAGE LEVEL (dBV)
Figure 80. R x Audio Speaker Amplifier Distortion
No Load
130 Ω
1.4
0
25
15
5.0
000 0.80.8 1.6 2.4 2.81.6 2.4 3.23.2
620 Ω
No Load
620 Ω
1.6
1.2
1.0
0.8
0.6
0.4
0.2
20
10
0.4 1.2 2.0 2.8 0.4 1.2 2.0
130 Ω
Rx AUDIO
MC13110A/B MC13111A/B
36 MOTOROLA ANALOG IC DEVICE DATA
Transmit Audio Path
This portion of the audio path goes from “C In” to “Tx Out”.The “C In” pin will be ac–coupled. The audio transmit signalpath includes automatic level control (ALC) (also referred toas the Compressor), Tx mute, limiter, filters, and Tx gainadjust. The ALC provides “soft” limiting to the output signalswing as the input voltage slowly increases. With thistechnique the gain is slightly lowered to help reduce distortionof the audio signal. The limiter section provides hard limitingdue to rapidly changing signal levels, or transients. This isaccomplished by clipping the signal peaks. The ALC, Txmute, and limiter functions can be enabled or disabled via theMPU serial interface. The Tx gain adjust can also be remotelycontrolled to set different desired signal levels. The typicalmaximum output voltage at “Tx Out” should be approximately0 dBV @ THD = 5.0%.
Figures 82 to 86 represent the transmit audio path filterresponse. The filter response attenuation, again, is verydefinite above 3800 Hz. This is the filter cutoff frequency.Inband (audio), wideband, and ripple characteristics are alsoshown in these graphs.
The compressor transfer characteristics, shown inFigure 87, has three different slopes. A typical compressorslope can be found between –55 and –15 dBV. Here theslope is 2.0. At an input level above –15 dBV the automaticlevel control (ALC) function is activated and prevents hardclipping of the output. The slope below –55 dBV input level isone. This is where the compressor curve ends. Above 5.0dBV the output actually begins to decrease and distort. Thisis due to supply voltage limitations.
In Figure 88 the ALC function is off. Here the compressorcurve continues to increase above –15 dBV up to –4.0 dBV.
The limiter begins to clip the output signal at this level anddistortion is rapidly rising. Similarly, Figure 68 (ALC andLimiter Off) shows to compressor transfer curve extending allthe way up to the maximum output. Finally, Figure 90 through93 show the Tx Out signal versus several combinations ofALC and Limiter selected.
Figure 81 is the noise data measured for theMC13110A/13111A. This data is for 0 dB gain setting and –20dBV (100 mVrms) audio levels.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 81. T x Path Noise DataTransmit
ScramblerTransmit
Gain(dB)
Amp_Out(dBV)
Tx_Out(dBV)
off/on muted muted < –95
off –9.0 < –95 –83
off 0 < –95 –74
off 10 < –95 –64
on (MC13110A) –9.0 < –95 –82
on (MC13110A) 0 < –95 –73
on (MC13110A) 10 –< –95 –63
Mic AmpLike the Speaker Amp the Mic Amp is also an inverting
rail–to–rail operational amplifier. The noninverting inputterminal is connected to the internal VB reference. Externalresistors and capacitors are used to set the gain andfrequency response. The “Tx In” input is ac–coupled.
MC13110A/B MC13111A/B
37MOTOROLA ANALOG IC DEVICE DATA
100100
180
5.0
0.3
100
10
f, FREQUENCY (Hz)
f, FREQUENCY (Hz)
f, FREQUENCY (Hz)
f, FREQUENCY (Hz)
Figure 82. T x Audio Wideband Frequency Response Figure 83. T x Audio Inband Frequency Response
Figure 84. T x Audio Ripple Response Figure 85. T x Audio Inband Phase Response
–10
–30
–50
–70
–100
0.1
–0.1
–0.3
–0.6
–0.7
–5.0
–15
–25
–35
–55
135
45
–45
–135
–180
100
1000
1000 10000 1000
1000
100000 10000
10000
1000000
10000
C In to Tx OutVin = –10 dBV
C In to Tx OutVin = –10 dBV
C In to Tx OutVin = –10 dBV
–90–45
0.2
0
–0.2
–0.4
–0.5 C In to Tx OutVin = –10 dBV
°PH
ASE
( )
90
0
–90
VOLT
AGE
GAI
N (d
B)V
,ga
in
VOLT
AGE
GAI
N (d
B)V
,ga
in
VOLT
AGE
GAI
N (d
B)V
,ga
in
0
–20
–40
–60
–80
Tx AUDIO
Out
, OU
TPU
T VO
LTAG
E LE
VEL
(dBV
)
–60
0
100
10
C In, INPUT VOLTAGE LEVEL (dBV)
GR
OU
P D
ELAY
(ms)
Figure 86. T x Audio Inband Group Delay
f, FREQUENCY (Hz)
Figure 87. T x Audio Compressor Response
Compressor
–101.0
–20
0
–25
–35
–40101000 10000
C In to Tx OutVin = –10 dBV
T x
0.1 Distortion
ALC On,Limiter On or Off
–5.0
–15
–30
–50 –40 –30 –20 –10 0
DIS
TORT
ION
(%)
4.0
2.0
0
3.0
1.0
MC13110A/B MC13111A/B
38 MOTOROLA ANALOG IC DEVICE DATA
–9.0
OU
TPU
T LE
VEL
(mV)
t, TIME (µs)
t, TIME (µs)
t, TIME (µs)
Tx PROGRAMMABLE GAIN CONTROL SETTING
A–4.0
–12
–16
–20
Out
, OU
TPU
T VO
LTAG
E LE
VEL
(dBV
)T x
B
C
–8.0
–7.0 –5.0 –3.0 –1.0 1.0 3.0 5.0 7.0 9.0
A: ALC Off, Limiter OffB: ALC Off, Limiter OnC: ALC On, Limiter On or Off
VCC = 3.6 V
OU
TPU
T LE
VEL
(mV)
OU
TPU
T LE
VEL
(mV)
Limiter and ALC Off
Limiter On and ALC Off Limiter On and ALC On
0
200 mV/Div500 µs/Div
200 mV/Div500 µs/Div
200 mV/Div500 µs/Div
Out
, OU
TPU
T VO
LTAG
E LE
VEL
(dBV
)T x O
ut, O
UTP
UT
VOLT
AGE
LEVE
L (d
BV)
T x
DIS
TORT
ION
(%)
4.0
2.0
0
3.0
1.0
DIS
TORT
ION
(%)
4.0
2.0
0
3.0
1.0
0
–60
0
C In, INPUT VOLTAGE LEVEL (dBV)C In, INPUT VOLTAGE LEVEL (dBV)
–5.0
–40
–10
–15
–20
–30
–40–50–50 –40 –30 –20 –10 0 10 –40 –30 –10 0–20
ALC Off,Limiter On
Distortion
ALC Off,Limiter Off
10–60
–25
–35
–5.0
–10
–15
–20
–25
–30
–35
Compressor TransferCompressor Transfer
Distortion
Figure 88. T x Audio Compressor Response Figure 89. T x Audio Compressor Response
Figure 90. T x Audio Maximum Output Voltageversus Gain Control Setting Figure 91. T x Output Audio Response
Figure 92. T x Output Audio Response Figure 93. T x Audio Output Response
Tx AUDIO
MC13110A/B MC13111A/B
39MOTOROLA ANALOG IC DEVICE DATA
PLL SYNTHESIZER SECTION
PLL Frequency Synthesizer General DescriptionFigure 95 shows a simplified block diagram of the
programmable universal dual phase locked loop (PLL)designed into the MC13110A/B and MC13111A/B IC. Thisdual PLL is fully programmable through the MCU serialinterface and supports most country channel frequenciesincluding USA (25 ch), Spain, Australia, Korea, New Zealand,U.K., Netherlands, France, and China (see channel frequencytables in AN1575, “Worldwide Cordless TelephoneFrequencies”).
The 2nd local oscillator and reference divider provide thereference frequency signal for the Rx and Tx PLL loops. Theprogrammed divider value for the reference divider isselected based on the crystal frequency and the desired Rxand Tx reference frequency values. For the U.K., additionaldivide by 25 and divide by 4 blocks are provided to allow forgeneration of the 1.0 kHz and 6.2 kHz reference frequencies.
The 14–bit Rx counter is programmed for the desired firstlocal oscillator frequency. The 14–bit Tx counter isprogrammed for the desired transmit channel frequency. Allcounters power–up to a set default state for USA channel #21using a 10.24 MHz reference frequency crystal (see power–updefault latch register state in the Serial ProgrammableInterface section).
To extend the sensitivity of the 1st LO for U.S. 25 channeloperation, internal fixed capacitors can be connected to thetank circuit through microprocessor programmable control.When designing the external PLL loop filters, it isrecommended that the Tx and Rx phase detectors beconsidered as current drive type outputs. The loop filtercontrol voltage must be 0.5 V away from either the positive ornegative supply rail.
PLL I/O Pin ConfigurationsThe 2nd LO, Rx and Tx PLL’s, and MPU serial interface are
powered by the internal voltage regulator at the “PLL Vref” pin.The “PLL Vref” pin is the output of a voltage regulator which ispowered from the “VCC Audio” power supply pin. It is regulatedby an internal bandgap voltage reference. Therefore, themaximum input and output levels for most of the PLL I/O pins(LO2 In, LO2 Out, Rx PD, Tx PD, Tx VCO) is the regulatedvoltage at the “PLL Vref” pin. The ESD protection diodes onthese pins are also connected to “PLL Vref”.
Internal level shift buffers are provided for the pins (Data,Clk, EN, Clk Out) which connect directly to the
microprocessor. The maximum input and output levels forthese pins is VCC. Figure 94 shows a simplified schematic ofthe I/O pins.
Figure 94. PLL I/O Pin Simplified Schematics
PLL Vref(2.5 V)
InI/O
VCC Audio(2.7 to 5.5 V)
PLL Vref(2.5 V)
VCC Audio(2.7 to 5.5 V)
Clk Out PinData, Clk and EN PinsLO2 In, LO2 Out, Rx PD, Tx PD and
Tx VCO Pins
Out
2.0 µA
PLL Loop Control Voltage RangeThe control voltage for the Tx and Rx loop filters is set by
the phase detector outputs which drive the external loopfilters. The phase detectors are best considered to have acurrent mode type output. The output can have three states;ground, high impedance, and positive supply, which in thiscase is the voltage at “PLL Vref”. When the loop is locked thephase detector outputs are at high impedance. An exceptionof this state is for narrow current pulses, referenced to eitherthe positive or negative supply rails. If the loop voltages getwithin 0.5 V of either rail the linear current output starts todegrade. The phase detector current source was notdesigned to operate at the supply rails. VCO tuning range willalso be limited by this voltage range
The maximum loop control voltage is the “PLL Vref” voltagewhich is 2.5 V. If a higher loop control voltage range isdesired, the “PLL Vref” pin can be pulled to a higher voltage.It can be tied directly to the VCC voltage (with suitable filtercapacitors connected close to each pin). When this is done,the internal voltage regulator is automatically disabled. Thisis commonly used in the telephone base set where anexternal 5.0 V regulated voltage is available. It is important toremember, that if “PLL Vref” is tied to VCC and VCC is not aregulated voltage, the PLL loop parameters and lock–up timewill vary with supply voltage variation. The phase detectorgain constant, Kpd, will not be affected if the “PLL Vref” is tiedto VCC.
Figure 95. Dual PLL Simplified Block Diagram
14–b ProgrammableRx Counter
14–b ProgrammableTx Counter
12–b Programmable
ReferenceCounter
÷ 25
÷1
÷ 4
LO2 In
LO2 Out1
2
Tx PD
8
6
Tx VCO
Rx PD
4
LO1 In
40LO1 Out
41
Tx PhaseDetector(CurrentOutput)
Rx PhaseDetector(CurrentOutput)
LP Loop Filter
Tx Ref
Rx Ref
U.K. Base
U.K. Handset
U.K. Handset
U.K. Base
Vcap Ctrl
42
1st LO
LP Loop Filter
TxVCO
ProgrammableInternal Capacitor
MC13110A/B MC13111A/B
40 MOTOROLA ANALOG IC DEVICE DATA
Loop Filter Characteristics
Lets consider the following discussion on loop filters. Thefundamental loop characteristics, such as capture range,loop bandwidth, lock–up time, and transient response arecontrolled externally by loop filtering.
Figure 96 is the general model for a Phase Lock Loop(PLL).
PhaseDetector (Kpd)
Filter(Kf)
VCO(Ko) fo
Divider(Kn)
fi
Figure 96. PLL Model
Where:Kpd = Phase Detector Gain ConstantKf = Loop Filter Transfer FunctionKo = VCO Gain ConstantKn = Divide Ratio (1/N)fi = Input frequencyfo = Output frequencyfo/N = Feedback frequency divided by N
From control theory the loop transfer function can berepresented as follows:
A = Kpd Kf Ko Kn Open loop gain
Kpd can be either expressed as being 2.5 V/4.0 π or1.0 mA/2.0 π for the CT–0 circuits. More details aboutperformance of different type PLL loops, refer to Motorolaapplication note AN535.
The loop filter can take the form of a simple low pass filter.A current output, type 2 filter will be used in this discussionsince it has the advantage of improved step response,velocity, and acceleration.
The type 2 low pass filter discussed here is represented asfollows:
FromPhaseDetector
To VCO
R2
C2C1
Figure 97. Loop Filterwith Additional Integrating Element
From Figure 97, capacitor C1 forms an additionalintegrator, providing the type 2 response, and filters thediscrete current steps from the phase detector output. Thefunction of the additional components R2 and C2 is to createa pole and a zero (together with C1) around the 0 dB point ofthe open loop gain. This will create sufficient phase marginfor stable loop operation.
In Figure 98, the open loop gain and the phase isdisplayed in the form of a Bode plot. Since there are twointegrating functions in the loop, originating from the loopfilterand the VCO gain, the open loop gain response follows a
second order slope (–40 dB/dec) creating a phase of –180degrees at the lower and higher frequencies. The filtercharacteristic needs to be determined such that it is adding apole and a zero around the 0 dB point to guarantee sufficientphase margin in this design (Qp in Figure 98).
Phase
Figure 98. Bode Plot of Gain andPhase in Open Loop Condition
A, O
pen
Loop
Gai
n
wp
Open Loop Gain
Qp
–180
–90
0
0
The open loop gain including the filter response can beexpressed as:
Aopenloop KpdKo(1 jw(R2C2))
jwKnjw1 jwR2C1C2C1C2
(1)
The two time constants creating the pole and the zero inthe Bode plot can now be defined as:
T1 R2C1C2C1 C2
T2 R2C2 (2)
By substituting equation (2) into (1), it follows:
Aopenloop KpdKoT1
w2C1KnT21 jwT2
1 jwT1 (3)
The phase margin (phase + 180) is thus determined by:
Qp arctan(wT2)–arctan(wT1) (4)
At w=wp, the derivative of the phase margin may be set tozero in order to assure maximum phase margin occurs at wp(see also Figure 98). This provides an expression for wp:
dQpdw
0 T2
1 (wT2)2– T1
1 (wT1)2(5)
w wp 1
T2T1 (6)
Or rewritten:
T1 1wp
2T2 (7)
MC13110A/B MC13111A/B
41MOTOROLA ANALOG IC DEVICE DATA
By substituting into equation (4), solve for T2:
T2
tanQp2
4
wp(8)
By choosing a value for wp and Qp, T1 and T2 can becalculated. The choice of Qp determines the stability of theloop. In general, choosing a phase margin of 45 degrees is agood choice to start calculations. Choosing lower phasemargins will provide somewhat faster lock–times, but alsogenerate higher overshoots on the control line to the VCO.This will present a less stable system. Larger values of phasemargin provide a more stable system, but also increaselock–times. The practical range for phase margin is 30degrees up to 70 degrees.
The selection of wp is strongly related to the desiredlock–time. Since it is quite complicated to accuratelycalculate lock time, a good first order approach is:
T_lock 3wp
(9)
Equation (9) only provides an order of magnitude for locktime. It does not clearly define what the exact frequencydifference is from the desired frequency and it does not showthe effect of phase margin. It assumes, however, that thephase detector steps up to the desired control voltagewithout hesitation. In practice, such step response approachis not really valid. The two input frequencies are not locked.Their phase maybe momentarily zero and force the phasedetector into a high impedance mode. Hence, the lock timesmay be found to be somewhat higher.
In general, wp should be chosen far below the referencefrequency in order for the filter to provide sufficientattenuation at that frequency. In some applications, thereference frequency might represent the spacing betweenchannels. Any feedthrough to the VCO that shows up as aspur might affect adjacent channel rejection. In theory, withthe loop in lock, there is no signal coming from the phasedetector. But in practice leakage currents will be supplied toboth the VCO and the phase detector. The externalcapacitors may show some leakage, too. Hence, the lowerwp, the better the reference frequency is filtered, but thelonger it takes for the loop to lock.
As shown in Figure 98, the open loop gain at wp is 1 (or0 dB), and thus the absolute value of the complex open loopgain as shown in equation (3) solves C1:
C1 KpdKoT1
w2KnT2 1 wpT2
2
1 wpT12 (10)
With C1 known, and equation (2) solve C2 and R2:
C2 C1T2T1
1 (11)
R2 T2C2
(12)
The VCO gain is dependent on the selection of theexternal inductor and the frequency required. The freerunning frequency of the VCO is determined by:
f 12 LCT (13)
In which L represents the external inductor value and CTrepresents the total capacitance (including internalcapacitance) in parallel with the inductor. The VCO gain canbe easily calculated via the internal varicap transfer curveshown below.
Figure 99. Varicap Capacitanceversus Control Voltage
0
15
, CAP
ACIT
ANC
E (p
F)
14
12
13
11
10
9.0
8.0
7.00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
V cap
As can be derived from Figure 99, the varicap capacitancechanges 1.3 pF over the voltage range from 1.0 V to 2.0 V:
Cvar 1.3 pF
V(14)
Combining (13) with (14) the VCO gain can be determinedby:
Ko 1jw
1
2 LCTCvar
2 1
2 LCTCvar2
(15)
Although the basic loopfilter previously described providesadequate performance for most applications, an extra polemay be added for additional reference frequency filtering.Given that the channel spacing in a CT–0 telephone set isbased on the reference frequency, and any feedthrough to
MC13110A/B MC13111A/B
42 MOTOROLA ANALOG IC DEVICE DATA
the first LO may effect parameters like adjacent channelrejection and intermodulation. Figure 100 shows a loopfilterarchitecture incorporating an additional pole.
FromPhaseDetector
To VCO
R2
C2C1
Figure 100. Loop Filterwith Additional Integrating Element
C3
R3
For the additional pole formed by R3 and C3 to be efficient,the cut–off frequency must be much lower than the referencefrequency. However, it must also be higher than wp in ordernot to compromise phase margin too much. The followingequations were derived in a similar manner as for the basicfilter previously described.
Similarly, it can be shown:
Aopenloop –KpdKo
Knw2(C1 C2 C3) – w2C1C2C3R2R3
1 jwT21 jwT1 (16)
In which:
T1 (C1 C2)T2 (C1C2)T3
C1 C2 C3 w2C1T2T3(17)
T2 R2C2 T3 R3C3 (19)(18)
From T1 it can be derived that:
C2 (T1 T2)C3 C1T2 T3 T1 w2T1T2T3
T3 T1 (20)
In analogy with (10), by forcing the loopgain to 1 (0 dB) atwp, we obtain:
C1(T1 T2) C2T3 C3T2 KpdKo
Knwp2 1 wpT2
2
1 wpT12 (21)
Solving for C1:
C1
(T2 T1)T3C3 (T3 T1)T2C3 (T3 T1)KpdKoT1
wp2Kn 1wpT2
2
1wpT12
(T3 T1)T2 (T3 T1)T3 T2 T3 T1 wp2T1T2T3T3
(22)
By selecting wp via (9), the additional time constantexpressed as T3, can be set to:
T3 1Kwp
(23)
MC13110A/B MC13111A/B
43MOTOROLA ANALOG IC DEVICE DATA
The K–factor shown determines how far the additionalpole frequency will be separated from wp. Selecting too smallof a K–factor, the equations may provide negativecapacitance or resistor values. Too large of a K–factor maynot provide the maximum attenuation.
By selecting R3 to be 100 kΩ, C3 becomes known and C1and C2 can be solved from the equations. By using equations(8) and (7), time constants T2 and T1 can be derived byselecting a phase margin. Finally, R2 follows from T2 and C2.
The following pages, the loopfilter components aredetermined for both handset and baseset the US applicationbased on the equations described. Choose K to beapproximately five times wp (5.0wp).
In an application, wp is chosen to be 20 times less than thereference frequency of 5.0 kHz and the phase margin has
been set to 45 degrees. This provides a lock time accordingto (9) of about 2.0 ms (order of magnitude). With the adjacentchannels spaced at least 15 kHz away, referencefeedthrough at wp will not be directly disastrous but still, theadditional pole may be added in the loopfilter design foradded safety.
In an application, wp is chosen to be 20 times less than thereference frequency of 5.0 kHz and the phase margin hasbeen set to 45 degrees. This provides a lock time accordingto (9) of about 2.0 ms (order of magnitude). With the adjacentchannels spaced at least 15 kHz away, referencefeedthrough at wp will not be directly disastrous but still, theadditional pole may be added in the loopfilter design foradded safety.
Ope
n Lo
op G
ain
(dB)
Figure 101. Open Loop Response Handset USwith Selected Values
f, FREQUENCY (Hz)
PhaseMargin
100 1000 10000 100000 1000000–80
–40
0
40
80
0
20
40
60
80
Phas
e M
argi
n (d
egre
es)
LoopGain
FromPhaseDetector
To VCO
22 k
.0686800 1000
100 k
Figure 102. Open Loop Response Baseset USwith Selected Values
Microprocessor Serial InterfaceThe Data, Clock, and Enable (“Data”, “Clk”, and “EN”
respectively) pins provide a MPU serial interface forprogramming the reference counters, the transmit andreceive channel divide counters, the switched capacitor filterclock counter, and various other control functions. The “Data”and “Clk” pins are used to load data into the MC13111A/Bshift register (Figure 109). Figure 105 shows the timingrequired on the “Data” and “Clk” pins. Data is clocked into theshift register on positive clock transitions.
Figure 105. Data and Clock Timing Requirement
Data,Clk, EN
Data
Clk
tsuDC
tr tf
50%
50%
th
10%
90%
After data is loaded into the shift register, the data islatched into the appropriate latch register using the “EN” pin.This is done in two steps. First, an 8–bit address is loadedinto the shift register and latched into the 8–bit address latchregister. Then, up to 16–bits of data is loaded into the shiftregister and latched into the data latch register. It is specifiedby the address that was previously loaded. Figure 106 showsthe timing required on the EN pin. Latching occurs on thenegative EN transition.
Figure 106. Enable Timing Requirement
Clk
EN
tsuEC
50%
50% 50%
trec
Previous Data Latched
LastClock
FirstClock
50%
The state of the “EN” pin when clocking data into the shiftregister determines whether the data is latched into theaddress register or a data register. Figure 107 shows theaddress and data programming diagrams. In the dataprogramming mode, there must not be any clock transitionswhen “EN” is high. The clock can be in a high state (defaulthigh) or a low state (default low) but must not have anytransitions during the “EN” high state. The convention inthese figures is that latch bits to the left are loaded into theshift register first. A minimum of four “Clk” rising edgetransition must occur before a negative “EN” transition willlatch data or an address into a register.
The MPU serial interface is fully operational within 100 µsafter the power supply has reached its minimum level duringpower–up (see Figure 108). The MPU Interface shiftregisters and data latches are operational in all four powersaving modes; Inactive, Standby, Rx, and Active Modes.Data can be loaded into the shift registers and latched intothe latch registers in any of the operating modes.
Data RegistersFigure 109 shows the data latch registers and addresses
which are used to select each of each registers. Latch bits tothe left (MSB) are loaded into the shift register first. The LSBbit must always be the last bit loaded into the shift register.Bits proceeding the register must be “0’s” as shown.
Power–Up Defaults for Data RegistersWhen the IC is first powered up, all latch registers are
initialized to a defined state. The device is initially placed in the
Rx mode with all mutes active. The reference counter is set togenerate a 5.0 kHz reference frequency from a 10.24 MHzcrystal. The switched capacitor filter clock counter is setproperly for operation with a 10.24 MHz crystal. The Tx and Rxcounter registers are set for USA handset channel frequency,number 21 (Channel 6 for previous FCC 10 Channel Band).Figure 110 shows the initial power–up states for all latchregisters.
6. (00000110)
SCF Clock Dividers Latch (MC13111A/B only)
06–b Switched
Capacitor FilterClock Counter Latch
4–b VoltageReference Adjust MSB LSBMSB LSB
3–b Low BatteryDetect Threshold Select 0 0
Figure 109. Microprocessor Interface Data Latch Registers
14–b Tx CounterMSB LSB 1. (00000001)
2. (00000010)
3. (00000011)
4. (00000100)
5. (00000101)
6. (00000110)
Latch Address
Tx Counter Latch
Rx Counter Latch
Reference Counter Latch
Mode Control Latch
Gain Control Latch
SCF Clock Dividers Latch (MC13110A/B only)
12–b Reference CounterMSB LSBU.K.BS
Select
StdbyMode4–b Vol Control
RxMode
TxMute
Rx Mute
SP Mute
5–b Tx Gain Control 5–b Rx Gain Control 5–b CD Threshold Control
U.K.HS
Select
0ALC
DisableMPUClk 2
LimiterDisable
ClkDisable
00
0
0
06–b Switched
Capacitor FilterClock Counter Latch
4–b VoltageReference Adjust MSB LSBMSB LSB
MSB LSB MSB LSB MSB LSB
MSB LSB
0
MPUClk 1
MPUClk 0
3–b Low BatteryDetect Threshold Select
14–b Rx CounterMSB LSB0IP3
Increase
Tx SblBypass
7. (00000111)
Auxillary Latch
0 0 0 0 0 0 0 0 0 3–b Test Mode 4–b 1st LO Capacitor Selection
NOTE: 12. Bits 6 and 7 in the SCF latch register are ”Don’t Cares” for the MC13111A/B since this part does not have a scrambler.
Tx and Rx Counter RegistersThe 14 bit Tx and Rx counter registers are used to select
the transmit and receive channel frequencies. In the Rxcounter there is an “IP3 Increase” bit that allows the ability totrade off increased receiver mixer performance versusreduced power consumption. With “IP3 increase” = <1>,there is about a 10 dB improvement in 1 dB compression and3rd order intercept for both the 1st and 2nd mixers. However,there is also an increase in power supply current of 1.3 mA.The power–up default for the MC13111A/B is “IP3 Increase”= <0>. The register bits are shown in Figure 111.
Reference Counter RegisterReference Counter
Figure 113 shows how the reference frequencies for theRx and Tx loops are generated. All countries except the U.K.require that the Tx and Rx reference frequencies be identical.
In this case, set “U.K. Base Select” and “U.K. HandsetSelect” bits to “0”. Then the fixed divider is set to “1” and theTx and Rx reference frequencies will be equal to the crystaloscillator frequency divided by the programmable referencecounter value.
The U.K. is a special case which requires a differentreference frequency value for Tx and Rx. For U.K. baseoperation, set “U.K. Base Select” to “1”. For U.K. handsetoperation, set “U.K. Handset Select” to “1”. The Netherlandsis also a special case. A 2.5 kHz reference frequency is usedfor both the Tx and Rx reference and the total divider valuerequired is 4096. This is larger than the maximum dividevalue available from the 12–bit reference divider (4095). Inthis case, set “U.K. Base Select” to “1” and set “U.K. HandsetSelect” to “1”. This will give a fixed divide by 4 for both the Txand Rx reference. Then set the reference divider to 1024 toget a total divider of 4096.
Figure 111. R x and Tx Counter Register Latch Bits
Reference Frequency SelectionThe “LO2 In” and “LO2 Out” pins form a reference oscillator
when connected to an external parallel–resonant crystal. Thereference oscillator is also the second local oscillator for theRF Receiver. Figure 114 shows the relationship betweendifferent crystal frequencies and reference frequencies forcordless phone applications in various countries. “LO2 In”may also serve as an input for an externally generatedreference signal which is ac–coupled. The switchedcapacitor filter 6–bit programmable counter must beprogrammed for the crystal frequency that is selected sincethis clock is derived from the crystal frequency and must beheld constant regardless of the crystal that is selected. Theactual switched capacitor clock divider ratio is twice theprogrammed divider ratio due to the a fixed divide by 2.0 afterthe programmable counter. The scrambler mixer modulationfrequency is the switched capacitor clock divided by 40 forthe MC13110A/B.
Mode Control RegisterThe power saving modes; mutes, disables, volume
control, and microprocessor clock output frequency are all
set by the Mode Control Register. Operation of the ControlRegister is explained in Figures 115 through 119.ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 116. Mute and Disable Control Bit Descriptions
ÁÁÁÁÁÁÁÁÁÁÁÁ
ALC Disable ÁÁÁÁ
10ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Automatic Level Control DisabledNormal Operation
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Tx Limiter DisableÁÁÁÁÁÁ
10
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Tx Limiter DisabledNormal Operation
ÁÁÁÁÁÁÁÁÁÁÁÁ
Clock Disable(MC13110A/111A)
ÁÁÁÁ
10ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
MPU Clock Output DisabledNormal OperationÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
Clock Disable(MC13110B/111B)
ÁÁÁÁÁÁ
10
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Don’t CareNormal Operation
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Tx Mute ÁÁÁÁÁÁ
10
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Transmit Channel MutedNormal Operation
ÁÁÁÁÁÁÁÁÁÁÁÁ
Rx Mute ÁÁÁÁ
10ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Receive Channel MutedNormal Operation
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
SP MuteÁÁÁÁÁÁ
10
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Speaker Amp MutedNormal Operation
MC13110A/B MC13111A/B
48 MOTOROLA ANALOG IC DEVICE DATA
Power Saving Operating ModesWhen the MC13110A/B or MC13111A/B are used in a
handset, it is important to conserve power in order to prolongbattery life. There are five modes of operation for theMC13110A/MC13111A; Active, Rx, Standby, Interrupt, andInactive. The MC13110B/MC13111B has three modes ofoperation. They are Active, Rx, and Standby. In the Activemode, all circuit blocks are powered. In the Rx mode, allcircuitry is powered down except for those circuit sectionsneeded to receive a transmission from the base. In theStandby and Interrupt Modes, all circuitry is powered downexcept for the circuitry needed to provide the clock output forthe microprocessor. In the Inactive Mode, all circuitry ispowered down except the MPU serial interface. Latchmemory is maintained in all modes. All mode functions arethe same for the MC13110B/MC13111B, except that there isno Inactive mode. With the B” version the MPU Clock isalways running so that there can never be a register reset ifthe memory is disturbed. Figure 118 shows the controlregister bit values for selection of each power saving modeand Figure 118 shows the circuit blocks which are powered ineach of these operating modes.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 117. Power Saving Mode Selection
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Stdby Mode Bit
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Rx Mode Bit
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
“CD Out/Hardware
Interrupt” Pin
ÁÁÁÁÁÁÁÁÁÁÁÁ
PowerSavingMode
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
MC13110A/MC13111A
ÁÁÁÁÁÁÁÁÁÁÁÁ
0 ÁÁÁÁÁÁÁÁÁÁ
0 ÁÁÁÁÁÁÁÁÁÁ
X ÁÁÁÁÁÁÁÁ
Active
ÁÁÁÁÁÁÁÁÁÁÁÁ
0 ÁÁÁÁÁÁÁÁÁÁ
1 ÁÁÁÁÁÁÁÁÁÁ
X ÁÁÁÁÁÁÁÁ
RxÁÁÁÁÁÁÁÁÁÁÁÁ
1 ÁÁÁÁÁÁÁÁÁÁ
0 ÁÁÁÁÁÁÁÁÁÁ
X ÁÁÁÁÁÁÁÁ
Standby
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
1 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
1 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
1 or HighImpedance
ÁÁÁÁÁÁÁÁÁÁÁÁ
Inactive
ÁÁÁÁÁÁÁÁÁÁÁÁ
1 ÁÁÁÁÁÁÁÁÁÁ
1 ÁÁÁÁÁÁÁÁÁÁ
0 ÁÁÁÁÁÁÁÁ
Interrupt
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
MC13110B/MC13111B [Note 14]
ÁÁÁÁÁÁÁÁÁÁÁÁ
0 ÁÁÁÁÁÁÁÁÁÁ
0 ÁÁÁÁÁÁÁÁÁÁ
X ÁÁÁÁÁÁÁÁ
Active
ÁÁÁÁÁÁÁÁÁÁÁÁ
0 ÁÁÁÁÁÁÁÁÁÁ
1 ÁÁÁÁÁÁÁÁÁÁ
X ÁÁÁÁÁÁÁÁ
Rx
ÁÁÁÁÁÁÁÁÁÁÁÁ
1 ÁÁÁÁÁÁÁÁÁÁ
X ÁÁÁÁÁÁÁÁÁÁ
X ÁÁÁÁÁÁÁÁ
Standby
ÁÁÁÁÁÁÁÁÁÁÁÁ
1 ÁÁÁÁÁÁÁÁÁÁ
1 ÁÁÁÁÁÁÁÁÁÁ
0 ÁÁÁÁÁÁÁÁ
Interrupt
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
NOTES: 13. “X” is a don’t care14. MPU Clock Out is ”Always On”
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 118. Circuit Blocks PoweredDuring Power Saving Modes
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Ci i Bl k
MC13110A/MC13111A
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁCi i Bl k
MC13110B/MC13111B
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Circuit Blocks ÁÁÁÁÁÁ
ActiveÁÁÁÁÁÁ
RxÁÁÁÁÁÁÁÁ
Standby ÁÁÁÁÁÁ
Inactive
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
“PLL Vref” Regulated Voltage
ÁÁÁÁÁÁ
XÁÁÁÁÁÁ
XÁÁÁÁÁÁÁÁ
X1 ÁÁÁÁÁÁ
X1, 2
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
MPU Serial InterfaceÁÁÁÁÁÁ
XÁÁÁÁÁÁ
XÁÁÁÁÁÁÁÁ
XÁÁÁÁÁÁ
X2ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
2nd LO OscillatorÁÁÁÁÁÁ
XÁÁÁÁÁÁ
XÁÁÁÁÁÁÁÁ
XÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁMPU Clock Output ÁÁÁ
ÁÁÁXÁÁÁÁÁÁ
XÁÁÁÁÁÁÁÁ
X ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁRF Receiver and 1st LO VCO
ÁÁÁÁÁÁ
XÁÁÁÁÁÁ
XÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁRx PLLÁÁÁÁÁÁXÁÁÁÁÁÁXÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁCarrier Detect
ÁÁÁÁÁÁ
XÁÁÁÁÁÁ
XÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁData Amp ÁÁÁ
ÁÁÁXÁÁÁÁÁÁ
XÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁLow Battery Detect ÁÁÁ
ÁÁÁXÁÁÁÁÁÁ
XÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁTx PLL ÁÁÁ
ÁÁÁXÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁRx and Tx Audio PathsÁÁÁXÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
NOTES: 15. In Standby and Inactive Modes, “PLL Vref” remains poweredbut is not regulated. It will fluctuate with VCC.
16. There is no Inactive mode for MC13110B/MC13111B.
Power Saving Application – Option 1 (MC13110B andMC13111B Only)
When the handset is in standby, power can be reduced byentering a “low power” mode and periodically switching to“sniff” mode to check for incoming calls. Figure 119. showsan application where the “Clk Out” pin provides the clock forthe MPU. In this application, the 2nd LO and MPU clock runcontinuously. The MPU maintains control at all times and setsthe timing for transitions into the “sniff” mode. Power is savedin the low power mode by putting the MC13110B/MC13111Binto its “Standby” mode. Only the 2nd LO and MPU clockdivider are active. By programming the MPU clock divider toa large divide value of 20, 80, or 312.5 this will reduce theMPU clock frequency and save power in the MPU.
MC13110A/B MC13111A/B
49MOTOROLA ANALOG IC DEVICE DATA
Power Saving Application – Option 2 (MC13110A andMC13111A Only)
In some handset applications it may be desirable to powerdown all circuitry including the microprocessor (MPU). Firstput the MC13110A/MC13111A into the Inactive mode. Thisturns off the MPU Clock Output (see Figure 120) anddisables the microprocessor. Once a command is given toswitch the IC into an “Inactive” mode, the MPU Clock outputwill remain active for a minimum of one reference countercycle (about 200 µs) and up to a maximum of two referencecounter cycles (about 400 µs). This is performed in order togive the MPU adequate time to power down.
An external timing circuit should be used to initiate theturn–on sequence. The “CD Out” pin has a dual function. Inthe Active and Rx modes it performs the carrier detectfunction. In the Standby and Inactive modes the carrierdetect circuit is disabled and the “CD Out” pin is in a “High”state, because of an external pull–up resistor. In the Inactivemode, the “CD Out” pin is the input for the hardware interruptfunction. When the “CD Out” pin is pulled “low”, by theexternal timing circuit, the IC switches from the Inactive to theInterrupt mode. Thereby turning on the MPU Clock Output.The MPU can then resume control of the IC. The “CD Out”pin must remain low until the MPU changes the operatingmode from Interrupt to Standby, Active, or Rx modes.
Figure 119. Power Saving Application – Option 1
Timer
MPU ClkDivider
Clk In
SPI Port
Clk Out
SPI Port
LO2 Out
LO2 In
MC13110BMC13111B Microprocessor
Mode
MPU Timer
MPUClock
Out
“Low Power” “Sniff”
Standby Mode Rx Mode
32.8, 128 or 512 kHz 4.0 MHz
MC13110A/B MC13111A/B
50 MOTOROLA ANALOG IC DEVICE DATA
Figure 120. Power Saving Application – Option 2 (MC13110A/MC13111A Only)
MPU ClkDivider
Clk In
SPI Port
Clk Out
SPI Port
LO2 Out
LO2 In
MC13110A/MC13111A
Microprocessor
CD Out/HW Interrupt
Interrupt
External Timer
VCC
Mode
EN
CD Out/Hardware Interrupt
MPU Clock Out
CD Out Low
Delay after MPU selects Inactive Mode to when CD turns off.
CD Turns Off
External TimerPulls Pin Low
MPU InitiatesMode Change
Timer OutputDisabled
MPU InitiatesInactive Mode
“MPU Clock Out” remains active for a minimum of one count of referencecounter after “CD Out/Hardware Interrupt” pin goes high
Active/Rx Inactive Interrupt Standby/Rx/Active
MPU “Clk Out” Divider ProgrammingThe “Clk Out” signal is derived from the second local
oscillator. It can be used to drive a microprocessor (MPU) clockinput. This will eliminate the need for a separate crystal to drivethe MPU, thus reducing system cost. Figure 121 shows therelationship between the second LO crystal frequency and the
clock output for each divide value. Figure 122 shows the “ClkOut” register bit values. With a 10.24 MHz crystal, the divide by312.5 gives the same clock frequency as a clock crystal andallows the MPU to display the time on a LCD display withoutadditional external components.
MPU “Clk Out” Power–Up Default Divider ValueThe power–up default divider value is “divide by 5”. This
provides a MPU clock of about 2.0 MHz after initialpower–up. The reason for choosing a relatively low clockfrequency at in i t ia l power–up is because somemicroprocessors operate using a 3.0 V power supply andhave a maximum clock frequency of 2.0 MHz. After initialpower–up, the MPU can change the clock divider value andset the clock to the desired operating frequency. Special carewas taken in the design of the clock divider to insure that the
transition between one clock divider value and another is“smooth” (i.e. there will be no narrow clock pulses to disturbthe MPU).
MPU “Clk Out” Radiated Noise on Circuit BoardThe clock line running between the MC13110A/B or
MC13111A/B and the microprocessor has the potential toradiate noise. Problems in the system can occur, especially ifthe clock is a square wave digital signal with large highfrequency harmonics. In order to minimize the radiated noise,a 1000 Ω resistor is included on–chip in series with the “ClkOut” output driver. A small capacitor or inductor with acapacitor can be connected to the “Clk Out” line on the PCBto form a one or two pole low pass filter. This filter shouldsignificantly reduce noise radiated by attenuating the highfrequency harmonics on the signal line. The filter can also beused to attenuate the signal level so that it is only as large asrequired by the MPU clock input. To further reduce radiatednoise, the PCB signal trace length should be kept to aminimum.
Volume Control ProgrammingThe volume control adjustable gain block can be
programmed in 2 dB gain steps from –14 dB to +16 dB. Thepower–up default value for the MC13110A/B andMC13111A/B is 0 dB. (see Figure 123)
Gain Control RegisterThe gain control register contains bits which control the Tx
Voltage Gain, Rx Voltage Gain, and Carrier Detect threshold.Operation of these latch bits are explained in Figures 124,125 and 126.
Tx and Rx Gain ProgrammingThe Tx and Rx audio signal paths each have a
programmable gain block. If a Tx or Rx voltage gain, other
than the nominal power–up default, is desired, it can beprogrammed through the MPU interface. Alternately, theseprogrammable gain blocks can be used during final test of thetelephone to electronically adjust for gain tolerances in thetelephone system (see Figure 125). In this case, the Tx andRx gain register values should be stored in ROM during finaltest so that they can be reloaded each time the IC is poweredup.
Figure 124. Gain Control Latch Bits
5–b Tx Gain Control 5–b Rx Gain Control 5–b CD Threshold Control0
Carrier Detect Threshold ProgrammingThe “CD Out” pin gives an indication to the microprocessor
if a carrier signal is present on the selected channel. Thenominal value and tolerance of the carrier detect threshold isgiven in the carrier detect specification section of thisdocument. If a different carrier detect threshold value isdesired, it can be programmed through the MPU interface asshown in Figure 126 below. Alternately, the carrier detectthreshold can be electronically adjusted during final test ofthe telephone to reduce the tolerance of the carrier detect
threshold. This is done by measuring the threshold and thenby adjusting the threshold through the MPU interface. In thiscase, it is necessary to store the carrier detect register valuein ROM so that the CD register can be reloaded each time thecombo IC is powered up. If a preamp is used before the firstmixer it may be desirable to scale the carrier detect range byconnecting an external resistor from the “RSSI” pin toground. The internal resistor is 187 kΩ.
Clock Divider/Voltage Adjust RegisterThis register controls the divider value for the
programmable switched capacitor filter clock divider, the lowbattery detect threshold select, the voltage reference adjust,and the scrambler bypass mode (MC13110A/B only).Operation is explained in Figures 127 through 134. The Txand Rx Audio bits are don’t cares for either the MC13111A orthe MC13111B device. However, for the MC13110A/B, thesebits are defined. Figure 129 describes the operation. Note thepower–up default bit is set to <0>, which is the scramblerbypass mode.
Low Battery DetectThe low battery detect circuit can be operated in
programmable and non–programmable threshold modes.
The non–programmable threshold mode is only available inthe 52 QFP package. In this mode, there are two low batterydetect comparators and the threshold values are set byexternal resistor dividers which are connected to the REF1and REF2 pins. In the programmable threshold mode,several different threshold levels may be selected throughthe “Low Battery Detect Threshold Register” as shown in Figure128. The power–on default value for this register is <0,0,0> andis the non–programmable mode. Figure 130 shows equivalentschematics for the programmable and non–programmableoperating modes.
Voltage Reference AdjustmentAn internal 1.5 V bandgap voltage reference provides the
voltage reference for the “BD1 Out” and “BD2 Out” low batterydetect circuits, the “PLL Vref” voltage regulator, the “VB”reference, and all internal analog ground references. Theinitial tolerance of the bandgap voltage reference is ±6%. Thetolerance of the internal reference voltage can be improved to±1.5% through MPU serial interface programming. Duringfinal test of the telephone, the battery detect threshold ismeasured. Then, the internal reference voltage value isadjusted electronically through the MPU serial interface toachieve the desired accuracy level. The voltage referenceregister value should be stored in ROM during final test sothat it can be reloaded each time the MC13110A/B orMC13111A/B is powered up (see Figure 131).
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 131. Bandgap Voltage Reference Adjustment
ÁÁÁÁÁÁÁÁ
Vref Adj.Bit #3ÁÁÁÁÁÁ
Vref Adj.Bit #2ÁÁÁÁÁÁÁÁ
Vref Adj.Bit #1ÁÁÁÁÁÁ
Vref Adj.Bit #0ÁÁÁÁÁÁÁÁ
Vref Adj.#ÁÁÁÁÁÁÁÁ
Vref Adj.AmountÁÁÁÁ
ÁÁÁÁ0ÁÁÁÁÁÁ
0ÁÁÁÁÁÁÁÁ
0ÁÁÁÁÁÁ
0ÁÁÁÁÁÁÁÁ
0ÁÁÁÁÁÁÁÁ
–9.0%ÁÁÁÁÁÁÁÁ
0 ÁÁÁÁÁÁ
0ÁÁÁÁÁÁÁÁ
0 ÁÁÁÁÁÁ
1ÁÁÁÁÁÁÁÁ
1 ÁÁÁÁÁÁÁÁ
–7.8%ÁÁÁÁÁÁÁÁ
0 ÁÁÁÁÁÁ
0ÁÁÁÁÁÁÁÁ
1 ÁÁÁÁÁÁ
0ÁÁÁÁÁÁÁÁ
2 ÁÁÁÁÁÁÁÁ
–6.6%
ÁÁÁÁÁÁÁÁ
0 ÁÁÁÁÁÁ
0ÁÁÁÁÁÁÁÁ
1 ÁÁÁÁÁÁ
1ÁÁÁÁÁÁÁÁ
3 ÁÁÁÁÁÁÁÁ
–5.4%
ÁÁÁÁÁÁÁÁ
0 ÁÁÁÁÁÁ
1ÁÁÁÁÁÁÁÁ
0 ÁÁÁÁÁÁ
0ÁÁÁÁÁÁÁÁ
4 ÁÁÁÁÁÁÁÁ
–4.2%
ÁÁÁÁ0 ÁÁÁ1ÁÁÁÁ0 ÁÁÁ1ÁÁÁÁ5 ÁÁÁÁ–3.0%ÁÁÁÁÁÁÁÁ
0ÁÁÁÁÁÁ
1ÁÁÁÁÁÁÁÁ
1ÁÁÁÁÁÁ
0ÁÁÁÁÁÁÁÁ
6ÁÁÁÁÁÁÁÁ
–1.8%ÁÁÁÁÁÁÁÁ
0ÁÁÁÁÁÁ
1ÁÁÁÁÁÁÁÁ
1ÁÁÁÁÁÁ
1ÁÁÁÁÁÁÁÁ
7ÁÁÁÁÁÁÁÁ
–0.6%ÁÁÁÁÁÁÁÁ
1 ÁÁÁÁÁÁ
0ÁÁÁÁÁÁÁÁ
0 ÁÁÁÁÁÁ
0ÁÁÁÁÁÁÁÁ
8 ÁÁÁÁÁÁÁÁ
+0.6 %
ÁÁÁÁÁÁÁÁ
1 ÁÁÁÁÁÁ
0ÁÁÁÁÁÁÁÁ
0 ÁÁÁÁÁÁ
1ÁÁÁÁÁÁÁÁ
9 ÁÁÁÁÁÁÁÁ
+1.8 %
ÁÁÁÁÁÁÁÁ
1 ÁÁÁÁÁÁ
0ÁÁÁÁÁÁÁÁ
1 ÁÁÁÁÁÁ
0ÁÁÁÁÁÁÁÁ
10 ÁÁÁÁÁÁÁÁ
+3.0 %
ÁÁÁÁ1 ÁÁÁ0ÁÁÁÁ1 ÁÁÁ1ÁÁÁÁ11 ÁÁÁÁ+4.2 %ÁÁÁÁÁÁÁÁ1
ÁÁÁÁÁÁ1ÁÁÁÁÁÁÁÁ0
ÁÁÁÁÁÁ0ÁÁÁÁÁÁÁÁ12
ÁÁÁÁÁÁÁÁ+5.4 %ÁÁÁÁ
ÁÁÁÁ1ÁÁÁÁÁÁ
1ÁÁÁÁÁÁÁÁ
0ÁÁÁÁÁÁ
1ÁÁÁÁÁÁÁÁ
13ÁÁÁÁÁÁÁÁ
+6.6 %ÁÁÁÁÁÁÁÁ
1 ÁÁÁÁÁÁ
1ÁÁÁÁÁÁÁÁ
1 ÁÁÁÁÁÁ
0ÁÁÁÁÁÁÁÁ
14 ÁÁÁÁÁÁÁÁ
+7.8 %
ÁÁÁÁÁÁÁÁ
1 ÁÁÁÁÁÁ
1ÁÁÁÁÁÁÁÁ
1 ÁÁÁÁÁÁ
1ÁÁÁÁÁÁÁÁ
15 ÁÁÁÁÁÁÁÁ
+9.0 %
Switched Capacitor Filter Clock ProgrammingA block diagram of the switched capacitor filter clock
divider is show in Figure 132. There is a fixed divide by 2 afterthe programmable divider. The switched capacitor filter clockvalue is given by the following equation;
The scrambler modulation clock frequency (SMCF) isproportional to the SCF clock. The following equation definesits value:
SMCF = (SCF Clock)/40
The SCF divider should be set to a value which brings theSCF Clock as close to 165.16 kHz as possible. This is basedon the 2nd LO frequency which is chosen in Figure 114.
Figure 132. SCF Clock Divider Circuit
LO2 Out
6–bProgrammable
SCF Clock Counter
LO2 In
2nd LOCrystal
SCFClockDivide
By 2.0
ScramblerModulationClock
DivideBy 40
MC13110A/Bonly
Corner Frequency Programming for MC13110A/B andMC13111A/B
Four different corner frequencies may be selected byprogramming the SCF Clock divider as shown in Figures 133and 134. It is important to note, that all filter cornerfrequencies will change proportionately with the SCF ClockFrequency and Scrambler Modulation Frequency. Thepower–up default SCF Clock divider value is 31.
NOTE: 18. All filter corner frequencies have a tolerance of ±3%.19. Rx and Tx Upper Corner Frequencies are the same corner frequencies for the MC13110A/B in scrambler bypass
NOTES: 20. All filter corner frequencies have a tolerance of ±3%.21. Rx and Tx Upper Corner Frequencies are the same corner frequencies for the MC13110A/B in scrambler bypass
Figure 135. Auxiliary Register Latch Bits
4–b 1st LO CapacitorSelection3–b Test ModeMSB LSB MSB LSB000000000
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁInput Frequency/SC Counter Value * 2ÁÁÁ
ÁÁÁ5ÁÁÁÁÁÁ1ÁÁÁÁÁÁ0ÁÁÁÁÁÁ1ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁALC Gain = 10 Option
ÁÁÁÁÁÁÁÁÁÁN/A
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁN/AÁÁÁ
ÁÁÁ6ÁÁÁÁÁÁ1ÁÁÁÁÁÁ1ÁÁÁÁÁÁ0ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁALC Gain = 25 Option
ÁÁÁÁÁÁÁÁÁÁN/A
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁN/A
Auxiliary RegisterThe auxiliary register contains a 4–bit First LO Capacitor
Selection latch and a 3–bit Test Mode latch. Operation ofthese latch bits are explained in Figures 135, 136 and 137.
Test ModesTest modes are be selected through the 3–bit Test Mode
Register. In test mode, the “Tx VCO” input pin is multiplexedto the input of the counter under test. The output of thecounter under test is multiplexed to the “Clk Out” output pinso that each counter can be individually tested. Make suretest mode bits are set to “0’s” for normal operation. Testmode operation is described in Figure 136. During normaloperation, the “Tx VCO” input can be a minimum of 200 mVppat 80 MHz and should be AC coupled. Input signals should bestandard logic levels of 0 to 2.5 V and a maximum frequency of16 MHz.
First Local Oscillator Programmable Capacitor SelectionThere is a very large frequency difference between the
minimum and maximum channel frequencies in the 25Channel U.S. standard. The internal varactor adjustment
range is not large enough to accommodate this largefrequency span. An internal capacitor with 15 programmablecapacitor values can be used to cover the 25 channelfrequency span without the need to add external capacitorsand switches. The programmable internal capacitor can alsobe used to eliminate the need to use an external variablecapacitor to adjust the 1st LO center frequency duringtelephone assembly. Figure 32 shows the schematic of the1st LO tank circuit. Figure 137 shows the register control bitvalues.
The internal programmable capacitor is composed of amatrix bank of capacitors that are switched in as desired.Programmable capacitor values between about 0 and 16 pFcan be selected in steps of approximately 1.1 pF. The internalparallel resistance values in the table can be used tocalculate the quality factor (Q) of the oscillator if the Q of theexternal inductor is known. The temperature coefficient of thevaractor is 0.08%/°C. The temperature coefficient of theinternal programmable capacitor is negligible. Tolerance onthe varactor and programmable capacitor values is ±15%.
Figure 137. First Local Oscillator Internal Capacitor Selection
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
1st LOCap.Bit 3
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
1st LOCap.Bit 2
ÁÁÁÁÁÁÁÁÁÁÁÁ
1st LOCap.Bit 1
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
1st LOCap.Bit 0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
1st LOCap.
Select
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
InternalProgrammable
CapacitorValue (pF)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
VaractorValue over
0.3 to 2.5 V (pF)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
EquivalentInternalParallel
Resistanceat 40 MHz (kΩ)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
EquivalentInternalParallel
Resistanceat 51 MHz (kΩ)
ÁÁÁÁÁÁÁÁ
0 ÁÁÁÁÁÁÁÁ
0 ÁÁÁÁÁÁ
0ÁÁÁÁÁÁÁÁ
0 ÁÁÁÁÁÁÁÁ
0 ÁÁÁÁÁÁÁÁÁÁ
0.0 ÁÁÁÁÁÁÁÁÁÁÁÁ
9.7 to 5.8 ÁÁÁÁÁÁÁÁÁÁÁÁ
1200 ÁÁÁÁÁÁÁÁÁÁÁÁ
736ÁÁÁÁÁÁÁÁ
0 ÁÁÁÁÁÁÁÁ
0 ÁÁÁÁÁÁ
0ÁÁÁÁÁÁÁÁ
1 ÁÁÁÁÁÁÁÁ
1 ÁÁÁÁÁÁÁÁÁÁ
0.6 ÁÁÁÁÁÁÁÁÁÁÁÁ
9.7 to 5.8 ÁÁÁÁÁÁÁÁÁÁÁÁ
79.3 ÁÁÁÁÁÁÁÁÁÁÁÁ
48.8
ÁÁÁÁÁÁÁÁ
0 ÁÁÁÁÁÁÁÁ
0 ÁÁÁÁÁÁ
1ÁÁÁÁÁÁÁÁ
0 ÁÁÁÁÁÁÁÁ
2 ÁÁÁÁÁÁÁÁÁÁ
1.7 ÁÁÁÁÁÁÁÁÁÁÁÁ
9.7 to 5.8 ÁÁÁÁÁÁÁÁÁÁÁÁ
131 ÁÁÁÁÁÁÁÁÁÁÁÁ
80.8
ÁÁÁÁÁÁÁÁ
0 ÁÁÁÁÁÁÁÁ
0 ÁÁÁÁÁÁ
1ÁÁÁÁÁÁÁÁ
1 ÁÁÁÁÁÁÁÁ
3 ÁÁÁÁÁÁÁÁÁÁ
2.8 ÁÁÁÁÁÁÁÁÁÁÁÁ
9.7 to 5.8 ÁÁÁÁÁÁÁÁÁÁÁÁ
31.4 ÁÁÁÁÁÁÁÁÁÁÁÁ
19.3
ÁÁÁÁÁÁÁÁ
0 ÁÁÁÁÁÁÁÁ
1 ÁÁÁÁÁÁ
0ÁÁÁÁÁÁÁÁ
0 ÁÁÁÁÁÁÁÁ
4 ÁÁÁÁÁÁÁÁÁÁ
3.9 ÁÁÁÁÁÁÁÁÁÁÁÁ
9.7 to 5.8 ÁÁÁÁÁÁÁÁÁÁÁÁ
33.8 ÁÁÁÁÁÁÁÁÁÁÁÁ
20.8
ÁÁÁÁÁÁÁÁ
0 ÁÁÁÁÁÁÁÁ
1 ÁÁÁÁÁÁ
0ÁÁÁÁÁÁÁÁ
1 ÁÁÁÁÁÁÁÁ
5 ÁÁÁÁÁÁÁÁÁÁ
4.9 ÁÁÁÁÁÁÁÁÁÁÁÁ
9.7 to 5.8 ÁÁÁÁÁÁÁÁÁÁÁÁ
66.6 ÁÁÁÁÁÁÁÁÁÁÁÁ
41
ÁÁÁÁÁÁÁÁ
0 ÁÁÁÁÁÁÁÁ
1 ÁÁÁÁÁÁ
1ÁÁÁÁÁÁÁÁ
0 ÁÁÁÁÁÁÁÁ
6 ÁÁÁÁÁÁÁÁÁÁ
6.0 ÁÁÁÁÁÁÁÁÁÁÁÁ
9.7 to 5.8 ÁÁÁÁÁÁÁÁÁÁÁÁ
49.9 ÁÁÁÁÁÁÁÁÁÁÁÁ
30.7
ÁÁÁÁÁÁÁÁ
0 ÁÁÁÁÁÁÁÁ
1 ÁÁÁÁÁÁ
1ÁÁÁÁÁÁÁÁ
1 ÁÁÁÁÁÁÁÁ
7 ÁÁÁÁÁÁÁÁÁÁ
7.1 ÁÁÁÁÁÁÁÁÁÁÁÁ
9.7 to 5.8 ÁÁÁÁÁÁÁÁÁÁÁÁ
40.7 ÁÁÁÁÁÁÁÁÁÁÁÁ
25.1ÁÁÁÁÁÁÁÁ1
ÁÁÁÁÁÁÁÁ0
ÁÁÁÁÁÁ0ÁÁÁÁÁÁÁÁ0
ÁÁÁÁÁÁÁÁ8
ÁÁÁÁÁÁÁÁÁÁ8.2
ÁÁÁÁÁÁÁÁÁÁÁÁ9.7 to 5.8
ÁÁÁÁÁÁÁÁÁÁÁÁ27.1
ÁÁÁÁÁÁÁÁÁÁÁÁ16.7ÁÁÁÁ
ÁÁÁÁ1ÁÁÁÁÁÁÁÁ0
ÁÁÁÁÁÁ0ÁÁÁÁÁÁÁÁ1
ÁÁÁÁÁÁÁÁ9
ÁÁÁÁÁÁÁÁÁÁ9.4
ÁÁÁÁÁÁÁÁÁÁÁÁ9.7 to 5.8
ÁÁÁÁÁÁÁÁÁÁÁÁ21.6
ÁÁÁÁÁÁÁÁÁÁÁÁ13.3ÁÁÁÁ
ÁÁÁÁ1ÁÁÁÁÁÁÁÁ0
ÁÁÁÁÁÁ1ÁÁÁÁÁÁÁÁ0
ÁÁÁÁÁÁÁÁ10
ÁÁÁÁÁÁÁÁÁÁ10.5
ÁÁÁÁÁÁÁÁÁÁÁÁ9.7 to 5.8
ÁÁÁÁÁÁÁÁÁÁÁÁ20.5
ÁÁÁÁÁÁÁÁÁÁÁÁ12.6ÁÁÁÁ
ÁÁÁÁ1ÁÁÁÁÁÁÁÁ
0ÁÁÁÁÁÁ
1ÁÁÁÁÁÁÁÁ
1ÁÁÁÁÁÁÁÁ
11ÁÁÁÁÁÁÁÁÁÁ
11.6ÁÁÁÁÁÁÁÁÁÁÁÁ
9.7 to 5.8ÁÁÁÁÁÁÁÁÁÁÁÁ
18.6ÁÁÁÁÁÁÁÁÁÁÁÁ
11.5ÁÁÁÁÁÁÁÁ
1ÁÁÁÁÁÁÁÁ
1ÁÁÁÁÁÁ
0ÁÁÁÁÁÁÁÁ
0ÁÁÁÁÁÁÁÁ
12ÁÁÁÁÁÁÁÁÁÁ
12.7ÁÁÁÁÁÁÁÁÁÁÁÁ
9.7 to 5.8ÁÁÁÁÁÁÁÁÁÁÁÁ
17.2ÁÁÁÁÁÁÁÁÁÁÁÁ
10.6ÁÁÁÁÁÁÁÁ
1 ÁÁÁÁÁÁÁÁ
1 ÁÁÁÁÁÁ
0ÁÁÁÁÁÁÁÁ
1 ÁÁÁÁÁÁÁÁ
13 ÁÁÁÁÁÁÁÁÁÁ
13.8 ÁÁÁÁÁÁÁÁÁÁÁÁ
9.7 to 5.8 ÁÁÁÁÁÁÁÁÁÁÁÁ
15.8 ÁÁÁÁÁÁÁÁÁÁÁÁ
9.7ÁÁÁÁÁÁÁÁ
1 ÁÁÁÁÁÁÁÁ
1 ÁÁÁÁÁÁ
1ÁÁÁÁÁÁÁÁ
0 ÁÁÁÁÁÁÁÁ
14 ÁÁÁÁÁÁÁÁÁÁ
14.9 ÁÁÁÁÁÁÁÁÁÁÁÁ
9.7 to 5.8 ÁÁÁÁÁÁÁÁÁÁÁÁ
15.3 ÁÁÁÁÁÁÁÁÁÁÁÁ
9.4
ÁÁÁÁÁÁÁÁ
1 ÁÁÁÁÁÁÁÁ
1 ÁÁÁÁÁÁ
1ÁÁÁÁÁÁÁÁ
1 ÁÁÁÁÁÁÁÁ
15 ÁÁÁÁÁÁÁÁÁÁ
16.0 ÁÁÁÁÁÁÁÁÁÁÁÁ
9.7 to 5.8 ÁÁÁÁÁÁÁÁÁÁÁÁ
14.2 ÁÁÁÁÁÁÁÁÁÁÁÁ
8.7
MC13110A/B MC13111A/B
59MOTOROLA ANALOG IC DEVICE DATA
OTHER APPLICATIONS INFORMATION
PCB Board Lay–Out ConsiderationsThe ideal printed circuit board (PCB) lay out would be
double–sided with a full ground plane on one side. Theground plane would be divided into separate sections toprevent any audio signal from feeding into the first localoscillator via the ground plane. Leaded components, canlikewise, be inserted on the ground plane side to improveshielding and isolation from the circuit side of the PCB. Theopposite side of the PCB is typically the circuit side. It has theinterconnect traces and surface mount components. In caseswhere cost allows, it may be beneficial to use multi–layerboards to further improve isolation of components andsensitive sections (i.e. RF and audio). For the CT–0 band, itis also permissible to use single–sided PC layouts, but withcontinuous full ground fill in and around the components.
The proper placement of certain components specified inthe application circuit may be very critical. In a lay–outdesign, these components should be placed before the otherless critical components are inserted. It is also imperativethat all RF paths be kept as short as possible. Finally, theMC13110A/B and MC13111A/B ground pins should be tied toground at the pins and VCC pins should have adequatedecoupling to ground as close to the IC as possible. In mixedmode systems where digital and RF/Analog circuitry arepresent, the VCC and VEE buses need to be ac–decoupledand isolated from each other. The design must also takegreat caution to avoid interference with low level analogcircuits. The receiver can be particularly susceptible tointerference as they respond to signals of only a fewmicrovolts. Again, be sure to keep the dc supply lines for thedigital and analog portions separate. Avoid ground pathscarrying common digital and analog currents, as well.
components that were used to achieve the results shown inthe typical curves and tables, but alternate componentsshould give similar results. The MC13110A/B andMC13111A /B IC are capable of matching the sensitivity, IMD,adjacent channel rejection, and other performance criteria ofa multi–chip analog cordless telephone system. For the mostpart, the same external components are used as in themulti–chip solution.
VB and PLL V refVB is an internally generated bandgap voltage. It functions
as an ac reference point for the operational amplifiers in theaudio section as well as for the battery detect circuitry. Thispin needs to be sufficiently filtered to reduce noise andprevent crosstalk between Rx audio to Tx audio signal paths.A practical capacitor range to choose that will minimizecrosstalk and noise relative to start up time is 0.5 µf to 10 µf.The start time for a 0.5 µf capacitor is approximately 5.0 ms,while a 10µf capacitor is about 10 ms.
The “PLL Vref” pin is the internal supply voltage for the Rxand Tx PLL’s. It is regulated to a nominal 2.5 V. The “VCCAudio” pin is the supply voltage for the internal voltageregulator. Two capacitors with 10 µF and 0.01 µF values mustbe connected to the “PLL Vref” pin to filter and stabilize thisregulated voltage. The “PLL Vref” pin may be used to powerother IC’s as long as the total external load current does notexceed 1.0 mA. The tolerance of the regulated voltage isinitially ±8.0%, but is improved to ±4.0% after the internalBandgap voltage reference is adjusted electronically throughthe MPU serial interface. The voltage regulator is turned off inthe Standby and Inactive modes to reduce current drain. Inthese modes, the “PLL Vref” pin is internally connected to the“VCC Audio” pin (i.e., the power supply voltage is maintainedbut is now unregulated).
It is important to note that the momentary drop in voltagebelow 2.5 V during this transition may affect initial PLL locktimes and also may trigger the reset. To prevent this, the PLLVref capacitor described above should be kept the same orlarger than the VB capacitor, say 10 µf as shown in theevaluation and application diagrams.
DC CouplingChoosing the right coupling capacitors for the compander
is also critical. The coupling capacitors will have an affect onthe audio distortion, especially at lower audio frequencies. Auseful capacitor range for the compander timing capacitors is0.1 µf to 1.0 µf. It is advised to keep the compandercapacitors the same value in both the handset and basesetapplications.
All other dc coupling capacitors in the audio section willform high pass filters. The designer should choose theoverall cut off frequency (–3.0 dB) to be around 200 Hz.Designing for lower cut off frequencies may add unnecessarycost and capacitor size to the design, while selecting too highof a cut off frequency may affect audio quality. It is notnecessary or advised to design each audio couplingcapacitors for the same cut off frequency. Design for theoverall system cut off frequency. (Note: Do not expect theapplication, evaluation, nor production test schematics tonecessarily be the correct capacitor selections.) The goals ofthese boards may be different than the systems approach adesigner must consider.
For the supply pins (VCC Audio and VCC RF) choose a 10µf in parallel with a high quality 0.01 µf capacitor. Separationof the these two supply planes is essential, too. This is toprevent interference between the RF and audio sections. It isalways a good design practice to add additional coupling oneach supply plane to ground as well.
The IF limiter capacitors are recommended to be 0.1 µf.Smaller values lower the gain of the limiter stage. The–3.0 dB limiting sensitivity and SINAD may be adverselyaffected.
MC13110A/B MC13111A/B
60 MOTOROLA ANALOG IC DEVICE DATA
APPENDIX A
Figure 138.
12
Mix
O
ut L
im In
2BN
CBN
C
40 41 42 43 44 45 46 47 48 49 50 51 52
12
34
56
78
910
1112
13
26 25 24 23 22 21 20 19 18 17 16 15 14
3938
3736
3534
3332
3130
2928
27
C38
0.01
C37
0.01
R34
txt
C35
0.01
MC
1311
1A
R37
txt
C28
txt
F1 txt
F2 txt
C31 0.
1C
300.
1R
28 txt
L1 txt
C53
1000
C54
0.01
C55
10µ
R53
47
V CC
Gnd
RSS
I
BNC D
et O
ut
DA
In
T xIn
Amp
Out
T xO
ut
BD2
Out
DA
Out
BD1
Out
R xPD
PLL
V ref
T xPD
T xVC
OC
lk O
utC
D O
ut
Con
nect
orC
ontro
llor
RF
In1
RF
In2
LO2
In
V cap
Ctrl
SA O
ut
E O
ut
Scr O
ut
BNC
BNC
BNC
C39
0.0
1
R39
49.9
R40
49.9
T2–L
2tx
tC
40tx
t
R44
150
C44
47µ
C45
220
pR
4547
k
R46
47 k
C46
0.1
C47
0.4
7
C48
0.4
7
V CC
V CC
V CC
R51
a82
kR
50a
110
k
R51
b10
0 k
R50
b10
0 k
C52
10µ
R42
a tx
tR
4a tx
t
C42
atx
tR
42b
txt
R4b
txt
C1
txt
C2
txt
C3
0.1
XC txt
C42
btx
tC
4tx
t
C5a
0.01
R9
10 k
R10
10 k
R11
10 k
R13
100
k
V CC
R14
100
k
R16
100
k
V CC
V CC
V CC
C18
0.4
7C19
0.1
R20
47 k
C20
220
p
R21
47
kC
21 0
.1
C23
a 0.
01
C24
0.0
1
C23
b10
µ
C26
0.0
47
Mix
1In
1
Mix
1In
2
Mix
1O
utG
nd RF
Mix
2O
utM
ix2
InSG
ndR
FLi
m InLi
m C1
Lim C2
V CC
RF
Lim
Out
Q Coi
lLO
1In
LO1
Out
V cap
Ctrl
Gnd
Aud
io
SA O
ut
SA In
E O
ut
E C
ap
E In
Scr O
ut
Ref
2
Ref
1
V B
RSS
I
Det
Out
R xAu
dio
In
V CC
Audi
o
DA
In
T xIn
Amp
Out
C In
C C
ap
T xO
ut
BD2
Out
DA
Out
BD1
Out
LO2
InV a
gPL
LV
T x PDG
ndPL
LD
ata
ENC
lkC
lkO
utC
DO
utLO
2O
utR x PD
ref
T x VCO
Mix
Out
Mix
In
T1 txt
txt:
see
text
C5b
10µ
Fig
ure
138.
Eva
luat
ion
Boa
rd S
chem
atic
MC
1311
0A
MC13110A/B MC13111A/B
61MOTOROLA ANALOG IC DEVICE DATA
APPENDIX A
Figure 139. Evaluation Board Bill of Materials for U.S. and French Application
APPENDIX C – MEASUREMENT OF COMPANDER ATTACK/DECAY TIME
This measurement definition is based on EIA/CCITTrecommendations.
Compressor Attack TimeFor a 12 dB step up at the input, attack time is defined as
the time for the output to settle to 1.5X of the final steady statevalue.
Compressor Decay TimeFor a 12 dB step down at the input, decay time is defined
as the time for the input to settle to 0.75X of the final steadystate value.
Decay Time
0.75X Final Value
1.5X Final Value
Attack Time
0 mV
0 mV
Input
Output
12 dB
Expander AttackFor a 6.0 dB step up at the input, attack time is defined as
the time for the output to settle to 0.57X of the final steadystate value.
Expander DecayFor a 6.0 dB step down at the input, decay time is defined
as the time for the output to settle to 1.5X of the final steadystate value.
Decay Time
1.5X Final Value
0.57X Final Value
Attack Time
0 mV
Input
Output
6.0 dB
0 mV
MC13110A/B MC13111A/B
65MOTOROLA ANALOG IC DEVICE DATA
FB SUFFIXPLASTIC PACKAGE
CASE 848B–04(QFP–52)ISSUE C
OUTLINE DIMENSIONS
NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD WHERETHE LEAD EXITS THE PLASTIC BODY AT THEBOTTOM OF THE PARTING LINE.
4. DATUMS –A–, –B– AND –D– TO BE DETERMINED ATDATUM PLANE –H–.
5. DIMENSIONS S AND V TO BE DETERMINED ATSEATING PLANE –C–.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLDPROTRUSION. ALLOWABLE PROTRUSION IS 0.25(0.010) PER SIDE. DIMENSIONS A AND B DOINCLUDE MOLD MISMATCH AND ARE DETERMINEDAT DATUM PLANE –H–.
7. DIMENSION D DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBAR PROTRUSIONSHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE DDIMENSION AT MAXIMUM MATERIAL CONDITION.DAMBAR CANNOT BE LOCATED ON THE LOWERRADIUS OR THE FOOT.
Y14.5M, 1982.2 CONTROLLING DIMENSION: MILLIMETER.3 DATUM PLANE –AB– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEADWHERE THE LEAD EXITS THE PLASTIC BODY ATTHE BOTTOM OF THE PARTING LINE.
4 DATUMS –T–, –U–, AND –Z– TO BE DETERMINEDAT DATUM PLANE –AB–.
5 DIMENSIONS S AND V TO BE DETERMINED ATSEATING PLANE –AC–.
6 DIMENSIONS A AND B DO NOT INCLUDE MOLDPROTRUSION. ALLOWABLE PROTRUSION IS0.250 (0.010) PER SIDE. DIMENSIONS A AND B DOINCLUDE MOLD MISMATCH AND AREDETERMINED AT DATUM PLANE –AB–.
7 DIMENSION D DOES NOT INCLUDE DAMBARPROTRUSION. DAMBAR PROTRUSION SHALLNOT CAUSE THE D DIMENSION TO EXCEED0.350 (0.014).
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, andspecifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motoroladata sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights ofothers. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or otherapplications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injuryor death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorolaand its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney feesarising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges thatMotorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an EqualOpportunity/Affirmative Action Employer.
MC13110A/B MC13111A/B
68 MOTOROLA ANALOG IC DEVICE DATA
Mfax is a trademark of Motorola, Inc.How to reach us:USA/EUROPE/Locations Not Listed : Motorola Literature Distribution; JAPAN : Nippon Motorola Ltd.: SPD, Strategic Planning Office, 4–32–1,P.O. Box 5405, Denver, Colorado 80217. 1–303–675–2140 or 1–800–441–2447 Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan. 81–3–5487–8488
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