MBISR Documentation1

CHAPTER 1

INTRODUCTION

1

INTRODUCTION

Embedded memory test design has become an essential part of the system-on-chip

(SOC) development infrastructure. According to the recent ITRS report, the memory cores will

occupy more than 90% of the chip area in less than ten years. The yield of on-chip memories

thus will dominate the chip yield. Go/no-go testing is no longer enough for embedded memories

in the SOC era. Memory diagnostics is quickly becoming a critical issue, so far as manufacturing

yield and time-to-volume of SOC products are concerned. Effective memory diagnostics and

failure analysis (FA) methodologies will help improve the yield of SOC products, especially with

rapid revolution in new product development and advanced process technologies.

Memories are one of the most universal cores. In Alpha 21264, cache RAMs

represent 2/3transistors and 1/3 area. In StrongArmSA110, the embedded RAMs occupy 90%

area In average SOC, memory cores will represent more than 90% of the chip area by 2010

[ITRS 2000]. Here we mentioned different reasons why memory testing is important

Memory testing is a more and more important issue

RAMs are key components for electronic systems

Memories represent about 30% of the semiconductor market

Embedded memories are dominating the chip yield.

Memory testing is more and more difficult

Growing density, capacity, and speed

Emerging new architectures and technologies

2

Embedded memories: access, diagnostics & repair, heterogeneity,

custom design, power & noise, scheduling, compression, etc.

Cost drives the need for more efficient test methodologies

IFA, fault modeling and simulation, test algorithm development and

evaluation, diagnostics, DFT, BIST, BIRA, BISR, etc.

Test automation is required

Failure analysis, fault simulation, ATG, and diagnostics

BIST/BIRA/BISR generation

Embedded memory testing is increasingly difficult

High bandwidth (speed and I/O data width)

Heterogeneity and plurality

Isolation (accessibility)

AC test, diagnostics, and repair

BIST is considered the best solution. Because, for Embedded memories accessibility of Pins is

not sufficient for testing out side the chip.

3

CHAPTER 2

MEMORIES AND MEMORY FAULT ANALYSIS

4

MEMORIES AND MEMORY FAULT ANALYSIS

SOC consists of many memory models. Like, SRAM, FLASH, ROM etc, we

consider here only SRAM type of memory core. In this section we will see what the functional

model of SRAM is and what types of Functional Faults, Fault Models and Defects exist in

SRAM cores due to process variation and manufacturing.

2.1 BASIC FUNCTIONAL MODEL OF SRAM CORE

Basic functional model of SRAM is shown below. Many sub functional models are

there, fault can be any where in the sub modules. Faults can be exist in address decoder logic,

cell array, write driver etc. In section 2 we will see how different faults exists and what are the

fault models respectively

5

2.2 FAULT ANALYSIS

Failure analysis (FA) and diagnosis of memory cores plays a key role in system-on-

chip (SOC) product development and yield ramp-up.

FAULT ANALYSIS

Stuck-at-Fault (SF): Either a cell or a line is stuck to logical `0' or `1'.

ST0 ST1

Transition Fault (TF): The 0!1 (or 1!0) transition is impossible on a cell or a line.

Coupling Fault (CF): When a cell is written to 0!1 (or 1!0), the content of the other cell is

changed. CF is generalized to a k-coupling fault when k-1 cells are changed and is classified into

Inversion or Idempotent coupling faults depending upon what content changed.

6

Address Decoder Fault (ADF): No cell will be accessed with a certain address or multiple

cells are accessed simultaneously or a certain cell can be accessed with multiple addresses.

1) There is no cell for particular address

2) There is no address for a cell

3) Multiple cells pointed by single memory address

4) Multiple Addresses points to single cell

Address Decoder Open Faults (ADOF): CMOS address decoder open faults are caused

by open defects in the CMOS logic gates of the memory address decoders, and due to their

sequential behavior, cannot be mapped to faults of the memory array itself.

Retention Faults (RF): A cell fails to retain its logic value after some time. This fault is

caused by a broken pull-up resistor.

Neighborhood Pattern Sensitive Fault (NPSF): a typical neighborhood pattern

sensitive faults preventing the base cell from being transited to a certain value is called

‘static’NPSF, and an NPSF is called `dynamic' when a transition on the neighborhood cells

triggers a transition on the base cell.

7

2.3 RAM TEST ALGORITHM

•A test algorithm (or simply test) is a finite sequence of test elements

−A test element contains a number of memory operations (access commands)

∗Data pattern (background) specified for the Read operation

∗Address (sequence) specified for the Read and Write operations

•A March test algorithm is a finite sequence of March elements

−A March element is specified by an address order and a number of Read/Write operations

8

CHAPTER 3

BIST (Built-in Self Test)

9

BIST (Built-in Self Test)

Built-in Self Test, or BIST, is the technique of designing additional hardware and

software features into integrated circuits to allow them to perform self-testing, i.e., testing of

their own operation (functionally, parametrically, or both) using their own circuits, thereby

reducing dependence on an external automated test equipment (ATE)

BIST is a Design-for-Testability (DFT) technique, because it makes the electrical testing of a

chip easier, faster, more efficient, and less costly. The concept of BIST is applicable to just about

any kind of circuit, so its implementation can vary as widely as the product diversity that it caters

to.

3.1 Why BIST?

The main drivers for the widespread development of BIST techniques are the fast-rising

costs of ATE testing and the growing complexity of integrated circuits. It is now common to see

complex devices that have functionally diverse blocks built on different technologies inside

them. Such complex devices require high-end mixed-signal testers that possess special digital

and analog testing capabilities. BIST can be used to perform these special tests with additional

on-chip test circuits, eliminating the need to acquire such high-end testers.

3.2 Advantages of Implementing BIST

1) Lower cost of test, since the need for external electrical testing using an ATE will be reduced,

if not eliminated;

2) Better fault coverage, since special test structures can be incorporated onto the chips;

10

3) Shorter test times if the BIST can be designed to test more structures in parallel;

4) Easier customer support;

5) Capability to perform tests outside the production electrical testing environment.

Built-in self-test (BIST) has been proven to be one of the most cost-effective and

The last advantage mentioned can actually allow the consumers themselves to test the chips prior

to mounting or even after these are in the application boards.

3.3 Disadvantages of implementing BIST

1) Additional silicon area and fab processing requirements for the BIST circuits;

2) Reduced access times;

3) Additional pin (and possibly bigger package size) requirements, since the BIST circuitry need

a way to interface with the outside world to be effective;

4) Possible issues with the correctness of BIST results, since the on-chip testing hardware itself

can fail

3.4 BIST TECHNIQUES

BIST techniques are classified in a number of ways, but two common classification

of BIST are the Logic BIST (LBIST) and the Memory BIST (MBIST).

LBIST, which is designed for testing random logic, typically employs a pseudo-

random pattern generator (PRPG) to generate input patterns that are applied to the device's

internal scan chain, and a multiple input signature register (MISR) for obtaining the response of

11

the device to these test input patterns. An incorrect MISR output indicates a defect in the

device.

12

CHAPTER 4

MBIST (memory built in self test

13

MBIST (memory built in self test)

MBIST, as its name implies, is used specifically for testing memories. It typically

consists of test circuits that apply, read, and compare test patterns designed to expose defects in

the memory device. There now exists a variety of industry-standard MBIST algorithms, such as

the "March" algorithm, the checkerboard algorithm, and the varied pattern background

algorithm.

4.1 Why MBIST?

4.1.1 Memory testing is more and more difficult

−Growing density, capacity, and speed

−Emerging new architectures and technologies

−Embedded memories: access, diagnostics & repair, heterogeneity, custom design, power &

noise, scheduling, compression, etc

4.1.2 Widely used solutions for memory testing for the following reasons:

(1) No external test equipment

(2) Reduced development efforts;

(3) Tests can run at circuit speed to yield a more realistic test time;

(4) On-chip test pattern generation to provide higher controllability and observability.

(5) On-chip response analysis;

(6) Test can be on-line or off-line;

(7) Adaptability to engineering changes;

(8) Easier burn-in support.

14

4.2 MEMORY CORES ON SOC

We have different test patterns for Testing Different memories

--- SRAM

--- DRAM

--- FLASH MEMORY

--- ROM

In this document we consider SRAM Memory core for testing.

15

4.3 VARIOUS MBIST ALGORITHMS

4.3.1 Classical Test Algorithms

Classical test algorithms are either (1) simple, fast but have poor fault coverage,

such as Zero-one, Checkerboard; or (2) have good fault coverage but complex and slow, such as

Walking, GALPAT, Sliding Diagonal, Butterfly, MOVI, and etc.. Due to these imbalanced

conflicting traits, the popularity of these algorithms is decreasing.

4.3.2 March-based Test Algorithms

A March-based test algorithm is a finite sequence of March elements. A March

Element is specified by an address order and a number of reads and writes. Examples of some

March-based tests are MATS, MATS+, Marching 1/0, March C-, March Y, March A, March B,

and etc.. Since March-based tests are all simple and possess good fault coverage, they are the

dominant test algorithms implemented in most modern memory BIST.

4.4 IDEAL IMPLEMENTTATION OF MEMORY BIST

4.4.1 BLOCK DIAGRAM OF MEMORY BIST

16

4.4.2 DESCRIPTION

BIST module consists of 3 blocks.

BIST Controller

BIST controllers are mainly used to control pattern generators and comparators, and to

strictly allow the controller to perform write and read operations in compliance with the Memory

BIST Protocol.

Pattern Generator

Pattern generators are mainly used to generate different patterns required for a

Memory BIST operation. These Patterns can be Marching ones and zeros, Alternations ones

and zeros, random numbers and fixed patterns.

Comparator

Comparators are mainly used to compare the Memory Read data and compare

against the expected values, the values generated by the pattern generator. Any failing

comparisons will be flagged as BIST fail by the BIST Controller.

17

CHAPTER 5

MBISR (memory built in self repair)

18

MBISR (memory built in self repair)

Today’s deep submicron technologies allow the implementation of multiple

memories on a single chip Due to their high density memories is more prone to faults. These

faults impact the total chip Yield. One way to solve this problem is to enhance the memory by

redundant memory locations.

The memory is tested by external test hardware or by on chip dedicated hardware

(memory BIST). The second testing strategy is the preferred method for embedded memories.

The present BIST concept prefers a redundancy logic that is placed in parallel to a

memory without spare rows and spare columns. There will be no additional delay for the word

redundancy logic on top of a memory in the data path of the memory.

The memory is repaired during testing by storing faulty addresses in

registers. Furthermore, the application can be started immediately after the memory

BIST passes. The redundancy logic calculation will not increase the test time of the

memory BIST.

5.1 BLOCK DIAGRAM OF MBIST WITH SELF REPAIR

The MBISR concept contains an interface between MBIST logic and redundancy

wrapper for storing faulty addresses. The MBIST controller output must provide three signals to

the wrapper logic during test.

A fail signal to store data in the redundancy registers

The expected data that is compared to the results of RAM data

The failing address

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5.2 ARCHITECTURE

5.2.1 Description

Bist controller writes data to every memory location of the ram.

Bist controller reads data from every memory location and compares with the actual

written data.

If both are same that memory location is functioning correctly.

If the read data is different from actual written data in that particular memory location

fault is there with the corresponding memory location.

Bist controller sends all the fault address to the redundancy logic and those addresses are

saved in redundancy logic register.

Whenever external peripherals accessing memory if the operation to be performed is

write then the input address is compares against all the fault address stored.

Data_out

o_readcontroller

MUX

Redundancy logic

mbist

sram

Control logic

20

Mbist with self repair

If input address matches with any of the fault address the data to be written will be saved

in the redundancy logic data register also along with memory.

If the external operation is to be performed is read then the address in is compared against

all the fault address in the redundancy logic.

If the address matches with any of the fault address and also if fill bit is 1 then the output

data will be taken from corresponding redundancy logic data register.

If the input address is not matched with the fault address the output data will be read from

ram.

21

5.2.2 Architecture diagram

MBIST CONTROLLER

Error

REDUNDANCYLOGIC

Dataout_Redundancy

Out_Select

MUX1

MUX2

MUX3

R

AM

MUX

Address_In Wr in Data in Clk RstBist

Data_out

22

Micro architecture

fail

address dataFA

address dataFA

address dataFO

Address expected dataFA

fail_address expected_data

Address Write data

ram

Controller

data outfail_overflow

Mbist controller

23

CHAPTER 6

VHDL CODE

24

VHDL CODE

6.1 Design units:

6.1.1 MBSIR top module

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity top_module is

port(clk:in std_logic;

rst:in std_logic;

bist:in std_logic;

address_in:integer range 0 to 15;

wr_in:in std_logic;

data_in:in std_logic_vector(3 downto 0);

data_out:out std_logic_vector(3 downto 0));

end top_module;

architecture Behavioral of top_module is

component bist_controller


rst:in std_logic;

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bist:in std_logic;

error:out std_logic;

wr:out std_logic;

address:out integer range 0 to 15;

data1:out std_logic_vector(3 downto 0);

data2:in std_logic_vector(3 downto 0);

fault_address:out integer range 0 to 15 );

end component;

component mux_control

port(a:in std_logic;

b:in std_logic;

select_l:in std_logic;

c:out std_logic);

end component;

component mux

port(a:in std_logic_vector(3 downto 0);

b:in std_logic_vector(3 downto 0);


c:out std_logic_vector(3 downto 0));

end component;

component mux_integer

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port(a:in integer range 0 to 15;

b:in integer range 0 to 15;


c:out integer range 0 to 15);

end component;

component memory


address:integer range 0 to 15;

rst:in std_logic;

wr_en:in std_logic;


data2:out std_logic_vector(3 downto 0));

end component;

component redundancy_logic


rst:in std_logic;

error:in std_logic;

wr_in:in std_logic;

bist:in std_logic;

address_in:in integer range 0 to 15;

fault_address:in integer range 0 to 15;

27


dataout_redundancy:out std_logic_vector(3 downto 0));

end component;

signal error:std_logic;

signal fault_address: integer range 0 to 15;

signal data_bist:std_logic_vector(3 downto 0);

signal data1: std_logic_vector(3 downto 0);

signal data2: std_logic_vector(3 downto 0);

signal address_bist:integer range 0 to 15;

signal wr_en:std_logic;

signal wr:std_logic;

signal address_mem:integer range 0 to 15;

signal dataout_redundancy:std_logic_vector(3 downto 0);

begin

mbist:bist_controller

port map(clk=>clk,

rst=>rst,

bist=>bist,

error=>error,

address=>address_bist,

data1=>data_bist,

data2=>data2,

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wr=>wr,

fault_address=>fault_address);

mux_int:mux_integer

port map(a=>address_in,

b=>address_bist,

select_l=>bist,

c=>address_mem);

mux1:mux

port map(a=>data_in,

b=>data_bist,

select_l=>bist,

c=>data1);

mux2:mux_control

port map(a=>wr_in,

b=>wr,

select_l=>bist,

c=>wr_en);

memory1:memory

port map(clk=>clk,

address=>address_mem,

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rst=>rst,

wr_en=>wr_en,

data1=>data1,

data2=>data2);

redundancy_logic1:redundancy_logic

port map(clk=>clk,

rst=>rst,

error=>error,

wr_in=>wr_in,

bist=>bist,

address_in=>address_in,

fault_address=>fault_address,

data_in=>data_in,

dataout_redundancy=>dataout_redundancy);

mux3:mux

port map(a=>data2,

b=>dataout_redundancy,

select_l=>error,

c=>data_out);

end Behavioral;

30

6.1.2. Bist controller:

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_unsigned.all;

USE ieee.numeric_std.ALL;

ENTITY bist_controller IS


rst:in std_logic;

bist:in std_logic;

address:out integer range 0 to 15;

data1:out std_logic_vector(3 downto 0);


error:out std_logic;

wr:out std_logic;

fault_address:out integer range 0 to 15);

END bist_controller;

ARCHITECTURE behavior OF bist_controller IS

signal value:std_logic_vector(3 downto 0):="0011";

signal address_reg : integer range 0 to 15;

signal read_address : integer range 0 to 15;

signal expected_data:std_logic_vector(3 downto 0);

signal count1: integer range 0 to 15;

signal count2:std_logic_vector(3 downto 0);

31

signal count3: std_logic:='0';

BEGIN

process(clk)

begin

if(rst='1')then

data1<="ZZZZ";

address_reg<=0;

read_address<=0;

expected_data<="ZZZZ";

error<='0';

elsif(clk'event and clk='1') then

count3<=not count3;

wr<=count3;

address_reg<=count1;

read_address<=address_reg;

end if;

end process;

process(clk)

begin

if(clk'event and clk='1') then

if(count3='1') then

value<=value+1;

32

data1<=value;

count1<=count1+1;

address<= count1;

if(count1=15) then

count1<=0;

end if;

if(data2=value) then

error<='0';

else

error<='1';

fault_address<=read_address;

end if;

else

address<=count1;

expected_data<=value;

end if;

end if;

end process;

END;

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6.1.3 Memory

library IEEE;




entity memory is

Port ( address : in integer range 0 to 15;

data1 : in STD_LOGIC_VECTOR (3 downto 0);

data2 : out STD_LOGIC_VECTOR (3 downto 0);

wr_en : in STD_LOGIC;

rst : in STD_LOGIC;

clk : in STD_LOGIC);

end memory;

architecture Behavioral of memory is

type Memory is array(0 to 15)of std_logic_vector(3 downto 0);

signal Mem:Memory;

begin

process(clk,data1,address,wr_en)

begin

--Mem(1)(2)<='0';

34

--mem(3)<="0000";

if(clk='1' and clk' event)then

if (wr_en='1')then

Mem(address)<=data1;

elsif(wr_en='0')then

data2<=Mem(address);

end if;

end if;

end process;

end Behavioral;

35

6.1.4 Redundancy logic

library IEEE;




entity redundancy_logic is


rst:std_logic;

error:in std_logic;

wr_in:in std_logic;

address_in:in integer range 0 to 15;

fault_address:in integer range 0 to 15;

bist:in std_logic;


dataout_redundancy:out std_logic_vector(3 downto 0));

end redundancy_logic;

architecture Behavioral of redundancy_logic is

type reg1 is array(1 to 4) of integer range 0 to 15;

signal reg_address:reg1;

type reg2 is array(1 to 4) of std_logic_vector(3 downto 0);

signal reg_data :reg2;

36

type f1 is array(1 to 4) of std_logic;

signal f:f1;

signal index:integer range 1 to 4;

begin

process(clk)

begin

if(rst='1') then

reg_address(1)<=0;

reg_address(2)<=0;

reg_address(3)<=0;

reg_address(4)<=0;

reg_data(1)<="ZZZZ";




f(1)<='0';

f(2)<='0';

f(3)<='0';

f(4)<='0';

dataout_redundancy<="ZZZZ";

elsif(clk'event and clk='1') then

37

if(bist='1') then

if(error='1') then

reg_address(index)<=fault_address;

index<=index+1;

else

index<=index;

end if;

else

if(wr_in='1') then

if(address_in=reg_address(1)) then

reg_data(1)<=data_in;

f(1)<='1';

elsif(address_in=reg_address(2)) then


f(2)<='1';



f(3)<='1';



f(4)<='1';

38

end if;

else

if(address_in=reg_address(1) and f(1)<='1') then

dataout_redundancy<=reg_data(1);

elsif(address_in=reg_address(2) and f(2)<='1') then






end if;

end if;

end if;

end if;

end process;

end Behavioral;

39

6.1.5 Mux_int

library IEEE;




entity mux_integer is

port(a:in integer range 0 to 15;

b:in integer range 0 to 15;


c:out integer range 0 to 15);

end mux_integer;

architecture mux_int of mux_integer is

begin

process(a,b,select_l)

begin

if(select_l = '0') then

c<=a;

else

c<=b;

end if;

end process;

end mux_int;

40

6.1.6 Mux1

library IEEE;




entity mux is





end mux;

architecture Behavioral of mux is

begin


begin


c<=a;

else

c<=b;

end if;

end process;

end Behavioral;

41

6.1.7 Mux2

library IEEE;




entity mux_control is

port(a:in std_logic;

b:in std_logic;


c:out std_logic);

end mux_control;

architecture mux_control of mux_control is

begin


begin


c<=a;

else

c<=b;

end if;

end process;

end mux_control;

42

6.1.8 Mux3

library IEEE;




entity mux is





end mux;

architecture Behavioral of mux is

begin


begin


c<=a;

else

c<=b;

end if;

end process;

end Behavioral;

43

6.2 Test bench

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_unsigned.all;

USE ieee.numeric_std.ALL;

ENTITY test_bench_vhd IS

END test_bench_vhd;

ARCHITECTURE behavior OF test_bench_vhd IS

COMPONENT top_module

PORT(

clk : IN std_logic;

rst : IN std_logic;

bist : IN std_logic;

address_in : IN integer range 0 to 15;

wr_in : IN std_logic;

data_in : IN std_logic_vector(3 downto 0);

data_out : OUT std_logic_vector(3 downto 0));

END COMPONENT;

--Inputs

SIGNAL clk : std_logic := '0';

SIGNAL rst : std_logic := '0';

SIGNAL bist : std_logic := '0';

44

SIGNAL wr_in : std_logic := '0';

SIGNAL address_in :integer range 0 to 15:=0;

SIGNAL data_in : std_logic_vector(3 downto 0) := (others=>'0');

signal address1 :integer range 0 to 15:=0;

signal address2 :integer range 0 to 15:=0;

signal addr1 :integer range 0 to 15:=0;

signal addr2 :integer range 0 to 15:=0;

SIGNAL data_out : std_logic_vector(3 downto 0);

signal cnt :integer range 0 to 100:=0;

BEGIN

uut: top_module PORT MAP(

clk => clk,

rst => rst,

bist => bist,

address_in => address_in,

wr_in => wr_in,

data_in => data_in,

data_out => data_out);

PROCESS

BEGIN

clk<='0';

wait for 5ns;

45

clk<='1';

wait for 5ns;

END PROCESS;

rst<='1','0' after 10ns;

bist<='1','0' after 340 ns;

process(clk)

begin

if(clk'event and clk='1') then

cnt<=cnt+1;

addr1<=addr1+1;

addr2<=addr2+1;

if(cnt>35) then

if(cnt<45) then

wr_in<='1';

address_in<=addr1;

data_in<="1111";

end if;

if(cnt>45) then

wr_in<='0';

address_in<=addr2;

end if;

end if;

46

end if;

end process;

end;

47

CHAPTER 7

SIMULATION RESULTS

48

SIMULATION RESULTS

49

CHAPTER 8

SYNTHESIS REPORT

50

SYNTHESIS REPORT

Device utilization summary:

Selected Device: 3s100evq100-5

Number of Slices: 68 out of 960 7%

Number of Slice Flip Flops: 81 out of 1920 4%

Number of 4 input LUTs: 96 out of 1920 5%

Number used as logic: 88

Number used as Shift registers: 4

Number used as RAMs: 4

Number of IOs: 16

Number of bonded IOBs: 16 out of 66 24%

Number of GCLKs: 1 out of 24 4%

Timing Summary:

Minimum period: 4.988ns

Maximum Frequency: 200.487MHz

HDL Synthesis Report

Macro Statistics

# RAMs : 1

16x4-bit single-port RAM : 1

# Counters : 3

3-bit up counter : 1

4-bit up counter : 2

51

# Registers : 22

1-bit register : 4

4-bit register : 18

# Comparators : 9

4-bit comparator equal : 5

4-bit comparator not equal : 4

# Tristates : 6

4-bit tristate buffer : 6

Final Register Report

Macro Statistics

# Registers : 77

Flip-Flops : 77

# Shift Registers : 4

2-bit shift register : 4

Design Statistics

# IOs : 16

Cell Usage

# BELS : 97

# GND : 1

# INV : 3

# LUT2 : 9

52

# LUT2_L : 1

# LUT3 : 20

# LUT4 : 45

# LUT4_D : 6

# LUT4_L : 4

# MUXF5 : 8

# FlipFlops/Latches : 81

# FDC : 12

# FDCE : 16

# FDE : 52

# FDP : 1

# RAMS : 4

# RAM16X1S : 4

# Shift Registers : 4

# SRL16E : 4

# Clock Buffers : 1

# BUFGP : 1

# IO Buffers : 15

# IBUF : 11

# OBUF : 4

53

8.1 RTL SCHEMATICS

8.1.1 RTL_TOP

8.1.2 RTL_MBSIR

54

8.1.3 RTL_BIST CONTROLLER

55

8.1.4 RTL_MEMORY

8.1.5 RTL_MUX

56

8.1.6 RTL_REDUNDANCY LOGIC

8.2 TECNOLOGY SCHEMATICS

57

CONCLUSION

Memories are the most universal component today. Almost all system chips contain

some type of embedded memory, such as ROM, SRAM, DRAM, and flash. Memory testing is

very important but challenging. Memory BIST is considered the best solution due to various

engineering and economic reasons. March tests are the most popular algorithms currently

implemented in BIST hardware. Various implementation schemes for memory BISTs are

presented and their trade-offs are discussed. Integrating self repair feature improves the chip

yield.

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MBISR Documentation1

Documents

memory fault analysis

memory models

single memory address

memory address decoders

memory array

fault models

fault simulation

important memory testing