MAX1909-MAX8725

General DescriptionThe MAX1909/MAX8725 highly integrated control ICssimplify construction of accurate and efficient multi-chemistry battery chargers. The MAX1909/MAX8725use analog inputs to control charge current and volt-age, and can be programmed by a host microcontroller(µC) or hardwired. High efficiency is achieved throughuse of buck topology with synchronous rectification.

The maximum current drawn from the AC adapter is pro-grammable to avoid overloading the AC adapter whensupplying the load and the battery charger simultane-ously. The MAX1909/MAX8725 provide a digital outputthat indicates the presence of an AC adapter, and ananalog output that monitors the current drawn from theAC adapter. Based on the presence or absence of theAC adapter, the MAX1909/MAX8725 automatically selectthe appropriate source for supplying power to the sys-tem by controlling two external p-channel MOSFETs.Under system control, the MAX1909/MAX8725 allow thebattery to undergo a relearning or conditioning cycle inwhich the battery is completely discharged through thesystem load and then recharged.

The MAX1909 includes a conditioning charge featurewhile the MAX8725 does not. The MAX1909/MAX8725are available in space-saving 28-pin, 5mm 5mm thinQFN packages and operate over the extended -40°C to+85°C temperature range. The MAX1909/MAX8725 arenow available in lead-free packages.

ApplicationsNotebook and Subnotebook Computers Hand-Held Data Terminals

Features♦ ±0.5% Accurate Charge Voltage (0°C to +85°C)♦ ±3% Accurate Input Current Limiting♦ ±5% Accurate Charge Current♦ Programmable Charge Current >4A♦ Automatic System Power-Source Selection♦ Analog Inputs Control Charge Current and

Charge Voltage♦ Monitor Outputs for

Current Drawn from AC Input SourceAC Adapter Presence

♦ Up to 17.65V (max) Battery Voltage♦ Maximum 28V Input Voltage♦ Greater than 95% Efficiency♦ Charge Any Battery Chemistry: Li+, NiCd, NiMH,

Lead Acid, etc.

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Multichemistry Battery Chargers with AutomaticSystem Power Selector

________________________________________________________________ Maxim Integrated Products 1

Ordering Information

19-2805; Rev 2; 9/04

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

PART TEMP RANGE PIN-PACKAGE

MAX1909ETI -40°C to +85°C 28 Thin QFN

MAX1909ETI+ -40°C to +85°C 28 Thin QFN

MAX8725ETI -40°C to +85°C 28 Thin QFN

MAX8725ETI+ -40°C to +85°C 28 Thin QFN

28 27 26 25 24 23 22

8 9 10 11 12 13 14

15

16

17

18

19

20

21

7

6

5

4

3

2

1

MAX1909MAX8725

THIN QFN

TOP VIEW

LDO

DCIN

ACIN

REF

GND/PKPRES

ACOK

MODE

PDL

PDS

CSSP

CSSN

SRC

DHI

DHIV

DLOV

DLO

PGND

CSIP

CSIN

BATT

GND

CCS

CCV

CCI

VCTL

ICTLCLS

IINP

Pin Configuration

CSSP CSSN

LDO

DHI

DLOV

DLO

PGND

CSIP

CSIN

BATTGND

DCIN

VCTL

ICTL

MODE

ACIN

ACOK

CLS

CCVCCI

CCSREF

LDO

AC ADAPTER: INPUT

P30.01Ω

10µHN1

P1

0.015Ω

TOEXTERNAL LOAD

LDO

PDS

PDLSRC

LDO

REF

IINPIINP

DHIV

SRC

P2

MAX1909MAX8725

PKPRESMAX8725 ONLY

Minimum Operating Circuit

+Denotes lead-free package.

EVALUATION KIT AVAILABLE

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2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS(Circuit of Figure 1, VDCIN = VCSSP = VCSSN = 18V, VBATT = VCSIP = VCSIN = 12V, VVCTL = VICTL = 1.8V, MODE = float, ACIN = 0, CLS =REF, GND = PGND = 0, PKPRES = GND, LDO = DLOV, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functionaloperation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure toabsolute maximum rating conditions for extended periods may affect device reliability.

DCIN, CSSP, CSSN, SRC, ACOK to GND..............-0.3V to +30VDHIV ........................................................…SRC + 0.3, SRC - 6VDHI, PDL, PDS to GND ...............................-0.3V to (VSRC + 0.3)BATT, CSIP, CSIN to GND .....................................-0.3V to +20VCSIP to CSIN or CSSP to CSSN or PGND to GND ...-0.3V to +0.3VCCI, CCS, CCV, DLO, IINP, REF,

ACIN to GND ........................................-0.3V to (VLDO + 0.3V)DLOV, VCTL, ICTL, MODE, CLS, LDO,

PKPRES to GND...................................................-0.3V to +6V

DLOV to LDO.........................................................-0.3V to +0.3VDLO to PGND..........................................-0.3V to (DLOV + 0.3V)LDO Short-Circuit Current...................................................50mAContinuous Power Dissipation (TA = +70°C)

28-Pin TQFN (derate 20.8mW/°C above +70°C) .......1666mWOperating Temperature Range ...........................-40°C to +85°CJunction Temperature ......................................................+150°CStorage Temperature Range .............................-60°C to +150°CLead Temperature (soldering, 10s) .................................+300°C

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

CHARGE VOLTAGE REGULATION

VCTL Range 0 3.6 VVVCTL = 3.6V (3 or 4 cells);not including VCTL resistor tolerances

-0.8 +0.8

VVCTL = 3.6V/20 (3 or 4 cells); not includingVCTL resistor tolerances

-0.8 +0.8

VVCTL = 3.6V (3 or 4 cells); including VCTLresistor tolerances of 1%

-1.0 +1.0

Battery Regulation VoltageAccuracy

VVCTL = VLDO (3 or 4 cells, defaultthreshold of 4.2V/cell)

-0.5 +0.5

%

VVCTL Default Threshold VVCTL rising 4.1 4.3 V VVCTL = 3V 0 2.5

VCTL Input Bias Current VDCIN = 0, VVCTL = 5V 0 12

µA

CHARGE-CURRENT REGULATION

MAX1909 0 3.6 ICTL Range MAX8725 0 3.2 V

CSIP-to-CSIN Full-Scale Current-Sense Voltage

69.37 75.00 80.63 mV

MAX1909: VICTL = 3.6V (not including ICTLresistor tolerances)

-7.5 +7.5


-5 +5

MAX1909: VICTL = 3.6V x 0.5, MAX8725:VICTL = 3.2V x 0.5 (not including ICTLresistor tolerances)

-5 +5


-7.5 +7.5

Charge-Current Accuracy

MAX8725: VICTL = 0.18V (not includingICTL resistor tolerances)

-30 +30

%

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_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)(Circuit of Figure 1, VDCIN = VCSSP = VCSSN = 18V, VBATT = VCSIP = VCSIN = 12V, VVCTL = VICTL = 1.8V, MODE = float, ACIN = 0, CLS =REF, GND = PGND = 0, PKPRES = GND, LDO = DLOV, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)


MAX1909: VICTL = 3.6V x 0.5, MAX8725:VICTL = 3.2V x 0.5 (including ICTL resistortolerances of 1%)

-7.0 +7.0Charge-Current Accuracy

VICTL = VLDO (default threshold of 45mV) -5 +5

%

VICTL Default Threshold VICTL rising 4.1 4.2 4.3 V BATT/CSIP/CSIN Input VoltageRange

0 19 V

Charging enabled 350 650 CSIP/CSIN Input Current Charging disabled; VDCIN = 0 or VICTL = 0 0.1 1 µA

MAX1909 0.75 ICTL Power-Down ModeThreshold Voltage

MAX8725 0.06

V

MAX1909 0.85 ICTL Power-Up Mode ThresholdVoltage

MAX8725 0.11

V

VICTL = 3V -1 +1ICTL Input Bias Current VDCIN = 0V, VICTL = 5V -1 +1

µA

INPUT CURRENT REGULATION

CSSP-to-CSSN Full-ScaleCurrent-Sense Voltage

72.75 75.00 77.25 mV

VCLS = REF -3 +3

VCLS = REF x 0.75 -3 +3Input Current-LimitAccuracy

VCLS = REF x 0.5 -4 +4

%

C S S P /C S S N Inp ut V ol tag e Rang e 8.0 28 V VCSSP = VCSSN = VDCIN > 8.0V 450 730

CSSP/CSSN Input Current VDCIN = 0 0.1 1

µA

CLS Input Range 1.6 REF V CLS Input Bias Current VCLS = 2.0V -1 +1 µA

IINP Transconductance VCSSP - VCSSN = 56mV 2.7 3.0 3.3 mA/V

VCSSP - VCSSN = 75mV, terminated with10kΩ

-7.5 +7.5


-5 +5IINP Accuracy


-10 +10

%

IINP Output Current VCSSP - VCSSN = 150mV, VIINP = 0V 350 µA

IINP Output Voltage VCSSP - VCSSN = 150mV, VIINP = float 3.5 V

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4 _______________________________________________________________________________________



SUPPLY AND LINEAR REGULATOR

DCIN Input Voltage Range VDCIN 8.0 28 V DCIN falling 7 7.4 DCIN Undervoltage-Lockout Trip

Point DCIN rising 7.5 7.85 V

DCIN Quiescent Current IDCIN 8.0V < VDCIN < 28V 2.7 6 mA

VBATT = 19V, VDCIN = 0V, or ICTL = 0V 0.1 1 VBATT = 16.8V, VDCIN = 19V, ICTL = 0V 0.1 1 BATT Input Current IBATT

VBATT = 2V to 19V, VDCIN > VBATT + 0.3V 200 500

µA

LDO Output Voltage 8.0V < VDCIN < 28V, no load 5.25 5.4 5.55 V LDO Load Regulation 0 < ILDO < 10mA 80 115 mV

LDO Undervoltage-Lockout TripPoint

VDCIN = 8.0V 3.20 4 5.15 V

REFERENCE

REF Output Voltage Ref 0 < IREF < 500µA 4.2023 4.2235 4.2447 V REF Undervoltage-Lockout TripPoint

REF falling 3.1 3.9 V

TRIP POINTS

BATT POWER_FAIL Threshold VDCIN - VBATT, VDCIN falling 50 100 150 mV

BATT POWER_FAIL ThresholdHysteresis

100 200 300 mV

ACIN Threshold ACIN rising 2.007 2.048 2.089 V ACIN Threshold Hysteresis 10 20 30 mV

ACIN Input Bias Current VACIN = 2.048V -1 +1 µA

SWITCHING REGULATOR DHI Off-Time V B AT T = 16.0V , V D C I N = 19V , V M OD E = 3.6V 360 400 440 ns

DHI Minimum Off-Time V B AT T = 16.0V , V D C I N = 17V , V M OD E = 3.6V 260 300 350 ns

DLOV Supply Current IDLOV DLO low 5 10 µA

Sense Voltage for MinimumDiscontinuous Mode RippleCurrent

7.5 mV

Cycle-by-Cycle Current-LimitSense Voltage

97 mV

Sense Voltage for BatteryUndervoltage Charge Current

MAX1909 only, BATT = 3.0V per cell 3 4.5 6 mV

MAX1909 only, MODE = float (3 cell),VBATT rising

9.18 9.42

Battery Undervoltage Threshold MAX1909 only, MODE = LDO (4 cell),VBATT rising

12.235 12.565

V

DHIV Output Voltage With respect to SRC -4.5 -5.0 -5.5 V

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_______________________________________________________________________________________ 5



DHIV Sink Current 10 mA

DHI On-Resistance Low DHI = VDHIV, IDHI = -10mA 2 5 Ω DHI On-Resistance High DHI = VCSSN, IDHI = 10mA 2 4 Ω DLO On-Resistance High VDLOV = 4.5V, IDLO = +100mA 3 7 Ω DLO On-Resistance Low VDLOV = 4.5V, IDLO = -100mA 1 3 ΩERROR AMPLIFIERS

V C TL = 3.6, V BATT = 16.8V , M OD E = LD O 0.0625 0.125 0.2500 GMV Loop Transconductance V C TL = 3.6, V BATT = 12.6V , M OD E = FLOAT 0.0833 0.167 0.3330 mA/V

GMI Loop Transconductance MAX1909: ICTL = 3.6V, MAX8725: VICTL =3.2V, VCSSP - VCSIN = 75mV

0.5 1 2 mA/V

GMS Loop Transconductance VCLS = 2.048V, VCSSP - VCSSN = 75mV 0.5 1 2 mA/V

CCI/CCS/CCV Clamp Voltage 0.25V < VCCV < 2.0V, 0.25V < VCCI < 2.0V,0.25V < VCCS < 2.0V

150 300 600 mV

LOGIC LEVELS

MODE Input Low Voltage 0.8 V MODE Input Middle Voltage 1.6 1.8 2.0 V MODE Input High Voltage 2.8 V MODE Input Bias Current MODE = 0V or 3.6V -2 +2 µA

ACOK AND PKPRES

ACOK Input Voltage Range 0 28 V ACOK Sink Current VACOK = 0.4V, ACIN = 1.5V 1 mA

ACOK Leakage Current VACOK = 28V, ACIN = 2.5V 1 µA

PKPRES Input VoltageRange

0 LDO V

PKPRES Input Bias Current -1 +1 µA

PKPRES Battery Removal DetectThreshold

MAX8725, PKPRES rising 55 % ofLDO

PKPRES Hysteresis MAX8725 1 %PDS, PDL SWITCH CONTROL

PDS Switch Turn-Off Threshold VDCIN - VBATT, VDCIN falling 50 100 150 mV

PDS Switch Threshold Hysteresis VDCIN - VBATT 100 200 300 mV

PDS Output Low Voltage, PDSBelow SRC

IPDS = 0A 8 10 12 V

PDS Turn-On Current PDS = SRC 6 12 mA

PDS Turn-Off Current VPDS = VSRC - 2V, VDCIN = 16V 10 50 mA

PDL Switch Turn-On Threshold VDCIN - VBATT, VDCIN falling 50 100 150 mV

PDL Switch Threshold Hysteresis VDCIN - VBATT 100 200 300 mV

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6 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS(Circuit of Figure 1, VDCIN = VCSSP = VCSSN = 18V, VBATT = VCSIP = VCSIN = 12V, VVCTL = VICTL = 1.8V, MODE = float, ACIN = 0, CLS =REF, GND = PGND = 0, PKPRES = GND, LDO = DLOV, TA = -40°C to +85°C, unless otherwise noted.)


CHARGE VOLTAGE REGULATION

VCTL Range 0 3.6 VVVCTL = 3.6V (3 or 4 cells); not includingVCTL resistor tolerances

-0.8 +0.8

VVCTL = 3.6V/20 (3 or 4 cells); not includingVCTL resistor tolerances

-0.8 +0.8

VVCTL = 3.6V (3 or 4 cells); including VCTLresistor tolerances of 1%

-1.0 +1.0

Battery Regulation VoltageAccuracy

VVCTL = VLDO (3 or 4 cells, defaultthreshold of 4.2V/cell)

-0.8 +0.8

%

VVCTL Default Threshold VVCTL rising 4.1 4.3 V VVCTL = 3V 0 2.5

VCTL Input Bias Current VDCIN = 0V, VVCTL = 5V 0 12

µA

CHARGE-CURRENT REGULATION

MAX1909 0 3.6 ICTL Range MAX8725 0 3.2 V

CSIP-to-CSIN Full-Scale Current-Sense Voltage

69.37 80.63 mV


-7.5 +7.5


-5 +5

MAX1909: VICTL = 3.6V x 0.5, MAX8725:VICTL = 3.2V x 0.5 (not including ICTLresistor tolerances)

-5 +5


-7.5 +7.5

Charge-Current Accuracy

MAX8725: VICTL = 0.18V (not includingICTL resistor tolerances)

-30 +30

%



PDL Turn-On Resistance PDL = GND 50 100 150 kΩ

PDL Turn-Off Current VSRC - VPDL = 1.5V 6 12 mA

SRC = 19V, DCIN = 0V 1 SRC Input Bias Current SRC = 19, VBATT = 16V 450 1000 µA

Delay Time Between PDL andPDS Transitions

2.5 5 7.5 µs

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_______________________________________________________________________________________ 7

ELECTRICAL CHARACTERISTICS (continued)(Circuit of Figure 1, VDCIN = VCSSP = VCSSN = 18V, VBATT = VCSIP = VCSIN = 12V, VVCTL = VICTL = 1.8V, MODE = float, ACIN = 0, CLS =REF, GND = PGND = 0, PKPRES = GND, LDO = DLOV, TA = -40°C to +85°C, unless otherwise noted.)


MAX1909: VICTL = 3.6V x 0.5, MAX8725:VICTL = 3.2V x 0.5 (including ICTL resistortolerances of 1%)

-7.0 +7.0Charge-Current Accuracy

VICTL = VLDO (default threshold of 45mV) -5 +5

%

VICTL Default Threshold VICTL rising 4.3 V BATT/CSIP/CSIN Input VoltageRange

0 19 V

CSIP/CSIN Input Current Charging enabled 650 µA

MAX1909 0.75 ICTL Power-Down ModeThreshold Voltage

MAX8725 0.06

V

MAX1909 0.85 ICTL Power-Up Mode ThresholdVoltage

MAX8725 0.11

V

INPUT CURRENT REGULATION

CSSP-to-CSSN Full-ScaleCurrent-Sense Voltage

72.75 77.25 mV

VCLS = REF -3 +3

VCLS = REF x 0.75 -3 +3Input Current-Limit Accuracy

VCLS = REF x 0.5 -4 +4

%

CSSP/CSSN Input Voltage Range 8.0 28 VCSSP/CSSN Input Current VCSSP = VCSSN = VDCIN > 8.0V 730 µA

CLS Input Range 1.6 REF V IINP Transconductance VCSSP - VCSSN = 56mV 2.7 3.3 mA/V


-7.5 +7.5


-5 +5IINP Accuracy


-10 +10

%

IINP Output Current VCSSP - VCSSN = 150mV, VIINP = 0V 350 µA

IINP Output Voltage VCSSP - VCSSN = 150mV, VIINP = float 3.5 VSUPPLY AND LINEAR REGULATOR

DCIN Input Voltage Range VDCIN 8.0 28 V DCIN falling 7 D C IN U nd er vol tag e- Lockout Tr i p

P oi nt DCIN rising 7.85 V

DCIN Quiescent Current IDCIN 8.0V < VDCIN < 28V 6 mA

BATT Input Current IBATT VBATT = 2V to 19V, VDCIN > VBATT + 0.3V 500 µA

LDO Output Voltage 8.0V < VDCIN < 28V, no load 5.25 5.55 V LDO Load Regulation 0 < ILDO < 10mA 115 mV

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8 _______________________________________________________________________________________



LDO Undervoltage-Lockout TripPoint

VDCIN = 8.0V 3.20 5.15 V

REFERENCE

REF Output Voltage Ref 0 < IREF < 500µA 4.1960 4.2520 V REF Undervoltage-Lockout TripPoint

REF falling 3.9 V

TRIP POINTS

BATT POWER_FAIL Threshold VDCIN - VBATT, VDCIN falling 50 150 mV

BATT POWER_FAIL ThresholdHysteresis

100 300 mV

ACIN Threshold ACIN rising 2.007 2.089 V ACIN Threshold Hysteresis 10 30 mV

SWITCHING REGULATOR DHI Off-Time VBATT = 16.0V, VDCIN = 19V, VMODE = 3.6V 360 440 ns

DHI Minimum Off-Time VBATT = 16.0V, VDCIN = 17V, VMODE = 3.6V 260 350 ns

DLOV Supply Current IDLOV DLO low 10 µA

Sense Voltage for BatteryUndervoltage Charge Current

MAX1909 only, BATT = 3.0V per cell 3 6 mV

MAX1909 only, MODE = float (3 cell),VBATT rising

9.18 9.42

Battery Undervoltage Threshold MAX1909 only, MODE = LDO (4 cell),VBATT rising

12.235 12.565

V

DHIV Output Voltage With respect to SRC -4.5 -5.5 V DHIV Sink Current 10 mA

DHI On-Resistance Low DHI = VDHIV, IDHI = -10mA 5 Ω DHI On-Resistance High DHI = VCSSN, IDHI = 10mA 4 Ω DLO On-Resistance High VDLOV = 4.5V, IDLO = +100mA 7 Ω DLO On-Resistance Low VDLOV = 4.5V, IDLO = -100mA 3 ΩERROR AMPLIFIERS

V C TL = 3.6, V BATT = 16.8V , M OD E = LD O 0.0625 0.2500 GMV Loop Transconductance V C TL = 3.6, V BATT = 12.6V , M OD E = FLOAT 0.0833 0.3330

mA/V

GMI Loop Transconductance MAX1909: ICTL = 3.6V, MAX8725: VICTL =3.2V, VCSSP - VCSIN = 75mV

0.5 2.0 mA/V

GMS Loop Transconductance VCLS = 2.048V, VCSSP - VCSSN = 75mV 0.5 2.0 mA/V

CCI/CCS/CCV Clamp Voltage 0.25V < VCCV < 2.0V, 0.25V < VCCI < 2.0V,0.25V < VCCS < 2.0V

150 600 mV

LOGIC LEVELS

MODE Input Low Voltage 0.8 V MODE Input Middle Voltage 1.6 2.0 V

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_______________________________________________________________________________________ 9



MODE Input High Voltage 2.8 VACOK AND PKPRES

ACOK Input Voltage Range 0 28 V ACOK Sink Current VACOK = 0.4V, ACIN = 1.5V 1 mA

PKPRES Input Voltage Range 0 LDO V PKPRES Battery Removal DetectThreshold

MAX8725, PKPRES rising 55 % ofLDO

PDS, PDL SWITCH CONTROL

PDS Switch Turn-Off Threshold VDCIN - VBATT, VDCIN falling 50 150 mV

P D S S w i tch Thr eshol d H yster esi s VDCIN - VBATT 100 300 mV

PDS Output Low Voltage, PDSBelow SRC

IPDS = 0A 8 12 V

PDS Turn-On Current PDS = SRC 6 mA

PDS Turn-Off Current VPDS = VSRC - 2V, VDCIN = 16V 10 mA

PDL Switch Turn-On Threshold VDCIN - VBATT, VDCIN falling 50 150 mV

P D L S w i tch Thr eshol d H yster esi s VDCIN - VBATT 100 300 mV

PDL Turn-On Resistance PDL = GND 50 150 kΩ

PDL Turn-Off Current VSRC - VPDL = 1.5V 6 mA

SRC Input Bias Current SRC = 19, VBATT = 16V 1000 µA

Note 1: Guaranteed by design. Not production tested.

BATTERY INSERTIONAND REMOVAL RESPONSE

MAX1909/MAX8725 toc01

500μs/div

1V

0V

2V

3V

16V

17V

0A

0AIIN

IBATT

VBATT

VCCI, VCCV

5A/div

5A/div

VCCI

VCCV

VCCV

VCCV

VCCI

VCCI

SYSTEM LOAD-TRANSIENT RESPONSEMAX1909/MAX8725 toc02

100μs/div

1V

0V

2V

3V

5A

5A

0A

5A

0A

0AIBATT

IIN

ISYSTEMLOAD

VCCS

VCCI

CCS

CCI

Typical Operating Characteristics(Circuit of Figure 2, VDCIN = 20V, charge current = 3A, 4 Li+ series cells, TA = +25°C, unless otherwise noted.)

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LDO LOAD REGULATION

MAX

1909

/MAX

8725

toc0

4

LDO CURRENT (mA)LD

O OU

TPUT

ERR

OR (%

)987654321

-1.2

-1.0

-0.8

-0.6

-0.4

-0.2

0

-1.40 10

LINE-TRANSIENT RESPONSEMAX1909/MAX8725 toc03

500μs/div

1.8V

VBATT AC-COUPLED200mV/div

INDUCTOR CURRENT200mA/div

1.6V

3A

20V

30VVDCIN

VCCV

REF vs. TEMPERATURE

MAX

1909

/MAX

8725

toc0

7

TEMPERATURE (°C)

REF

OUTP

UT E

RROR

(%)

603510-15

-0.15

-0.10

-0.05

0

0.05

0.10

-0.20-40 85

EFFICIENCY vs. CHARGE CURRENT

MAX

1909

/MAX

8725

toc0

8

CHARGE CURRENT (A)

EFFI

CIEN

CY (%

)

2.52.01.51.00.5

82

84

86

88

90

92

94

96

98

100

800 3.0

4 CELLS

3 CELLS

LDO LINE REGULATION

MAX

1909

/MAX

8725

toc0

5

INPUT VOLTAGE (V)

LDO

OUTP

UT E

RROR

(%)

2010

-0.05

0

0.05

0.10

-0.100 30

REF LOAD REGULATION

MAX

1909

/MAX

8725

toc0

6

REF CURRENT (μA)

REF

OUTP

UT E

RROR

(%)

800600400200

-0.12

-0.10

-0.08

-0.06

-0.04

-0.02

0

-0.140 1000

Typical Operating Characteristics (continued)(Circuit of Figure 2, VDCIN = 20V, charge current = 3A, 4 Li+ series cells, TA = +25°C, unless otherwise noted.)

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SWITCHING FREQUENCY vs. VIN - VBATT

MAX

1909

/MAX

8725

toc0

9

VIN - VBATT (V)

SWIT

CHIN

G FR

EQUE

NCY

(kHz

)

8642

50

100

150

200

250

300

350

400

450

500

00 10

IINP ERROR vs. INPUT CURRENT

MAX

1909

/MAX

8725

toc1

0

INPUT CURRENT (A)

IINP

(%)

3.02.50.5 1.0 1.5 2.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

00 3.5

CHARGERDISABLED

-3

-1

-2

1

0

2

3

1.5 2.52.0 3.0 3.5

INPUT CURRENT-LIMIT ACCURACY vs. VCLS

MAX

1909

/MAX

8725

toc1

4

VCLS (V)

INPU

T CU

RREN

T-LI

MIT

ACC

URAC

Y (%

)

-8

-4

-6

2

0

-2

6

4

8

1.5 3.0 3.52.0 2.5 4.0 4.5 5.0 5.5 6.0

IINP ACCURACY vs. INPUT CURRENT

MAX

1909

/MAX

8725

toc1

1

INPUT CURRENT (A)

IINP

ACCU

RACY

(%)

-2

0

-1

2

1

3

4

0.5 1.51.0 2.0 2.5 3.0

INPUT CURRENT-LIMIT ACCURACYvs. SYSTEM LOAD

MAX

1909

/MAX

8725

toc1

2

SYSTEM LOAD (A)

INPU

T CU

RREN

T-LI

MIT

ACC

URAC

Y (%

)

VBATT = 10V

VBATT = 13V

VBATT = 12VVBATT = 16V

ICHARGE = 3A

MAX1909 ONLY


INPUT CURRENT-LIMIT ACCURACYvs. SYSTEM LOAD

MAX

1909

/MAX

8725

toc1

3

SYSTEM LOAD (A)

INPU

T CU

RREN

T-LI

MIT

ACC

URAC

Y (%

)

3.02.50.5 1.0 1.5 2.0

-1

0

1

2

3

4

-20 3.5

VBATT = 16V VBATT = 12V

VBATT = 13V VBATT = 10V

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12 ______________________________________________________________________________________


PDL-PDS SWITCHING,AC ADAPTER INSERTION


100μs/div

10V

20V

10V

20V

10V

20V

0V

VWALLADAPTER

VSYSTEMLOAD, VPDS

VPDS

VPDL, VBATT

VPDLSYSTEM LOAD

VPDL

VPDS

PDS-PDL SWITCHOVER,WALL ADAPTER REMOVAL


500μs/div

10V

20V

0V

10V

20V

10V

20V

0V

VWALLADAPTER

VSYSTEMLOAD

VSYSTEMLOAD

VPDS

VPDL

VBATT

VPDL

PDS-PDL SWITCHOVER,BATTERY INSERTION


50μs/div

10V

15V

0V

5V

10V

15V

20V

5V

0V

VSYSTEM

VPDS

VPDL

VBATT

VPKDET

CONDITIONING MODEWALL ADAPTER = 18V

VPKPRES

PDL-PDS SWITCHING,BATTERY REMOVAL


10μs/div

10V

15V

0V

5V

10V

15V

20V

5V

0V

VSYSTEM

VPDS

VPDL

VBATT

CONDITIONING MODEWALL ADAPTER = 18V

VPKPRES

MAX8725 ONLY

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Pin Description

PIN NAME FUNCTION

1 DCIN DC Supply Voltage Input. Bypass DCIN with a 1μF capacitor to power ground.

2 LDO Device Power Supply. Output of the 5.4V linear regulator supplied from DCIN. Bypass with a 1μF capacitor.

3 ACIN AC Detect Input. This uncommitted comparator input can be used to detect the presence of the charger’s power source. The comparator’s open-drain output is the ACOK signal.

4 REF 4.2235V Voltage Reference. Bypass with a 1μF capacitor to GND.

GND MAX1909: Ground this pin. 5

PKPRES MAX8725: Pull PKPRES high to disable charging. Used for detecting presence of battery pack.

6 ACOK AC Detect Output. High-voltage open-drain output is high impedance when ACIN is greater than 2.048V. The ACOK output remains a high impedance when the MAX1909/MAX8725 are powered down.

7 MODE

Trilevel Input for Setting Number of Cells and Asserting the Conditioning Mode: MODE = GND; asserts conditioning mode. MODE = float; charge with 3 times the cell voltage programmed at VCTL. MODE = LDO; charge with 4 times the cell voltage programmed at VCTL.

8 IINP Input Current Monitor Output. The current delivered at the IINP output is a scaled-down replica of the system load current plus the input-referred charge current sensed across CSSP and CSSN inputs. The transconductance of (CSSP - CSSN) to IINP is 3mA/V.

9 CLS Source Current-Limit Input. Voltage input for setting the current limit of the input source.

10 ICTL Input for Setting Maximum Output Current

11 VCTL Input for Setting Maximum Output Voltage

12 CCI Output Current-Regulation Loop-Compensation Point. Connect 0.01μF to GND.

13 CCV Voltage-Regulation Loop-Compensation Point. Connect 10k in series with 0.1μF to GND.

14 CCS Input Current-Regulation Loop-Compensation Point. Use 0.01μF to GND.

15 GND Analog Ground

16 BATT Battery Voltage Feedback Input

17 CSIN Output Current-Sense Negative Input

18 CSIP Output Current-Sense Positive Input. Connect a current-sense resistor from CSIP to CSIN.

19 PGND Power Ground

20 DLO Low-Side Power-MOSFET Driver Output. Connect to low-side NMOS gate. When the MAX1909/MAX8725 are shut down, the DLO output is low.

21 DLOV Low-Side Driver Supply. Bypass with a 1μF capacitor to ground.

22 DHIV High-Side Driver Supply. Bypass with a 0.1μF capacitor to SRC.

23 DHI High-Side Power-MOSFET Driver Output. Connect to high-side PMOS gate. When the MAX1909/MAX8725 are shut down, the DHI output is high.

24 SRC Source Connection for Driver for PDS/PDL Switches. Bypass SRC to power ground with a 1μF capacitor.

25 CSSN Input Current Sense for Charger (Negative Input)

26 CSSP Input Current Sense for Charger (Positive Input). Connect a current-sense resistor from CSSP to CSSN.

27 PDS Power-Source PMOS Switch Driver Output. When the MAX1909/MAX8725 are powered down, the PDS output is pulled to SRC through an internal 1M resistor.

28 PDL System-Load PMOS Switch Driver Output. When the MAX1909/MAX8725 are powered down, the PDL output is pulled to ground through an internal 100k resistor.


______________________________________________________________________________________ 13

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14 ______________________________________________________________________________________

CSSP CSSN

LDO

DHI

DLOV

DLO

PGND

CSIP

CSINBATT

GND

DCIN

VCTL

ICTL

MODE

ACIN

ACOK

CLS

CCVCCI

CCS REF

GND

TOHOST

SYSTEM

BATT +

TEMPBATT -

BATTERY

AC ADAPTER

R6590kΩ

1% R7196kΩ

1% C51μF

D4

P3 RS10.01Ω

R510kΩ

C110.1μF

C100.01μF

C90.01μF C12

1μF

C422μF

N1

P1

C161μF

C131μF R13

33Ω

C122μF

GNDPGND

RS20.015Ω

TOSYSTEM LOAD

R81MΩ

LDO

OUTPUT

(INPUT I LIMIT: 7.5A)

OUTPUT VOLTAGE: 12.6V

CHARGE I LIMIT: 3.0APDS

PDL

SRC

LDO

REF

DHIV

C170.1μF

R4100kΩ

SRC

C221μF

R910kΩ

P2MAX1909MAX8725

PKPRES (MAX8725 ONLY)

L110μH

LDO

LDO

0.1μF0.1μF

Figure 1. Typical Operating Circuit Demonstrating Hardwired Control

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______________________________________________________________________________________ 15

CSSP CSSN

LDO

DHI

DLOV

DLO

PGND

CSIP

CSINBATT

GND

DCIN

VCTL

ICTL

ACINMODE

ACOK

IINP

CCV

CCI

CCS REFAVDD/REF

SCLSDA

GND

HOST

BATT +

TEMPSDASCL

BATT -

SMARTBATTERY

AC ADAPTER

R6590kΩ

1% R7196kΩ

1% C51μF

D4

P3 P4 RS10.01Ω

R510kΩ

C110.1μF

C100.01μF

C90.01μF

C121μF

C422μF

N1

P1

C161μF

C131μF R13

33Ω

C122μF

GNDPGND

RS20.015Ω

TOSYSTEM LOAD

R81MΩ

LDO

OUTPUTS

OUTPUT

INPUT

A/D INPUT

OPEN-DRAIN

OUTPUT VOLTAGE: 16.8V

PDS

PDL

SRC

LDO

CLSREF

DHIV

C170.1μF

SRC

C151μF

R2110kΩ

P2MAX1909MAX8725

C140.1μF

R910kΩ

R19, R2010kΩ

(INPUT I LIMIT: 7.5A)L110μH

D/A OUTPUT

0.1μF0.1μF

LDO

PKPRES (MAX8725 ONLY)

Figure 2. Smart-Battery Charger Circuit Demonstrating Operation with a Host Microcontroller

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16 ______________________________________________________________________________________

CHGLOGIC

5.4VLINEAR

REGULATOR

4.2235VREFERENCE

LDO

DCIN

REF

ACOK

2.048V

IINP

DC-DCCONVERTER

PDS

DHI

PDL

DRIVER

DRIVER

DRIVER

DRIVER

DLOV

DLO

PGND

LVCBATT

MODE

VCTL

CSIP

CSIN

LEVELSHIFTER

LEVELSHIFTER

CSSP

CSSN

ICTL

CLS

SRDY

GND

GND

GMV

GMI

GMS

CCS

CCI

CCV

CELL SELECTLOGIC AND

BATTERY VOLTAGE-DIVIDER

ACIN

0.9 * LDORDY

SRC

SWITCH LOGIC

R

R9R

REF

MODE

DHIV

DCIN

0.8V

Gm

BATT

PKPRES

3.0V/CELL

BATT_UV

ICTLOK

PACK_ON

CHG

SRC

MAX1909MAX8725

SRC-10V

100kΩ

MAX1909 ONLY

MAX8725 ONLY

Figure 3. Functional Diagram

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______________________________________________________________________________________ 17

Detailed DescriptionThe MAX1909/MAX8725 include all of the functionsnecessary to charge Li+, NiMH, and NiCd batteries. Ahigh-efficiency, synchronous-rectified step-down DC-DC converter is used to implement a precision con-stant-current, constant-voltage charger with inputcurrent limiting. The DC-DC converter uses external p-channel/n-channel MOSFETs as the buck switch andsynchronous rectifier to convert the input voltage to therequired charge current and voltage. The charge cur-rent and input current-limit sense amplifiers have low-input-referred offset errors and can use small-valuesense resistors. The MAX1909/MAX8725 feature a volt-age-regulation loop (CCV) and two current-regulationloops (CCI and CCS). The CCV voltage-regulation loopmonitors BATT to ensure that its voltage never exceedsthe voltage set by VCTL. The CCI battery current-regu-lation loop monitors current delivered to BATT to ensurethat it never exceeds the current limit set by ICTL. Athird loop (CCS) takes control and reduces the chargecurrent when the sum of the system load and the input-referred charge current exceeds the power source cur-rent limit set by CLS. Tying CLS to the referencevoltage provides a 7.5A input current limit with a 10mΩsense resistor.

The ICTL, VCTL, and CLS analog inputs set the chargecurrent, charge voltage, and input current limit, respec-tively. For standard applications, internal set points forICTL and VCTL provide a 3A charge current using a15mΩ sense resistor and a 4.2V per-cell charge volt-age. The variable for controlling the number of cells isset with the MODE input. The MAX8725 includes aPKPRES input used for battery-pack detection.

Based on the presence or absence of the AC adapter,the MAX1909/MAX8725 automatically provide an open-drain logic output signal ACOK and select the appropri-ate source for supplying power to the system. Ap-channel load switch controlled from the PDL output anda similar p-channel source switch controlled from the PDSoutput are used to implement this function. Using theMODE control input, the MAX1909/MAX8725 can be pro-grammed to perform a relearning, or conditioning, cyclein which the battery is isolated from the charger and com-pletely discharged through the system load. When thebattery reaches 100% depth of discharge, it is rechargedto full capacity.

The circuit shown in Figure 1 demonstrates a simplehardwired application, while Figure 2 shows a typicalapplication for smart-battery systems with variablecharge current and source switch configuration that sup-ports battery conditioning. Smart-battery systems typical-ly use a host µC to achieve this added functionality.

Setting the Charge VoltageThe MAX1909/MAX8725 use a high-accuracy voltageregulator for charge voltage. The VCTL input adjuststhe battery output voltage. In default mode (VCTL =LDO), the overall accuracy of the charge voltage is±0.5%. VCTL is allowed to vary from 0 to 3.6V, whichprovides a 10% adjustment range of the battery volt-age. Limiting the adjustment range reduces the sensi-t ivity of the charge voltage to external resistortolerances from ±1% to ±0.05%. The overall accuracyof the charge voltage is better than ±1% when using±1% resistors to divide down the reference to establishVCTL. The per-cell battery termination voltage is a func-tion of the battery chemistry and construction. Consultthe battery manufacturer to determine this voltage. Thebattery voltage is calculated by the equation:

where VREF = 4.2235V, and CELL is the number of cellsselected with the MAX1909/MAX8725s’ trilevel MODEcontrol input. When MODE is tied to the LDO output,CELL = 4. When MODE is left floating, CELL = 3. WhenMODE is tied to ground, the charger enters condition-ing mode, which is used to isolate the battery from thecharger and discharge it through the system load. Seethe Conditioning Mode section. The internal error ampli-fier (GMV) maintains voltage regulation (see Figure 3for the Functional Diagram). The voltage-error amplifieris compensated at CCV. The component values shownin Figures 1 and 2 provide suitable performance formost applications. Individual compensation of the volt-age regulation and current-regulation loops allow foroptimal compensation. See the Compensation section.

Setting the Charge CurrentThe voltage on the ICTL input sets the maximum voltage across current-sense resistor RS2, which in turndetermines the charge current. The full-scale differen-tial voltage between CSIP and CSIN is 75mV; thus, for a0.015Ω sense resistor, the maximum charge current is5A. In default mode (ICTL = LDO), the sense voltage is45mV with an overall accuracy of ±5%. The charge cur-rent is programmed with ICTL using the equation:

IRS

VVCHG

ICTL= ×0 075

2 3 6.

.

V CELL VV V

BATT REFVCTL= +

⎛⎝⎜

⎞⎠⎟

⎛

⎝⎜

⎞

⎠⎟

−1 89 52

..

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18 ______________________________________________________________________________________

The input range for ICTL is 0 to 3.6V on the MAX1909,and 0 to 3.2V on the MAX8725. The charger shuts downif ICTL is forced below 0.75V for the MAX1909 and 0.06Vfor the MAX8725. When choosing current-sense resistorRS2, note that it must have a sufficient power rating tohandle the full-load current. The sense resistor’s I2Rpower loss reduces charger efficiency. Adjusting ICTL todrop the voltage across the current-sense resistorimproves efficiency, but may degrade accuracy due tothe current-sense amplifier’s input offset error. Thecharge-current error amplifier (GMI) is compensated atthe CCI pin. See the Compensation section.

Conditioning ChargeThe MAX1909 includes a battery voltage comparatorthat allows a conditioning charge of overdischarged Li+battery packs. If the battery-pack voltage is less than3.1V x the number of cells programmed by MODE, theMAX1909 charges the battery with 300mA current whenusing sense resistor RS2 = 0.015Ω. After the batteryvoltage exceeds the conditioning charge threshold, theMAX1909 resumes full-charge mode, charging to theprogrammed voltage and current limits. The MAX8725does not provide automatic support for providing aconditioning charge. To configure the MAX8725 to pro-vide a conditioning charge current, ICTL should bedirectly driven.

Setting the Input Current LimitThe total input current, from a wall cube or other DCsource, is the sum of the system supply current and thecurrent required by the charger. The MAX1909/MAX8725reduce the source current by decreasing the charge cur-rent when the input current exceeds the set input currentlimit. This technique does not truly limit the input current.As the system supply current rises, the available chargecurrent drops proportionally to zero. Thereafter, the totalinput current can increase without limit.

An internal amplifier compares the differential voltagebetween CSSP and CSSN to a scaled voltage set withthe CLS input. VCLS can be driven directly or set with aresistive voltage-divider between REF and GND.Connect CLS to REF to set the input current-limit sensevoltage to the maximum value of 75mV. Calculate theinput current as follows:

VCLS determines the reference voltage of the GMSerror amplifier. Sense resistor RS1 sets the maximumallowable source current. Once the input current limit isreached, the charge current is decreased linearly untilthe input current is below the desired threshold.

Duty cycle affects the accuracy of the input currentlimit. AC load current also affects accuracy (see theTypical Operating Characteristics). Refer to theMAX1909/MAX8725 EV kit data sheet for more detailson reducing the effects of switching noise.

When choosing the current-sense resistor RS1, carefullycalculate its power rating. Take into account variationsin the system’s load current and the overall accuracy ofthe sense amplifier. Note that the voltage drop acrossRS1 contributes additional power loss, which reducesefficiency.

System currents normally fluctuate as portions of thesystem are powered up or put to sleep. Without inputcurrent regulation, the input source must be able todeliver the maximum system current and the maximumcharger input current. By using the input current-limitcircuit, the output current capability of the AC walladapter can be lowered, reducing system cost.

Current MeasurementThe MAX1909/MAX8725 include an input current monitorIINP. The current delivered at the IINP output is a scaled-down replica of the system load current plus the input-referred charge current that is sensed across CSSP andCSSN inputs. The output voltage range is 0 to 3V. The voltage of IINP is proportional to the input currentaccording to the following equation:

VIINP = ISOURCE RS1 GIINP R9

where ISOURCE is the DC current supplied by the ACadapter power, GIINP is the transconductance of IINP (3mA/V typ), and R9 is the resistor connected betweenIINP and ground.

Leave the IINP pin unconnected if not used.

LDO RegulatorLDO provides a 5.4V supply derived from DCIN andcan deliver up to 10mA of extra load current. The low-side MOSFET driver is powered by DLOV, which mustbe connected to LDO as shown in Figure 1. LDO alsosupplies the 4.2235V reference (REF) and most of thecontrol circuitry. Bypass LDO with a 1µF capacitor.

Shutdown and Charge Inhibit (PKPRES)When the AC adapter is removed, the MAX1909/MAX8725 shut down to a low-power state that does notsignificantly load the battery. Under these conditions, amaximum of 6µA is drawn from the battery through thecombined load of the SRC, CSSP, CSSN, CSIP, CSIN,and BATT inputs. The charger enters this low-power statewhen DCIN falls below the undervoltage-lockout (UVLO)threshold of 7V. The PDS switch turns off, the PDL switchturns on, and the system runs from the battery.

IRS

VVIN

CLS

REF= ×

0 0751

.

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______________________________________________________________________________________ 19

The body diode of the PDL switch prevents the voltageon the power source output from collapsing.

Charging can also be inhibited by driving ICTL below0.035V, which suspends switching and pulls CCI, CCS,and CCV to ground. The PDS and PDL drivers, LDO,input current monitor, and control logic (ACOK) allremain active in this state. Approximately 3mA of sup-ply current is drawn from the AC adapter and 3µA(max) is drawn from the battery to support these functions.

In smart-battery systems, PKPRES is usually driven from avoltage-divider formed with a low-value resistor or PTCthermistor inside the battery pack and a local resistivepullup. This arrangement automatically detects the pres-ence of a battery. The MAX8725 threshold voltage is 55%of VLDO, with hysteresis of 1% VLDO to prevent erratictransitions.

AC Adapter Detection and Power-Source Selection

The MAX1909/MAX8725 include a hysteretic compara-tor that detects the presence of an AC power adapterand automatically delivers power to the system loadfrom the appropriate available power source. When theadapter is present, the open-drain ACOK outputbecomes high impedance. The switch threshold atACIN is 2.048V. Use a resistive voltage-divider from theadapter’s output to the ACIN pin to set the appropriatedetection threshold. When charging, the battery is iso-lated from the system load with the p-channel PDLswitch, which is biased off. When the adapter is absent,the drives to the switches change state in a fast break-before-make sequence. PDL begins to turn on 7.5µsafter PDS begins to turn off.

The threshold for selecting between the PDL and PDSswitches is set based on the voltage differencebetween the DCIN and the BATT pins. If this voltagedifference drops below 100mV, the PDS is switched offand PDL is switched on. Under these conditions, theMAX1909/MAX8725 are completely powered down.The PDL switch is kept on with a 100kΩ pulldown resis-tor when the charger is powered down through ICTL orPKPRES, or when the AC adapter is removed.

The drivers for PDL and PDS are fully integrated. The pos-itive bias inputs for the drivers connect to the SRC pin andthe negative bias inputs connect to a negative regulatorreferenced to SRC. With this arrangement, the drivers canswing from SRC to approximately 10V below SRC.

Conditioning ModeThe MAX1909/MAX8725 can be programmed to per-form a conditioning cycle to calibrate the battery’s fuelgauge. This cycle consists of isolating the battery fromthe charger and discharging it through the system load.When the battery reaches 100% depth of discharge, itis then recharged. Driving the MODE pin low places theMAX1909/MAX8725 in conditioning mode, which stopsthe charger from switching, turns the PDS switch off,and turns the PDL switch on.

To utilize the conditioning mode function, the configura-tion of the PDS switch must be changed to two source-connected FETs to prevent the AC adapter from sup-plying current to the system through the MOSFET’sbody diode. See Figure 2. The SRC pin must be con-nected to the common source node of the back-to-backFETs to properly drive the MOSFETs.

It is essential to alert the user that the system is performing a conditioning cycle. If the user termi-nates the cycle prematurely, the battery can be dis-charged even though the system was running off theAC adapter for a substantial period of time. If the ACadapter is in fact removed during conditioning, theMAX1909/MAX8725 keep the PDL switch on and thecharger remains off as it would in normal operation.

In the MAX8725, if the battery is removed during condi-tioning mode, the PKPRES control overrides condition-ing mode. When MODE is grounded and PKPRES goeshigh, the PDS switch starts turning on within 7.5µs andthe system is powered from the AC adapter.

In the MAX1909, disable conditioning mode before thebattery is overdischarged or removed.

DC-DC ConverterThe MAX1909/MAX8725 employ a buck regulator with aPMOS high-side switch and a low-side NMOS synchro-nous rectifier. The MAX1909/MAX8725 feature a pseu-do-fixed-frequency, cycle-by-cycle current-modecontrol scheme. The off-time is dependent upon VDCIN,VBATT, and a time constant, with a minimum tOFF of300ns. The MAX1909/MAX8725 can also operate in discontinuous conduction for improved light-load effi-ciency. The operation of the DC-DC controller is deter-mined by the following four comparators as shown inFigure 4:

• CCMP: Compares the control point (lowest voltageclamp (LVC)) against the charge current (CSI). Thehigh-side MOSFET on-time is terminated if the CCMPoutput is high.

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20 ______________________________________________________________________________________

COMP

IMAX

IMIN

ZCMP

CSS20X

DHI

DLO

GMS

GMILVC

CSI20X

GMV

CLS

ICTL

VCTL

1.94V

0.15V

0.1V

LVC

AC ADAPTER

CSSP CSSN

R

S

Q

Q

DHI

DLO

CSIP

CSIN

BATT

CCSCCICCV

TOFF

RCCV

CCV CCI CCS

COUT

MAX1909MAX8725

Figure 4. DC-DC Converter Functional Diagram

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______________________________________________________________________________________ 21

• IMIN: Compares the control point (LVC) against0.15V (typ). If IMIN output is low, then a new cyclecannot begin. This comparator determines whetherthe regulator operates in discontinuous mode.

• IMAX: Compares the charge current (CSI) to theinternally fixed cycle-by-cycle current limit. The current-sense voltage limit is 97mV. With RS2 =0.015Ω, this corresponds to 6A. The high-side MOSFET on-time is terminated if the IMAX output ishigh and a new cycle cannot begin until IMAX goeslow. IMAX protects against sudden overcurrentfaults.

• ZCMP: Compares the charge current (CSI) to 333mA(RS2 = 0.015Ω). The current-sense voltage thresholdis 5mV. If ZCMP output is high, then both MOSFETsare turned off. The ZCMP comparator terminates theswitch on-time in discontinuous mode.

CCV, CCI, CCS, and LVC Control BlocksThe MAX1909/MAX8725 control charge voltage (CCVcontrol loop), charge current (CCI control loop), or input current (CCS control loop), depending on the operatingconditions. The three control loops, CCV, CCI, and CCS,are brought together internally at the LVC amplifier. Theoutput of the LVC amplifier is the feedback control signal for the DC-DC controller. The minimum voltage at CCV, CCI, or CCS appears at the output ofthe LVC amplifier and clamps the other two controlloops to within 0.3V above the control point. Clampingthe other two control loops close to the lowest controlloop ensures fast transition with minimal overshootwhen switching between different control loops (see theCompensation section).

Continuous Conduction ModeWith sufficient battery current loading, the MAX1909/MAX8725s’ inductor current never reaches zero, whichis defined as continuous conduction mode. If the BATTvoltage is within the following range:

3.1V (number of cells) < VBATT < (0.88 VDCIN)

the regulator is not in dropout and switches at fNOM =400kHz. The controller starts a new cycle by turning onthe high-side p-channel MOSFET and turning off thelow-side n-channel MOSFET. When the charge currentis greater than the control point (LVC), CCMP goes highand the off-time is started. The off-time turns off thehigh-side p-channel MOSFET and turns on the low-siden-channel MOSFET. The operating frequency is gov-erned by the off-time and is dependent upon VDCINand VBATT. The off-time is set by the following equation:

where fNOM = 400kHz:

These equations describe the controller’s pseudo-fixed-frequency performance over the most common operat-ing conditions.

At the end of the fixed off-time, the controller can initiatea new cycle if the control point (LVC) is greater than0.15V (IMIN = high) and the peak charge current is lessthan the cycle-by-cycle limit (IMAX = low). If the chargecurrent exceeds IMAX, the on-time is terminated by theIMAX comparator.

If during the off-time the inductor current goes to zero,ZCMP = high, both the high- and low-side MOSFETsare turned off until another cycle is ready to begin. Thiscondition is discontinuous conduction. See theDiscontinuous Conduction section.

There is a minimum 0.3µs off-time when the (VDCIN -VBATT) differential becomes too small. If VBATT ≥ 0.88 xVDCIN, then the threshold for minimum off-time isreached and the tOFF is fixed at 0.3µs. The switchingfrequency in this mode varies according to the equation:

Discontinuous ConductionThe MAX1909/MAX8725 enter discontinuous-conduc-tion mode when the output of the LVC control point fallsbelow 0.15V. For RS2 = 0.015Ω, this corresponds to0.5A:

IV

RSAMIN =

×=

0 1520 2

0 5.

.

f

tV

V VOFFBATT

CSSN BATT

=

−+

⎛

⎝⎜

⎞

⎠⎟

1

1

ft tON OFF

=+

1

where IV t

LRIPPLEBATT OFF =

×

tL I

V VONRIPPLE

CSSN BATT=

×

−

tf

V VVOFF

NOM

CSSN BATT

CSSN=

−1

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22 ______________________________________________________________________________________

In discontinuous mode, a new cycle is not started untilthe LVC voltage rises above 0.15V. Discontinuous-mode operation can occur during conditioning chargeof overdischarged battery packs, when the charge cur-rent has been reduced sufficiently by the CCS controlloop, or when the charger is in constant voltage modewith a nearly full battery pack.

CompensationThe charge voltage, charge current, and input current-limit regulation loops are compensated separately andindependently at the CCV, CCI, and CCS pins.

CCV Loop CompensationThe simplified schematic in Figure 5 is sufficient todescribe the operation of the MAX1909/MAX8725 whenthe voltage loop (CCV) is in control. The required com-pensation network is a pole-zero pair formed with CCVand RCV. The pole is necessary to roll off the voltageloop’s response at low frequency. The zero is necessaryto compensate the pole formed by the output capacitorand the load. RESR is the equivalent series resistance(ESR) of the charger output capacitor (COUT). RL is theequivalent charger output load, where RL = ΔVBATT /ΔICHG. The equivalent output impedance of the GMVamplifier, ROGMV, is greater than 10MΩ. The voltageloop transconductance (GMV = ICCV / VBATT) dependson the MODE input, which determines the number ofcells. GMV = 0.125mA/mV for 4 cells and GMV =0.167mA/mV for 3 cells. The DC-DC converter transcon-ductance is dependent upon the charge current-senseresistor RS2:

where ACSI = 20, and RS2 = 0.015Ω in the TypicalOperating Circuits (Figures 1 and 2), so GMOUT =3.33A/V.

The loop transfer function is:

LTF GMR sC R

sC R

RsC R

G sC R

OUTOGMV CV CV

CV OGMV

L

OUT LMV OUT ESR

= ×× + ×( )

+ ×( )×

+ ×( )+ ×( )

1

1

11

GMA RSOUT

CSI=

×

12

CCV

COUT

RCV

RLRESR

ROGMV

CCV

BATT

GMV

REF

GMOUT

Figure 5. CCV Loop Diagram

NO. NAME CALCULATION DESCRIPTION

1 CCV pole

Lowest frequency pole created by CCV and GMV’s finite outputresistance. Since ROGMV is very large and not well controlled, theexact value for the pole frequency is also not well controlled(ROGMV > 10MΩ).

2 CCV zero

Voltage-loop compensation zero. If this zero is at the samefrequency or lower than the output pole fP_OUT, then the looptransfer function approximates a single pole response near thecrossover frequency. Choose CCV to place this zero at least onedecade below crossover to ensure adequate phase margin.

3 Output poleOutput pole formed with the effective load resistance RL and theoutput capacitance COUT. RL influences the DC gain but does notaffect the stability of the system or the crossover frequency.

4 Output zero

Output ESR Zero. This zero can keep the loop from crossing unitygain if fZ_OUT is less than the desired crossover frequency;therefore, choose a capacitor with an ESR zero greater than thecrossover frequency.

Table 1. Poles and Zeros of the Voltage-Loop Transfer Function

fR CP CV

OGMV CV_ =

×

12π

fR CZ CV

CV CV_ =

×

12π

fR CP OUT

L OUT_ =

×

12π

fR CZ OUT

ESR OUT_ =

×

12π

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The poles and zeros of the voltage-loop transfer functionare listed from lowest frequency to highest frequency inTable 1.

Near crossover, CCV has a much lower impedancethan ROGMV. Since CCV is in parallel with ROGMV, CCVdominates the parallel impedance near crossover.Additionally, RCV has a much higher impedance thanCCV and dominates the series combination of RCV andCCV, so:

COUT also has a much lower impedance than RL nearcrossover, so the parallel impedance is mostly capaci-tive and:

If RESR is small enough, its associated output zero hasa negligible effect near crossover and the loop-transferfunction can be simplified as follows:

Setting the LTF = 1 to solve for the unity-gain frequencyyields:

For stability, choose a crossover frequency lower than1/10th of the switching frequency. Choosing acrossover frequency of 30kHz and solving for RCVusing the component values listed in Figure 1 yields:

MODE = LDO (4 cells)

GMV = 0.125µA/mV

COUT = 22µF

VBATT = 16.8V

RL = 0.2Ω

GMOUT = 3.33A/V

fCO_CV = 30kHz

fOSC = 400kHz

To ensure that the compensation zero adequately can-cels the output pole, select fZ_CV ≤ fP_OUT:

CCV ≥ (RL/RCV) COUT

where CCV ≥ 4nF (assuming 4 cells and 4A maximumcharge current).

Figure 6 shows the Bode plot of the voltage-loop fre-quency response using the values calculated above.

CCI Loop CompensationThe simplified schematic in Figure 7 is sufficient todescribe the operation of the MAX1909/MAX8725 whenthe battery current loop (CCI) is in control. Since theoutput capacitor’s impedance has little effect on theresponse of the current loop, only a single pole isrequired to compensate this loop. ACSI is the internalgain of the current-sense amplifier. RS2 is the chargecurrent-sense resistor, RS2 = 15mΩ. ROGMI is theequivalent output impedance of the GMI amplifier,which is greater than 10MΩ. GMI is the charge-currentamplifier transconductance = 1µA/mV. GMOUT is theDC-DC converter transconductance = 3.3A/V.

The loop transfer function is given by:

LTF GM A RS GMIR

sR COUT CSIOGMI

OGMI CI= × × ×

+ ×2

1

RC f

GMV GMkCV

OUT CO CV

OUT=

× ×

×=

210

π _ Ω

fCO CV GM GMVR

COUTCV

OUT_

= ×

×

⎛

⎝⎜

⎞

⎠⎟2π

LTF GMR

sCGMVOUT

CV

OUT= ×

RsC R sC

L

OUT L OUT11

+ ×( )≅

R sC R

sC RROGMV CV CV

CV OGMVCV

× + ×( )+ ×( )

≅1

1

FREQUENCY (Hz)

MAG

NITU

DE (d

B)

PHAS

E (D

EGRE

ES)

100k10k1k100101

-20

0

20

40

60

80

-40

-90

-45

0

-1350.1 1M

MAGPHASE

Figure 6. CCV Loop Response

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24 ______________________________________________________________________________________

This describes a single-pole system. Since:

the loop transfer function simplifies to:

The crossover frequency is given by:

For stability, choose a crossover frequency lower than1/10th of the switching frequency:

CCI = GMI / (2π fO_CI)

Choosing a crossover frequency of 30kHz and using thecomponent values listed in Figure 1 yields CCI > 5.4nF.Values for CCI greater than 10 times the minimum valuemay slow down the current-loop response excessively.Figure 8 shows the Bode plot of the current-loop fre-quency response using the values calculated above.

CCS Loop CompensationThe simplified schematic in Figure 9 is sufficient todescribe the operation of the MAX1909/MAX8725 whenthe input current-limit loop (CCS) is in control. Since theoutput capacitor’s impedance has little effect on theresponse of the input current-limit loop, only a singlepole is required to compensate this loop. ACSS is theinternal gain of the current-sense amplifier. RS1 is theinput current-sense resistor; RS1 = 10mΩ in the typicaloperating circuits. ROGMS is the equivalent outputimpedance of the GMS amplifier, which is greater than10MΩ. GMS is the input current amplifier transconduc-tance = 1µA/mV. GMIN is the DC-DC converter’s input-referred transconductance = (1/D) GMOUT = (1/D)3.3A/V.

fGMI

CCO CICI

_ =2π

LTF GMIR

sR COGMI

OGMI CI=

+ ×1

GMA RSOUT

CSI=

×

12

FREQUENCY (Hz)

MAG

NITU

DE (d

B)

100k1k10

-20

0

20

40

60

100

80

-40

-45

0

-900.1

MAGPHASE

Figure 8. CCI Loop Response

CCS ROGMS

GMS

CSSCLS

CCS

CSSP

RS1

CSSN

GMIN

SYSTEMLOAD

ADAPTERINPUT

Figure 9. CCS Loop Diagram

CCI ROGMI

CCIGMI

CSI

ICTL

GMOUTCSIP

RS2

CSIN

Figure 7. CCI Loop Diagram

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The loop transfer function is given by:

Since:

the loop transfer function simplifies to:

The crossover frequency is given by:

For stability, choose a crossover frequency lower than1/10th the switching frequency:

CCS = GMS / (2π fCO_CS)

Choosing a crossover frequency of 30kHz and usingthe component values listed in Figure 1 yields CCS >5.4nF. Values for CCS greater than 10 times the mini-mum value may slow down the input current-loopresponse excessively. Figure 10 shows the Bode plot ofthe input current-limit loop frequency response usingthe values calculated above.

MOSFET DriversThe DHI and DLO outputs are optimized for drivingmoderately-sized power MOSFETs. The MOSFET drivecapability is the same for both the low-side and high-side switches. This is consistent with the variable dutyfactor that occurs in the notebook computer environ-ment where the battery voltage changes over a widerange. An adaptive dead-time circuit monitors the DLOoutput and prevents the high-side FET from turning onuntil DLO is fully off. There must be a low-resistance,low-inductance path from the DLO driver to the MOSFET gate for the adaptive dead-time circuit to workproperly. Otherwise, the sense circuitry in theMAX1909/MAX8725 interpret the MOSFET gate as “off”while there is still charge left on the gate. Use veryshort, wide traces measuring 1.25mm to 2.5mm if theMOSFET is 25mm from the device. Unlike the DLO out-put, the DHI output uses a fixed-delay 50ns time to pre-vent the low-side FET from turning on until DHI is fullyoff. The same layout considerations should be used forrouting the DHI signal to the high-side FET.

Since the transition time for a p-channel switch can bemuch longer than an n-channel switch, the dead timeprior to the high-side PMOS turning on is more pro-nounced than in other synchronous step-down regula-tors, which use high-side n-channel switches. On thehigh-to-low transition, the voltage on the inductor’s“switched” terminal flies below ground until the low-sideswitch turns on. A similar dead-time spike occurs onthe opposite low-to-high transition. Depending upon themagnitude of the load current, these spikes usuallyhave a minor impact on efficiency.

The high-side driver (DHI) swings from SRC to 5Vbelow SRC and typically sources 0.9A and sinks 0.5Afrom the gate of the p-channel FET. The internal pull-high transistors that drive DHI high are robust, with a2.0Ω (typ) on-resistance.

The low-side driver (DLO) swings from DLOV to groundand typically sources 0.5A and sinks 0.9A from the gateof the n-channel FET. The internal pulldown transistorsthat drive DLO low are robust, with a 1.0Ω (typ) on-resistance. This helps prevent DLO from being pulledup when the high-side switch turns on, due to capaci-tive coupling from the drain to the gate of the low-sideMOSFET. This places some restrictions on the FETsthat can be used. Using a low-side FET with smallergate-to-drain capacitance can prevent these problems.

fGMS

CCO CSCS

_ =2π

LTF GMSR

sR COGMS

OGMS CS=

+ ×1

GMA RSIN

CSS=

×

11

LTF GM A RS GMSR

sR CIN CSSOGMS

OGMS CS= × × ×

+ ×1

1

FREQUENCY (Hz)

MAG

NITU

DE (d

B)

100k 10M1k10

-20

0

20

40

60

100

80

-40

-45

0

-900.1

MAGPHASE

PHAS

E (D

EGRE

ES)

Figure 10. CCS Loop Response

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26 ______________________________________________________________________________________

Design ProcedureTable 2 lists the recommended components and refersto the circuit of Figure 2. The following sectionsdescribe how to select these components.

MOSFET SelectionMOSFETs P2 and P3 (Figure 1) provide power to thesystem load when the AC adapter is inserted. Thesedevices may have modest switching speeds, but mustbe able to deliver the maximum input current as set byRS1. As always, care should be taken not to exceed thedevice’s maximum voltage ratings or the maximumoperating temperature.

The p-channel/n-channel MOSFETs (P1, N1) are theswitching devices for the buck controller. The guidelines

for these devices focus on the challenge of obtaining highload-current capability when using high-voltage (>20V)AC adapters. Low-current applications usually requireless attention. The high-side MOSFET (P1) must be ableto dissipate the resistive losses plus the switching lossesat both VDCIN(MIN) and VDCIN(MAX).

Ideally, the losses at VDCIN(MIN) should be roughly equalto losses at VDCIN(MAX), with lower losses in between. Ifthe losses at VDCIN(MIN) are significantly higher than thelosses at VDCIN(MAX), consider increasing the size of P1.Conversely, if the losses at VDCIN(MAX) are significantlyhigher than the losses at VDCIN(MIN), consider reducingthe size of P1. If DCIN does not vary over a wide range,the minimum power dissipation occurs where the resistivelosses equal the switching losses.

REFERENCE QTY DESCRIPTION

C1, C4 2

22µF ±20%, 35V E-size low-ESRtantalum capacitorsAVX TPSE226M035R0300Kemet T495X226M035AS

C5, C15 2

1µF ±10%, 25V, X7R ceramic capacitors(1206)Murata GRM31MR71E105KTaiyo Yuden TMK316BJ105KLTDK C3216X7R1E105K

C9, C10 2

0.01µF ±10%, 25V, X7R ceramiccapacitors (0402)Murata GRP155R71E103KTDK C1005X7R1E103K

C11, C14,C17

3

0.1µF ±10%, 25V, X7R ceramiccapacitors (0603)Murata GRM188R71E104KTDK C1608X7R1E104K

C12, C13,C16

3

1µF ±10%, 6.3V, X5R ceramiccapacitors (0603)Murata GRM188R60J105KTaiyo Yuden JMK107BJ105KATDK C1608X5R1A105K

D4 1

Schottky diode, 0.5A, 30V SOD-123Diodes Inc. B0530WGeneral Semiconductor MBR0530ON Semiconductor MBR0530

D5 125V ±1% zener diodeCMDZ5253B

L1 110µH, 4.4A inductorSumida CDRH104R-100NCTOKO 919AS-100M

Table 2. Recommended ComponentsREFERENCE QTY DESCRIPTION

N1/P1 1

Dual n- and p-channel MOSFETs, 7A,30V and -5A, -30V, 8-pin SO, MOSFETFairchild FDS8958A orSingle n-channel MOSFETs, +13.5A,+30V FDS6670S andSingle p-channel MOSFETs, -13.5A,-30V FDS66709Z

P2, P3, P4 3Single, p-channel, -11A, -30V, 8-pin SOMOSFETsFairchild FDS6675

R4 1 100kΩ, ±5% resistor (0603)

R5, R9, R21 2 10kΩ ±1% resistors (0603)

R6 1 590kΩ ±1% resistor (0603)

R7 1 196kΩ ±1% resistor (0603)

R8 1 1MΩ ±5% resistor (0603)

R11 1 1kΩ ±5% resistor (0603)

R16 1 33Ω ±5% resistor (0603)

R19, R20 2 10kΩ ±5% resistors (0603)

RS1 10.01Ω ±1%, 0.5W sense resistor (2010)Vishay Dale WSL2010 0.010 1.0%IRC LRC-LR2010-01-R010-F

RS2 10.015Ω ±1%, 0.5W sense resistor (2010)Vishay Dale WSL2010 0.015 1.0%IRC LRC-LR2010-01-R015-F

U1 1MAX1909ETI/MAX8725ETI (28-pin thinQFN-EP)

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______________________________________________________________________________________ 27

Choose a low-side MOSFET that has the lowest possi-ble on-resistance (RDS(ON)), comes in a moderate-sized package, and is reasonably priced. Make surethat the DLO gate driver can supply sufficient current tosupport the gate charge and the current injected intothe parasitic gate-to-drain capacitor caused by thehigh-side MOSFET turning on; otherwise, cross-con-duction problems can occur.

The MAX1909/MAX8725 have an adaptive dead-time cir-cuit that prevents the high-side and low-side MOSFETsfrom conducting at the same time (see the MOSFETDrivers section). Even with this protection, it is still possi-ble for delays internal to the MOSFET to prevent oneMOSFET from turning off when the other is turned on.

Select devices that have low turn-off times. To be conservative, make sure that P1(tDOFF(MAX)) -N1(tDON(MIN)) < 40ns. Failure to do so may result inefficiency-killing shoot-through currents. If delay mis-match causes shoot-through currents, consider addingextra capacitance from gate to source on N1 to slowdown its turn-on time.

MOSFET Power DissipationWorst-case conduction losses occur at the duty factorextremes. For the high-side MOSFET, the worst-casepower dissipation (PD) due to resistance occurs at theminimum supply voltage:

Generally, a small high-side MOSFET is desired toreduce switching losses at high input voltages.However, the RDS(ON) required to stay within packagepower-dissipation limits often limits how small the MOSFET can be. The optimum occurs when the switch-ing (AC) losses equal the conduction (I2RDS(ON)) losses. High-side switching losses do not usuallybecome an issue until the input is greater than approxi-mately 15V. Switching losses in the high-side MOSFETcan become an insidious heat problem when maximumAC adapter voltages are applied, due to the squaredterm in the CV2 f switching-loss equation. If the high-side MOSFET that was chosen for adequate RDS(ON) atlow supply voltages becomes extraordinarily hot whensubjected to VDCIN(MAX), then choose a MOSFET withlower losses. Calculating the power dissipation in P1due to switching losses is difficult since it must allow fordifficult quantifying factors that influence the turn-onand turn-off times. These factors include the internalgate resistance, gate charge, threshold voltage, sourceinductance, and PC board layout characteristics. The

following switching-loss calculation provides only a veryrough estimate and is no substitute for breadboardevaluation, preferably including a verification using athermocouple mounted on P1:

where CRSS is the reverse transfer capacitance of P1,and IGATE is the peak gate-drive source/sink current.

For the low-side MOSFET (N1), the worst-case powerdissipation always occurs at maximum input voltage:

Choose a Schottky diode (D1, Figure 2) with a forwardvoltage low enough to prevent the N1 MOSFET bodydiode from turning on during the dead time. As a gen-eral rule, a diode with a DC current rating equal to 1/3rdthe load current is sufficient. This diode is optional andcan be removed if efficiency is not critical.

Inductor SelectionThe charge current, ripple, and operating frequency(off-time) determine the inductor characteristics.Inductor L1 must have a saturation current rating of atleast the maximum charge current plus 1/2 of the ripplecurrent (ΔIL):

ISAT = ICHG + (1/2) ΔIL

PD NVV

IRBATT

DCIN

LOADDS ON( ) ( )1 1

2

2=

⎛

⎝⎜

⎞

⎠⎟

⎡

⎣⎢⎢

⎤

⎦⎥⎥

⎛⎝⎜

⎞⎠⎟ ×−

PD P SwitchingV C f I

IDCIN MAX RSS SW LOAD

GATE( _ )

( )1

2

2=

× × ×

PD PVV

IRBATT

DCIN

LOADDS ON( ) ( )1

2

2=

⎛

⎝⎜

⎞

⎠⎟⎛⎝⎜

⎞⎠⎟ ×

0

1.0

0.5

1.5

8 10 11 12 139 14 15 16 17 18VBATT (V)

RIPP

LE C

URRE

NT (A

)

VDCIN = 19VVCTL = ICTL = LDO

3 CELLS

4 CELLS

Figure 11. Ripple Current vs. Battery Voltage (MAX1909)

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28 ______________________________________________________________________________________

The ripple current is determined by:

ΔIL = VBATT tOFF / L

where:

tOFF = 2.5µs (VDCIN - VBATT) / VDCIN for

VBATT < 0.88 VDCIN

or:

tOFF = 0.3µs for VBATT > 0.88 VDCIN

Figure 11 illustrates the variation of the ripple currentvs. battery voltage when the circuit is charging at 3Awith a fixed input voltage of 19V.

Higher inductor values decrease the ripple current.Smaller inductor values require high-saturation currentcapabilities and degrade efficiency. Designs that setLIR = ΔIL / ICHG = 0.3 usually result in a good balancebetween inductor size and efficiency.

Input-Capacitor SelectionThe input capacitor must meet the ripple currentrequirement (IRMS) imposed by the switching currents.Nontantalum chemistries (ceramic, aluminum, or OS-CON) are preferred due to their resilience to power-upsurge currents.

The input capacitors should be sized so that the temperature rise due to ripple current in continuousconduction does not exceed approximately 10°C. The maximum ripple current occurs at 50% duty factor orVDCIN = 2 VBATT, which equates to 0.5 ICHG. If theapplication of interest does not achieve the maximumvalue, size the input capacitors according to the worst-case conditions.

Output-Capacitor SelectionThe output capacitor absorbs the inductor ripple cur-rent and must tolerate the surge current delivered fromthe battery when it is initially plugged into the charger.As such, both capacitance and ESR are importantparameters in specifying the output capacitor as a filterand to ensure the stability of the DC-DC converter (seethe Compensation section). Beyond the stabilityrequirements, it is often sufficient to make sure that theoutput capacitor’s ESR is much lower than the battery’sESR. Either tantalum or ceramic capacitors can beused on the output. Ceramic devices are preferablebecause of their good voltage ratings and resilience tosurge currents.

Applications InformationStartup Conditioning Charge for

Overdischarged CellsIt is desirable to charge deeply discharged Li+ batter-ies at a low rate to improve cycle l i fe. TheMAX1909/MAX8725 automatically reduces the chargecurrent when the voltage per cell is below 3.1V. Thecharge current-sense voltage is set to 4.5mV (ICHG =300mA with RS2 = 15mΩ) until the battery voltage risesabove the threshold. There is approximately 300mV for3 cell, 400mV for 4 cell of hysteresis to prevent thecharge-current magnitude from chattering between thetwo values.

For the MAX8725, control the ICTL voltage to set a con-ditioning charge rate.

Layout and BypassingBypass DCIN with a 1µF capacitor to ground (Figure 1).D4 protects the MAX1909/MAX8725 when the DCpower source input is reversed. A signal diode for D4 isadequate because DCIN only powers the LDO and theinternal reference. Bypass LDO, DHIV, DLOV, andother pins as shown in Figure 1.

Good PC board layout is required to achieve specifiednoise, efficiency, and stable performance. The PCboard layout artist must be given explicit instructions—preferably, a sketch showing the placement of thepower-switching components and high-current routing.Refer to the PC board layout in the MAX1909/MAX8725evaluation kit for examples. A ground plane is essentialfor optimum performance. In most applications, the cir-cuit is located on a multilayer board, and full use of thefour or more copper layers is recommended. Use thetop layer for high-current connections, the bottom layerfor quiet connections, and the inner layers for an unin-terrupted ground plane.

Use the following step-by-step guide:

1) Place the high-power connections first, with theirgrounds adjacent:

a) Minimize the current-sense resistor tracelengths, and ensure accurate current sensingwith Kelvin connections.

b) Minimize ground trace lengths in the high-currentpaths.

c) Minimize other trace lengths in the high-currentpaths.

d) Use >5mm wide traces.

I IV V V

VRMS CHGBATT DCIN BATT

DCIN=

⎛

⎝⎜⎜

⎞

⎠⎟⎟

−( )

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______________________________________________________________________________________ 29

e) Connect C1 and C2 to the high-side MOSFET(10mm max length). Return these capacitors tothe power ground plane.

f) Minimize the LX node (MOSFETs, rectifier cath-ode, inductor (15mm max length)).

Ideally, surface-mount power components areflush against one another with their ground terminals almost touching. These high-currentgrounds are then connected to each other witha wide, filled zone of top-layer copper, so theydo not go through vias.

The resulting top-layer ground plane is connectedto the normal inner-layer ground plane at the out-put ground terminals, which ensures that the IC’sanalog ground is sensing at the supply’s outputterminals without interference from IR drops andground noise. Other high-current paths shouldalso be minimized, but focusing primarily on shortground and current-sense connections eliminatesabout 90% of all PC board layout problems.

2) Place the IC and signal components. Keep the mainswitching node (LX node) away from sensitive ana-log components (current-sense traces and REFcapacitor). Important: the IC should be less than10mm from the current-sense resistors.

Quiet connections to REF, VCTL, ICTL, CCV, CCI,CCS, IINP, ACIN, and DCIN should be returned to aseparate ground (GND) island. The appropriatetraces are marked on the schematic with theground symbol ( ). There is very little current flow-ing in these traces, so the ground island need notbe very large. When placed on an inner layer, a siz-able ground island can help simplify the layoutbecause the low-current connections can be madethrough vias. The ground pad on the backside ofthe package should also be connected to this quietground island.

3) Keep the gate drive traces (DHI and DLO) as shortas possible (L < 20mm), and route them away fromthe current-sense lines and REF. These tracesshould also be relatively wide (W > 1.25mm).

4) Place ceramic bypass capacitors close to the IC.The bulk capacitors can be placed further away.

5) Use a single-point star ground placed directlybelow the part at the PGND pin. Connect the powerground (ground plane) and the quiet ground islandat this location. See Figure 12.

Chip InformationTRANSISTOR COUNT: 2720

PROCESS: BiCMOS

INDUCTOR

CIN

COUT

COUT

INPUT

OUTPUT

KELVIN-SENSE VIASUNDER THE SENSE

RESISTOR(REFER TO EVALUATION KIT)

GND

PGNDPOWER PATH

QUIET GROUNDISLAND

Figure 12. PC Board Layout Examples

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Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses areimplied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

30 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

Package Information(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,go to www.maxim-ic.com/packages.)



QFN

TH

IN.E

PS

MAX1909-MAX8725

Documents

c stresses

c temperature range

c pinpackage

c junction temperature

c storage temperature

host microcontroller

c lead temperature soldering

maximum current