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Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203Copyright (c) 2015, Altera Corporation. All Rights Reserved.
( VCCIO = 3.3V ) ( VCCIO = 3.3V )
MAX10 BANKS 7 & 8
PMOD
User IO
HDMI TX
Flash
LI-USB3 CSI-2 TX Interface
User LED
HDMI_VIDEO_DIN14
HDMI_VIDEO_DIN15
FLASH_D3
FLASH_D1FLASH_D2
HDMI_VIDEO_DIN16
HDMI_VIDEO_DIN0
HDMI_VIDEO_DATA_EN
HDMI_HSYNC
HDMI_VSYNC
USER_IO3
USER_IO6USER_IO5
USER_IO1
USER_IO7
USER_IO8USER_IO9
USER_IO4
USER_IO2HDMI_VIDEO_DIN3
HDMI_VIDEO_DIN2
HDMI_VIDEO_DIN4
HDMI_VIDEO_DIN1
HDMI_VIDEO_DIN22
HDMI_VIDEO_DIN21
HDMI_VIDEO_DIN18
HDMI_VIDEO_DIN19
HDMI_VIDEO_DIN23
HDMI_VIDEO_DIN20HDMI_VIDEO_DIN17
HDMI_SCL
HDMI_SDA
HDMI_INTRUSER_IO0
HDMI_VIDEO_DIN5HDMI_VIDEO_DIN6
HDMI_VIDEO_DIN7
HDMI_VIDEO_DIN8HDMI_VIDEO_DIN9
HDMI_VIDEO_DIN10HDMI_VIDEO_DIN12
HDMI_VIDEO_DIN11
HDMI_VIDEO_DIN13
PMODA_D0PMODA_D4
PMODA_D6PMODA_D3
PMODB_D3PMODB_D2PMODB_D4PMODA_D2
PMODB_D6PMODB_D7PMODB_D5
PMODA_D7
MIPI_TX_CMOS_SCLK_3V3MIPI_TX_CMOS_SDATA_3V3
FLASH_RESETn FLASH_RESETn_MAX10
FLASH_CSn
FLASH_D0
FLASH_CLK
USER_LED0
USER_LED1
USER_LED2USER_LED3
USER_LED4
PMODA_D1
PMODA_D5
PMODB_D1
PMODB_D0
MIPI_TX_CMOS_RST_3V3
PMODB_D[7:0] 17
PMODA_D[7:0] 17
USER_IO[0:9] 17
HDMI_VIDEO_DIN[23:0] 14
HDMI_HSYNC 14
HDMI_VSYNC 14
HDMI_VIDEO_DATA_EN 14
HDMI_INTR 14
HDMI_SDA 14
HDMI_SCL 14
FLASH_D[0:3] 25
FLASH_CSn 25
FLASH_CLK 25
FLASH_RESETn 15,25
MIPI_TX_CMOS_SDATA_3V3 11
MIPI_TX_CMOS_SCLK_3V3 11
USER_LED[0:4] 18
MIPI_TX_CMOS_RST_3V3 11
Title
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MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)
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MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)
A3
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MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)
A3
7 25Thursday, March 24, 2016
BANK-7 BANK-8
MAX 10 TOP BANKS
10M50DAF484
U1D
DIFFIO_RX_T10NA17
DIFFIO_RX_T10PA18
DIFFIO_RX_T15NC15
DIFFIO_RX_T15PC16
DIFFIO_RX_T16NA16
DIFFIO_RX_T16PB16
DIFFIO_RX_T17NJ13
DIFFIO_RX_T17PH14
DIFFIO_RX_T18NC13
DIFFIO_RX_T18PC14
DIFFIO_RX_T19NB14
DIFFIO_RX_T19PA14
DIFFIO_RX_T1NE15
DIFFIO_RX_T1PE16
DIFFIO_RX_T20NE13
DIFFIO_RX_T20PD14
DIFFIO_RX_T21PE12
DIFFIO_RX_T21ND13
DIFFIO_RX_T22NJ12
DIFFIO_RX_T22PH13
DIFFIO_RX_T23NA12
DIFFIO_RX_T23PA13
DIFFIO_RX_T24ND12
DIFFIO_RX_T24PC12
DIFFIO_RX_T25NA10
DIFFIO_RX_T25PA11
DIFFIO_RX_T26NC10
DIFFIO_RX_T26PC11
DIFFIO_RX_T27NB11
DIFFIO_RX_T27PB12
DIFFIO_RX_T28NJ11
DIFFIO_RX_T28PH12
DIFFIO_RX_T31NB8
DIFFIO_RX_T31PA9
DIFFIO_RX_T2NC17
DIFFIO_RX_T2PD17
DIFFIO_RX_T30NC9
DIFFIO_RX_T30PB10
DIFFIO_RX_T29PA7
DIFFIO_RX_T29NA8
DIFFIO_RX_T5NF15
DIFFIO_RX_T5PF16
DIFFIO_RX_T6NB19
DIFFIO_RX_T6PC19
DIFFIO_RX_T7NB17
DIFFIO_RX_T7PC18
DIFFIO_RX_T8NA19
DIFFIO_RX_T8PA20
DIFFIO_RX_T9NE14
DIFFIO_RX_T9PD15
TBD7A15 VREFB7N0B15
DIFFIO_RX_T39NC7
DIFFIO_RX_T39PC8
DIFFIO_RX_T41NA6
DIFFIO_RX_T41PB7
DIFFIO_RX_T42PD8
DIFFIO_RX_T43NA4
DIFFIO_RX_T43PA5
DIFFIO_RX_T44NE9
DIFFIO_RX_T45PA2
DIFFIO_RX_T45NA3
DIFFIO_RX_T46PB3
DIFFIO_RX_T46NB4
DIFFIO_RX_T49ND5
DIFFIO_RX_T49PC5
DIFFIO_RX_T51NB1
DIFFIO_RX_T51PB2
DIFFIO_RX_T53PC3
VREFB8N0D7
TBD8C6
DIFFIO_RX_T47PB5
DIFFIO_RX_T47NC4
DIFFIO_RX_T48PE8
DIFFIO_RX_T53NC2
R250 0
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203Copyright (c) 2015, Altera Corporation. All Rights Reserved.
( VCCIO = 1.8V )
( VCCIO = 2.5V )
( VCCIO = 2.5V )
( VCCIO = 1.2V )
( VCCIO = 3.3V )
MAX10 CLOCKS
LPDDR2 Interface
Si5338
HDMI
USB Blaster II
User LVDS
OV5640 Interface
OV10640 Interface
Note: CLK125M_LVDS is the clocksource provided to external LVDS user interface.USER_CLKIN_P is used for external sigle-endedclock input.USER_CLKIN_P/N is used for external differentialclock input.
Copyright (c) 2015, Altera Corporation. All Rights Reserved.Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
PMOD, GPIO, LVDS USER IO
PMOD
User LVDS IO
User IO
LVDS
User GPIO
User LVDS IO
LVDS Termination
Note: USER_CLKIN_IO_Pis used if external single-endedclk needs to use on-chip PLLresource.USER_CLKIN_IO_P/N is usedfor external differential clk input.Values of R179,R180,R268, and R269 might be adjustedaccording to user input voltage.
PMOD Note: Place near MAX 10 side.
USER_IO9
USER_IO0USER_IO1
USER_IO2USER_IO3
USER_IO4
USER_IO5USER_IO6
USER_IO7USER_IO8
USER_LVDS_P0USER_LVDS_N0
USER_LVDS_P1USER_LVDS_N1
USER_LVDS_P2USER_LVDS_N2
USER_LVDS_P3USER_LVDS_N3
USER_LVDS_P4USER_LVDS_N4
USER_LVDS_P5USER_LVDS_N5
USER_LVDS_P6USER_LVDS_N6
USER_LVDS_P7USER_LVDS_N7
USER_LVDS_P8USER_LVDS_N8
CLKOUT_LVDS_PCLKOUT_LVDS_N
USER_CLKIN_PUSER_CLKIN_N_MAX10
USER_LVDS_N7USER_LVDS_P7
USER_LVDS_N6USER_LVDS_P6
USER_LVDS_N5USER_LVDS_P5
USER_LVDS_N3USER_LVDS_P3
USER_LVDS_P2USER_LVDS_N2
USER_LVDS_P1USER_LVDS_N1
USER_LVDS_P0USER_LVDS_N0
USER_LVDS_N8USER_LVDS_P8
USER_CLKIN_IO_N
USER_CLKIN_N_MAX10
USER_CLKIN_IO_P
USER_CLKIN_P
PMODA_IO3PMODA_IO7PMODA_IO6PMODA_IO2
PMODA_IO4PMODA_IO0PMODA_IO1PMODA_IO5
PMODA_IO3PMODA_IO2PMODA_IO1PMODA_IO0 PMODA_IO4
PMODA_IO5PMODA_IO6PMODA_IO7
PMODB_IO0
PMODB_IO0
PMODB_IO1
PMODB_IO1
PMODB_IO4
PMODB_IO2
PMODB_IO2
PMODB_IO3
PMODB_IO6
PMODB_IO4
PMODB_IO5
PMODB_IO5
PMODB_IO7
PMODB_IO6
PMODB_IO3
PMODB_IO7
3.3V 3.3V
3.3V 3.3V
PMODA_D0PMODA_D1PMODA_D2PMODA_D3
PMODA_D4PMODA_D5PMODA_D6PMODA_D7
PMODB_D0PMODB_D1PMODB_D2PMODB_D3
PMODB_D4PMODB_D5PMODB_D6PMODB_D7
CLKOUT_LVDS_NCLKOUT_LVDS_P
USER_LVDS_P4USER_LVDS_N4
3.3V 3.3V
2.5V 2.5V
2.5V 2.5V
3.3V
3.3V 3.3V
3.3V
PMODA_D[7:0] 7
PMODB_D[7:0] 7
USER_LVDS_P[0:8] 5
USER_LVDS_N[0:8] 5
USER_IO[0:9] 7
CLKOUT_LVDS_P 8
CLKOUT_LVDS_N 8
USER_CLKIN_P 8
USER_CLKIN_N_MAX10 8
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Header 2x7 (DNI)
J14
IO11
IO33
IO55
IO77
IO99
IO22
IO44
IO66
IO88
IO1010
IO1111
IO1212
IO1313
IO1414
R172 200J9
2x6 PMOD Connector
11
77
22
88
33
99
44
1010
55
1111
66
1212
R175 200
R153 DNI
R272 DNI
R2691.00k
R177 200
U11
824013
IO11
IO23
IO34
IO46
VDD5
GND2
R1792.0K
R1801.00k
R161 200
R167 DNI
U8
824013
IO11
IO23
IO34
IO46
VDD5
GND2
R164 200
R166 DNI
R158 200
U9
824013
IO11
IO23
IO34
IO46
VDD5
GND2
J13
Header 2x10 (DNI)
11
33
55
77
99
1111
1313
1515
1717
1919
22
44
66
88
1010
1212
1414
1616
1818
2020
R160 200
R178 200
R2682.0K
R165 DNI
R174 200
R154 DNI
R173 200
J12
Header 2x10 (DNI)
11
33
55
77
99
1111
1313
1515
1717
1919
22
44
66
88
1010
1212
1414
1616
1818
2020
R155 DNI
R162 DNI
R171 200
U10
824013
IO11
IO23
IO34
IO46
VDD5
GND2
R168 DNI
R169 DNI
R159 200
R170 DNI
R163 200
J8
2x6 PMOD Connector
11
77
22
88
33
99
44
1010
55
1111
66
1212
R157 200R156 200
R176 200
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PUSHBUTTON, SWITCH, LED
Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203Copyright (c) 2015, Altera Corporation. All Rights Reserved.
Note: MAX10_BYPASSn is used to bypassthe virtual JTAG device provided within theOn-Board USB-Blaster II.
USER_PB1
MAXII_CONF_DONE_RMAXII_CONF_DONE
MAX10_nCONFIG
MAX10_RESETn
USER_DIPSW1USER_DIPSW0
USER_DIPSW2USER_DIPSW3
USER_DIPSW5MAX10_CONFIG_SEL
USER_DIPSW4
MAX10_BYPASSn
USER_LED0
USER_LED1
USER_LED3
USER_LED4
USER_LED0_R
USER_LED1_R
USER_LED2_RUSER_LED2
USER_LED3_R
USER_LED4_R
1.2V_LED_R1.2V_LED
2.5V_LED_R
5V_LED_RUSER_PB2
USER_PB0
USER_PB3
3.3V
1.2V_VCCIO
3.3V
5V
2.5V
1.2V_VCCIO
3.3V
3.3V
USER_LED[0:4] 7
USER_PB[0:3] 6
MAX10_nCONFIG 9
MAX10_RESETn 9
USER_DIPSW[0:3] 6
MAX10_CONFIG_SEL 9
MAX10_BYPASSn 16
MAXII_CONF_DONE 15
1.2V_LED 15
USER_DIPSW[4:5] 4
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A3
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MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)
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R185 10.0K
D6 GREEN_LED
S7
PB Switch
1 32 4
R198 10.0K
R203 10.0K
D11 YELLOW_LED
S3
PB Switch
1 32 4
D3 GREEN_LED
D5 GREEN_LED
R200 150
R191 10.0K
R195 10.0K
D4 GREEN_LED
OPEN
SW2
DIPSWITCH4
1234 5
678
D8 GREEN_LED
S1
PB Switch
1 32 4
R204 10.0K
D7 GREEN_LED
R189 10.0K
R199 1.00k
S2
PB Switch
1 32 4
OPEN
SW1
DIPSWITCH4
1234 5
678
R194 390
R202 10.0K
R188 150
R183 150
R196 10.0K
R187 150
R186 150
R193 150R192 10.0K
R190 10.0K
D9YELLOW_LED
R181 10.0KR182 10.0K
S4
PB Switch
1 32 4
R278 390
S6
PB Switch
1 32 4
D10YELLOW_LED
R184 10.0K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203Copyright (c) 2015, Altera Corporation. All Rights Reserved.
CLOCKING
Notes:Use Clock Control GUI to program Si5338 oscillator outputs.(Defaults 100MHz, 125MHz, 24MHz, 24MHz)
I2C Address 70 HEX
Programmable ClockMAX 10
MAXII
DM385 CSI-2 TX Interface
3.3V CMOS complimentary
1.8V CMOS complimentary
3.3V Single-Ended CMOS
3.3V Single-Ended CMOS
3.3V CMOS3.3V CMOS
I2C_MAXII_SDA
I2C_MAXII_SCL
Si5338A_XTAL_25M_P
SI5338_INTR
Si5338A_XTAL_25M_N
CLK125M_R
CLK100M_LPDDR2_BK_RCLK100M_LPDDR2_R
CLK100M_LPDDR2_BKCLK100M_LPDDR2
1.8V_SI5338
CLK125M
CLK50M_MAX10CLK50M_MAXII
CLK50M_MAX10_RCLK50M_MAXII_R
3.3V_SI5338
OV5640_CLK24MHz_R OV5640_CLK24MHz
CLK24MCLK24M_RMIPI_TX_CLK24MHzMIPI_TX_CLK24MHz_R
CLK50M_EN
3.3V_SI510
3.3V
1.8V
3.3V
2.5V
CLK50M_MAXII 15
CLK50M_MAX10 8
CLK24M 8
CLK125M 8
CLK100M_LPDDR2 8
CLK100M_LPDDR2_BK 8
SI5338_INTR 16
I2C_MAXII_SDA 16
I2C_MAXII_SCL 16
OV5640_CLK24MHz 13
MIPI_TX_CLK24MHz 11
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C84
0.1uF
R207 0
L9
BLM15AG221SN1300mA
R210 0
C88
0.1uF
R213 0
C85
0.1uF
C87 DNI
R208 0
R211 0
Y225.00MHz
13
24
R216 22.0
C86
0.1uF
L6
BLM15AG221SN1300mA
C89 DNI
U14
Si5338C-CUSTOM
CLKIN_P1
CLKIN_N2
CLKIN3
I2C_LSB4
FDBK_P5
FDBK_N6
VDD17
VDD224
VDDO311
VDDO215
VDDO116
VDDO020
INTR8
CLK3B9
CLK3A10SCL
12
CLK2B13
CLK2A14
CLK1B17
CLK1A18
SDA19
CLK0B21
CLK0A22
RSVD_GND23
EPAD25
R205 4.7k
R214 1.00k
U15
510MCA50M0000AAGR
VDD6
GND3
NC1
CLKp4
CLKn5
OE2
R215 22.0
C82
0.1uF
L5
BLM15AG221SN1300mA
R206 22.0
R209 22.0
R212 DNI
C83
0.1uF
C240
0.1uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203Copyright (c) 2015, Altera Corporation. All Rights Reserved.
HOT SWAP and POWER 3.3V
5VDC Input
Hot Swap Controller Circuit
POWER 3.3VHot Swap for DC Plug
EN5329
CAUTION:When NOT using jumpers,solder R292 for power input from DC Jack,or solder R293 for USB power.SOLDER ONLY ONE POWER OPTION,AND SUGGEST NOT TO USE WITH JUMPER.
Notes:Place C90 near PVIN pin.
Notes:Place C96 near AVIN pin.
Notes:Place C91, R223 and R229 near EN5329QI VFB pin.
3.3V_VFB5V_P
5V_G
ATE
5V_P
G
5V_IMON
5V_F
B
5V_UV5V_OV
5V_N
5V_UV
5V_R3.3
3.3V_EN
3.3V_POK3.3V
5V_DCIN
5V_DCIN
5V_MONITOR
VBUS_5V
5V_MONITOR
5V
5V1.8V
3.3V
5V
3.3V_POK 21
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R2790
C96
1.0UF
C94
150uF
C92
22uF
R260 0
C91
6.8pF
R232
20.0K
R22660.4K
V2
RS
NS
1S
NS
2
U18
LTC4218CGN
NC1
VDD2
UV3
OV4
TIMER5
INTVCC6
GND7
SOURCE8
GATE9PG10/FLT11FB12IMON13ISET14SENSE-15SENSE+16
C97
0.1uF
R293 DNIR292 DNI
R284
DNI
C207
DNI
R225
10
TP2
C93
22uFC95
22uF
R223
348K
J11
HEADER, 1x3-PIN
123
R280DNI
TP1
R231 1.00k
R264 0C220
47uF
R233
20.0K
R228
1K
R21740.2K
V1
RS
NS
1S
NS
2
C98
0.01uF
R230
20.0K
R22469.8K
R222 0.005
R227
10.0K
C90
22uF
J10
DC Input Jack 2.0 mm
123
R221
20.0K
U16FDMC8878
5
123
4R281 10.0K
C99
0.1uF
R229
78.7K
XJ1
609002115121
EN5329QI
U17
PGND2
PGND3
PGND8
PGND9
TST210
TST111
TST012
NC
13
AGND15
AVIN16
ENABLE18
PVIN19
PVIN20
NC
(SW
)01
NC
(SW
)121
NC
(SW
)222
NC
(SW
)323
NC
(SW
)424
VOUT4
VOUT5
VOUT6
VOUT7
VFB14
POK17
PG
ND
25
PG
ND
26
SW3
POWER SW
32
1
45
6
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203Copyright (c) 2015, Altera Corporation. All Rights Reserved.
POWER 2.5V & 1.8V
POWER 2.5V
POWER 2.5V_VCCA POWER 1.8V
EN5329
Notes:Place caps near EP5348UI.
Notes:Place caps near EP5348UI.
Notes:Place C104 close to EP5358.
Notes:Place caps near EP5358HUI.
Note:Possible adjustment within15% VID setting by parallelRC combination.
1.8V_ENABLE
5V_R1.8
2.5V_ENABLE3.3V_POK
2.5V 1.8V2.5V_CORE 2.5V_VCCA5V
5V_R2.55V 2.5V
3.3V_POK 20
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R258 0
C105
DNI
L7 7427920221 2
R291
63.0K
R235
0
R255
DNI
C215
2.2uF
C176DNI
R289 0
C218
DNI
R236 0.1
C106
10uF
C211
2.2uF
C107
10uF
C212
0.1uF
U20
EP5358HUI
NC11
PGND2
PGND3
VFB/NC44
VSENSE5
AGND6
VOUT7
VOUT8
VS29 VS1
10 VS011
ENABLE12
AVIN13
PVIN14
NC1515
NC1616
C104
2.2uF
R290
200k
C216
5 pF
C175
DNI
TP3
C213
10uF
C219
47uF
TP4
C217
DNI
R2570
R282 0
C109
0.1uF
U19
EP5348UI
NC
(SW
)01
NC
(SW
)113
NC
(SW
)214
NC
03
PGND2
VFB4
AGND5
VOUT6
VOUT7
NC
18
NC
29
ENABLE10
AVIN11
PVIN12
C108
10uF
C251
2.2uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203Copyright (c) 2015, Altera Corporation. All Rights Reserved.
POWER 1.2V
Notes:Place the 10uF capacitor close to ferrite bead.Place the 0.1uF capacitor close to MAX 10 pin.
Place a 1μ F capfrom the AVIN pinto AGND pin.
EN5339
POWER 1.2V_CORE
POWER 1.2V_VCCIO
POWER 1.2V_VCCD_PLL
Notes:Place caps near EP5348UI.
Notes:Place caps near EP5348UI.
Notes:Place C112, R240 and R243 near EN5329QI VFB pin.
Notes:Place C111 close to PVIN pin.
1.2V_CORE_VFB
1.2V_CORE_ENABLE
1.2V_VCCIO_ENABLE
1.2V_CORE_POK
5V_R1.2CORE
1.2V_VCCIO_VFB
1.2V_VCCIO
1.8V
1.2V_CORE 1.2V_VCCD_PLL
1.2V_CORE_SENSE 1.2V_CORE
5V_R1.2VCCIO
3.3V
5V
2.5V
5V_R1.2VCCIO5V
1.2V_CORE_POK 15
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TP6
R238 0.01
C209
2.2uF
C112
15pF
C174
DNI
C119
DNI
C250
2.2uF
C113
47uF
C249
DNI
R254 0
C210
0.1uF
EN5339QI
U21
PGND2
PGND3
PGND8
PGND9
TST210
TST111
TST012
NC
13
AGND15
AVIN16
ENABLE18
PVIN19
PVIN20
NC
(SW
)01
NC
(SW
)121
NC
(SW
)222
NC
(SW
)323
NC
(SW
)424
VOUT4
VOUT5
VOUT6
VOUT7
VFB14
POK17
PG
ND
25
PG
ND
26
C115
2.2uF
C116
DNI
C122
0.1uF
C118
10uF
TP5
C208
5 pF
C111
22uF
R253 0
R285
200k
C121
10uF
R23910.0K
L8 7427920221 2
C248
DNI
R241DNI
R2420
C120
1.0UF
U22
EP5348UI
NC
(SW
)01
NC
(SW
)113
NC
(SW
)214
NC
03
PGND2
VFB4
AGND5
VOUT6
VOUT7
NC
18
NC
29
ENABLE10
AVIN11
PVIN12
C114
47uF
R315
51
R252DNI
R243
348K
R283 0
R286
200k
R240
348K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203Copyright (c) 2015, Altera Corporation. All Rights Reserved.
MAX 10 POWER & GROUND
Note:According to MAX 10 pinconnection guideline PCG-01018-1.2,"Tie the VCCINT pin to any1.2V power domain if you are not using ADC."Therefore, connect VCCINTto 1.2V_CORE for DC or DFproduction device migration.
Note:According to MAX 10 pinconnection guideline PCG-01018-1.2,"Tie the VCCA_ADC pinto any 2.5V power domainif you are not using ADC, and do not tie the VCCA_ADCpin to GND."Therefore, connect VCCA_ADCto 2.5V_CORE for DC or DFproduction device migration.
Note:For ES device, connect ADC_VREF to NCwhen not using external voltage reference.For DC/DF production device, ADC_VREFpin is migrated to VCCA according to MAX10 Errata.
ADC_VREF
3.3V1.2V_CORE
1.2V_VCCD_PLL
2.5V_VCCA
1.2V_CORE2.5V_VCCA
1.8V
2.5V
2.5V
1.2V_VCCIO
1.2V_VCCIO
3.3V
3.3V
2.5V_VCCA
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MAX 10 POWER
10M50DAF484
U1G
VCCN12
VCCN10
VCCM13
VCCM12
VCCM11
VCCL12
VCCL11
VCCL10
VCCK13
VCCK11
VCCD_PLL1T7
VCCD_PLL2G16
VCCD_PLL3G7
VCCD_PLL4U16
VCCA1R8
VCCA2H15
VCCA3H8
VCCA4T15
VCCINTJ7
VCCA_ADCH7
ADC_VREFH6
ANAIN1G5
ANAIN2J5
VCCIO1AL6
VCCIO1AK7
VCCIO1BM6
VCCIO1BL7
VCCIO2R6
VCCIO2P7
VCCIO2N7
VCCIO2N6
VCCIO3U9
VCCIO3U8
VCCIO3T9
VCCIO3T11
VCCIO3T10
VCCIO4U14
VCCIO4U12
VCCIO4U11
VCCIO4T13
VCCIO4T12
VCCIO5T17
VCCIO5R17
VCCIO5R16
VCCIO5P16
VCCIO5N16
VCCIO6N17
VCCIO6M17
VCCIO6L16
VCCIO6K17
VCCIO6K16
VCCIO6J17
VCCIO6H16
VCCIO7G14
VCCIO7G13
VCCIO7G12
VCCIO7F14
VCCIO7F12
VCCIO8G11
VCCIO8G10
VCCIO8F9
VCCIO8F11
MAX 10 GROUND
10M50DAF484
U1H
GNDY9
GNDY15
GNDY12
GNDW21
GNDV6
GNDV2
GNDV19
GNDU13
GNDU10
GNDT8
GNDT4
GNDT16
GNDT14
GNDR21
GNDR19
GNDP6
GNDP2
GNDP17
GNDN13
GNDN11
GNDM7
GNDM19
GNDM16
GNDM10
GNDL5
GNDL21
GNDL17
GNDL13
DNUL3
GNDK3
GNDK12
GNDK10
GNDJ6
GNDJ2
GNDJ19
GNDJ16
GNDG8
GNDG6
GNDG21
GNDG18
GNDG15
GNDF13
GNDF10
GNDE7
GNDE2
GNDD4
GNDD20
GNDD16
GNDD11
GNDB9
GNDB6
GNDB18
GNDB13
GNDAB22
GNDAB1
GNDAA4
GNDAA18
GNDA22
GNDA1
NC2F6NC1E5
REFGNDH5
R267 DNI
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203Copyright (c) 2015, Altera Corporation. All Rights Reserved.
DECOUPLING
Notes:Place capacitor near MAX 10 pins.
Notes:Place these capacitors close to each MAX 10 VCCA pin.
Notes:Place a 0.1uF capacitor close to each MAX 10 VCCD pin.
Notes:Place these capacitors close to MAX 10 VCCIO7 and VCCIO8 pins.Notes:
Place these capacitors close to MAX 10 VCCIO2.
Notes:Place 100uF near LPDDR2 or between LPDDR2 and MAX10.Place 1.0uF and 0.1uF capacitors close to MAX 10 VCCIO5 and VCCIO6 pins.
Notes:Place these capacitors close to MAX 10 VCCIO3 and VCCIO4 pins.Place one 0.1uF close to MAX 10 VCCA_ADC pin.
2.5V3.3V
1.2V_VCCD_PLL
2.5V_VCCA1.8V
1.2V_VCCIO1.2V_CORE
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C155
0.1uFC239
0.1uF
C148
0.1uF
C146
0.1uF
C235
0.1uF
C206
0.1uF
C230
0.1uF
C233
0.1uF
C222
1.0UF
C228
0.1uF
C124
0.1uF
C226
0.1uF
C144
0.1uF
C237
0.1uF
C224
0.1uF
C197
0.22uF
C194
1.0UF
C156
0.1uF
C149
0.1uF
C147
0.1uF
C231
0.1uF
C145
0.1uF
C236
0.1uF
C196
4.7uF
C234
0.1uF
C223
1.0UF
C229
0.1uF
C227
0.1uF
C221
1.0UF
C225
0.1uF
C232
DNI
C238
0.1uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203Copyright (c) 2015, Altera Corporation. All Rights Reserved.