Doc No. MV-S108467-00 Rev. C January 27, 2016 Document Classification: Proprietary Marvell. Moving Forward Faster 88SE9235 R1.1 Two-Lane PCIe 2.0 to Four-Port 6 Gbps SATA I/O Controller Datasheet
Doc No. MV-S108467-00 Rev. C
January 27, 2016
Document Classification: ProprietaryMarvell. Moving Forward Faster
88SE9235 R1.1Two-Lane PCIe 2.0 to Four-Port 6 Gbps SATA I/O Controller
Datasheet
88SE9235 R1.1 Two-Lane PCIe 2.0 to Four-Port 6 Gbps SATA I/O ControllerDatasheet
No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose, without the express written permission of Marvell. Marvell retains the right to make changes to this document at any time, without notice. Marvell makes no warranty of any kind, expressed or implied, with regard to any information contained in this document, including, but not limited to, the implied warranties of merchantability or fitness for any particular purpose. Further, Marvell does not warrant the accuracy or completeness of the information, text, graphics, or other items contained within this document. Marvell products are not designed for use in life-support equipment or applications that would cause a life-threatening situation if any such products failed. Do not use Marvell products in these types of equipment or applications. With respect to the products described herein, the user or recipient, in the absence of appropriate U.S. government authorization, agrees: 1) Not to re-export or release any such information consisting of technology, software or source code controlled for national security reasons by the U.S. Export Control Regulations ("EAR"), to a national of EAR Country Groups D:1 or E:2; 2) Not to export the direct product of such technology or such software, to EAR Country Groups D:1 or E:2, if such technology or software and direct products thereof are controlled for national security reasons by the EAR; and, 3) In the case of technology controlled for national security reasons under the EAR where the direct product of the technology is a complete plant or component of a plant, not to export to EAR Country Groups D:1 or E:2 the direct product of the plant or major component thereof, if such direct product is controlled for national security reasons by the EAR, or is subject to controls under the U.S. Munitions List ("USML"). At all times hereunder, the recipient of any such information agrees that they shall be deemed to have manually signed this document in connection with their receipt of any such information.
Copyright © 1999–2016. Marvell International Ltd. All rights reserved. Alaska, ARMADA, Avanta, Avastar, CarrierSpan, Kinoma, Link Street, LinkCrypt, Marvell logo, Marvell, Moving Forward Faster, Marvell Smart, PISC, Prestera, Qdeo, QDEO logo, QuietVideo, Virtual Cable Tester, The World as YOU See It, Vmeta, Xelerated, and Yukon are registered trademarks of Marvell or its affiliates. G.now, HyperDuo, Kirkwood, and Wirespeed by Design are trademarks of Marvell or its affiliates.
Patent(s) Pending—Products identified in this document may be covered by one or more Marvell patents and/or patent applications.
For more information, visit our website at: www.marvell.com
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Copyright © 2016 Marvell Doc No. MV-S108467-00 Rev. CJanuary 27, 2016 Document Classification: Proprietary
Ordering Information
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Copyright © 2016 Marvell Doc No. MV-S108467-00 Rev. CJanuary 27, 2016 Document Classification: Proprietary
ORDERING INFORMATION
Ordering Part Numbers and Package Markings
The following figure shows the ordering part numbering scheme for the 88SE9235 part. For complete ordering information, contact your Marvell FAE or sales representative.
Sample Ordering Part Number
The standard ordering part numbers for the respective solutions are indicated in the following table.
The next figure shows a typical Marvell package marking.
88SE9235 Package Marking and Pin 1 Location
Note: The above drawing is not drawn to scale. The location of markings is approximate. Add-on marks are not represented. Flip chips vary widely in their markings and flip chip examples are not shown here. For flip chips, the markings may be omitted per customer requirement.
Ordering Part Numbers
Part Number Description
88SE9235A1-NAA2C000 76-pin QFN 9 mm × 9 mm, Two-Lane PCIe 2.0 to four-port 6 Gbps SATA Controller.
88SE9235A1-NAA2I000 76-pin Industrial Grade QFN 9 mm × 9 mm, Two-Lane PCIe 2.0 to four-port 6 Gbps SATA Controller.
Part Number
Product Revision
Custom Code
Custom Code(optional )
88XXXXX - XX - XXX - C000 - XXXX
Temperature CodeC = CommercialI = Industrial
Environmental Code + = RoHS 0/6–= RoHS 5/61 = RoHS 6/62 = Green)
Package Code3-character
alphabetic code such as BCC, TEH
Custom Code
Extended Part Number
YYWW xx@Country of Origin
Part number, package code, environmental code eXXXXX = Part number AAA = Package codee = Environmental code (+ = RoHS 0/6, no code = RoHS 5/6, 1 = RoHS 6/6, 2 = Green)
Country of origin(contained in the mold ID ormarked as the last line onthe package)
Pin 1 location
Marvell Logo
Lot Number88XXXXX-AAAe
Date code, custom code, assembly plant codeYYWW = Date code (YY = year, WW = Work Week)xx = Custom code or die revision@ = Assembly plant code
88SE9235 R1.1 Two-Lane PCIe 2.0 to Four-Port 6 Gbps SATA I/O Controller Datasheet
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Copyright © 2016 Marvell Doc No. MV-S108467-00 Rev. CJanuary 27, 2016 Document Classification: Proprietary
Change History
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Copyright © 2016 Marvell Doc No. MV-S108467-00 Rev. CJanuary 27, 2016 Document Classification: Proprietary
CHANGE HISTORY
The following table identifies the document change history for Rev. C.
Document Changes *
* The type of change is categorized as: Parameter, Revision, or Update. A Parameter change is a change to a spec value, a Revision change is one that originates from the chip Revision Notice, and an Update change includes all other document updates.
Location Type Description Date
Global Update Removed preliminary from document title. January 25, 2016
88SE9235 R1.1 Two-Lane PCIe 2.0 to Four-Port 6 Gbps SATA I/O ControllerDatasheet
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Contents
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Copyright © 2016 Marvell Doc No. MV-S108467-00 Rev. CJanuary 27, 2016 Document Classification: Proprietary
CONTENTS
1 OVERVIEW ........................................................................................................................................................ 1-1
2 FEATURES ........................................................................................................................................................ 2-1
2.1 GENERAL .................................................................................................................................................. 2-2
2.2 PCIE ......................................................................................................................................................... 2-3
2.3 SATA CONTROLLER .................................................................................................................................. 2-4
2.4 SPI INTERFACE CONTROLLER .................................................................................................................... 2-5
2.5 PERIPHERAL INTERFACE CONTROLLER ....................................................................................................... 2-6
3 PACKAGE ......................................................................................................................................................... 3-1
3.1 PIN DIAGRAM ............................................................................................................................................ 3-2
3.2 MECHANICAL DIMENSIONS ......................................................................................................................... 3-3
3.3 SIGNAL DESCRIPTIONS ............................................................................................................................... 3-53.3.1 Signal Descriptions Overview ................................................................................................... 3-53.3.2 Pin Type Definitions .................................................................................................................. 3-53.3.3 Signal Descriptions ................................................................................................................... 3-6
4 LAYOUT GUIDELINES ...................................................................................................................................... 4-1
4.1 LAYOUT GUIDELINES OVERVIEW ................................................................................................................. 4-2
4.2 BOARD SCHEMATIC EXAMPLE .................................................................................................................... 4-3
4.3 LAYER STACK-UP ...................................................................................................................................... 4-54.3.1 Layer Stack-Up Overview ......................................................................................................... 4-54.3.2 Layer 1–Topside, Parts, Slow and High Speed Signal Routes, and Power Routes .................. 4-54.3.3 Layer 2–Solid Ground Plane ..................................................................................................... 4-54.3.4 Layer 3–Power Plane ................................................................................................................ 4-54.3.5 Layer 4–Bottom Layer, Slow and High-Speed Signal Routes, and Power Routes ................... 4-5
4.4 POWER SUPPLY ........................................................................................................................................ 4-64.4.1 Power Supply Overview ............................................................................................................ 4-64.4.2 VDD Power (1.0V) ..................................................................................................................... 4-64.4.3 Analog Power Supply (1.8V) ..................................................................................................... 4-64.4.4 Bias Current Resistor (RSET) ................................................................................................... 4-7
4.5 PCB TRACE ROUTING ............................................................................................................................... 4-8
4.6 RECOMMENDED LAYOUT ............................................................................................................................ 4-9
5 ELECTRICAL SPECIFICATIONS ...................................................................................................................... 5-1
5.1 ABSOLUTE MAXIMUM RATINGS ................................................................................................................... 5-2
5.2 RECOMMENDED OPERATING CONDITIONS ................................................................................................... 5-3
5.3 POWER REQUIREMENTS ............................................................................................................................. 5-4
5.4 DC ELECTRICAL CHARACTERISTICS ............................................................................................................ 5-5
5.5 THERMAL DATA ......................................................................................................................................... 5-6
88SE9235 R1.1 Two-Lane PCIe 2.0 to Four-Port 6 Gbps SATA I/O ControllerDatasheet
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1-1
Copyright © 2016 Marvell Doc No. MV-S108467-00 Rev. CJanuary 27, 2016 Document Classification: Proprietary
Overview
1 OVERVIEW
The 88SE9235 is a four-port, 3 Gbps or 6 Gbps SATA Host Bus Adapter that provides a two-lane PCIe 2.0 interface and SATA controller functions. The 88SE9235 supplies four 6 Gbps SATA ports.
The 88SE9235 supports devices compliant with the Serial ATA International Organization: Serial ATA Revision 3.1 specification. Figure 1-1 shows the system block diagram.
Figure 1-1 88SE9235 Architecture (All Others)
PCIe 2.0 x2 EndPoint Controller
(5 Gbps x 2)
Function 0 BAR Interface
Peripheral Interface Controller
(SPI/UART/GPIO)
Internal Bus and Bus Arbiter
Serial ATA 4-port AHCIController
(1.5, 3 or 6 Gbps)
88SE9235 R1.1 Two-Lane PCIe 2.0 to Four-Port 6 Gbps SATA I/O Controller Datasheet
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1-2
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2-1
Copyright © 2016 Marvell Doc No. MV-S108467-00 Rev. CJanuary 27, 2016 Document Classification: Proprietary
Features
2 FEATURES
This chapter contains the following information:
General
PCIe
SATA Controller
SPI Interface Controller
Peripheral Interface Controller
88SE9235 R1.1 Two-Lane PCIe 2.0 to Four-Port 6 Gbps SATA I/O Controller Datasheet
2-2 General
Copyright © 2016 Marvell Doc No. MV-S108467-00 Rev. CJanuary 27, 2016 Document Classification: Proprietary
2.1 General
55 nm CMOS process, 1.0V digital core, 1.8V analog, and 3.3V I/O power supplies.
Reference clock frequency of 25 MHz, provided by an external clock source or generated by an external crystal oscillator.
Features
PCIe 2-3
Copyright © 2016 Marvell Doc No. MV-S108467-00 Rev. CJanuary 27, 2016 Document Classification: Proprietary
2.2 PCIe
PCIe 2.0 endpoint device.
Compliant with PCIe 2.0 specifications.
Supports communication speed of 2.5 Gbps and 5 Gbps.
Supports AHCI programming interface registers for the SATA controller.
Supports aggressive power management.
Supports error reporting, recovery and correction.
Supports Message Signaled Interrupt (MSI).
Improved PCIe read request efficiency
88SE9235 R1.1 Two-Lane PCIe 2.0 to Four-Port 6 Gbps SATA I/O Controller Datasheet
2-4 SATA Controller
Copyright © 2016 Marvell Doc No. MV-S108467-00 Rev. CJanuary 27, 2016 Document Classification: Proprietary
2.3 SATA Controller
Compliant with Serial ATA Specification 3.1.
Supports communication speeds of 6 Gbps, 3 Gbps, and 1.5 Gbps.
Supports programmable transmitter signal levels.
Supports Gen 1i, Gen 1x, Gen 2i, Gen 2m, Gen 2x, and Gen 3i.
Supports four SATA ports.
Supports AHCI 1.0 programming interface.
Supports Native Command Queuing (NCQ).
Supports Port Multiplier FIS based switching or command based switching.
Supports Partial and Slumber Power Management states.
Supports Staggered Spin-up.
Features
SPI Interface Controller 2-5
Copyright © 2016 Marvell Doc No. MV-S108467-00 Rev. CJanuary 27, 2016 Document Classification: Proprietary
2.4 SPI Interface Controller
A four-pin interface provides read and write access to an external SPI flash or SPI ROM device.
Vendor specific information stored in the external device is read by the controller during the chip power-up.
PCI BootROMs of PCIe function 0 can also be stored in the external SPI device and read through the Expansion ROM BAR and the SPI interface controller.
88SE9235 R1.1 Two-Lane PCIe 2.0 to Four-Port 6 Gbps SATA I/O Controller Datasheet
2-6 Peripheral Interface Controller
Copyright © 2016 Marvell Doc No. MV-S108467-00 Rev. CJanuary 27, 2016 Document Classification: Proprietary
2.5 Peripheral Interface Controller
Eight General Purpose I/O (GPIO) ports.
Each of the GPIO pins can be assigned to act as a general input or output pin.
Each of the GPIO inputs can be programmed to generate an edge-sensitive or a level-sensitive maskable interrupt.
Each of the GPIO outputs can be programmed for a connected LED to blink at a user-defined fixed rate. The default rate is 100 ms.
3-1
Copyright © 2016 Marvell Doc No. MV-S108467-00 Rev. CJanuary 27, 2016 Document Classification: Proprietary
Package
3 PACKAGE
This chapter contains the following information:
Pin Diagram
Mechanical Dimensions
Signal Descriptions
88SE9235 R1.1 Two-Lane PCIe 2.0 to Four-Port 6 Gbps SATA I/O Controller Datasheet
3-2 Pin Diagram
Copyright © 2016 Marvell Doc No. MV-S108467-00 Rev. CJanuary 27, 2016 Document Classification: Proprietary
3.1 Pin Diagram
The 76-pin QFN pin diagram is illustrated in Figure 3-1.
Figure 3-1 SE9235 Pin Diagram
Note: The center area beneath the chip is the Exposed Die Pad (Epad). When designing the PCB, create a solder pad for the Epad and connect the Epad to ground.
SP
I_D
O
GPIO7
VD
D
TXP
_3V
SS
RX
P_2
RX
P_3
RX
N_3
TX
N_3
VA
A2_
2T
XN
_2
GP
IO3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
RX
N_2
SP
I_C
S
SP
I_C
LKV
DD
IOS
PI_
DI
VA
A2_
3
TXP
_2VSS
RXN_1VAA2_1
RXP_188SE9235
WAKE_NCLKN
VDDPERST_N
TST2
GPIO1
GPIO0TST0
TST5TST4
61626364656667686970717273747576
585960
CLKP
TST6GPIO6
VDD
VDDIOTST3
TST1
GPIO2
TP
VDDN/CTXP_0
N/C
TXN_0
RXN_0RXP_0
TXN_1
VDDTESTMODEGPIO5GPIO4
VD
D
VAA2_0
20
383736353433323130292827262524232221
PTX
P1
PT
XN
1V
SS
VD
D
XT
LN_O
SC
40 3957 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
N/C
VS
S
PR
XP
0
AV
DD
1
ISE
T
VA
A1
AV
DD
0P
TX
P0
XT
LOU
T
PR
XP
1P
TX
N0
PR
XN
0
PR
XN
1
N/C
TXP_1
Package
Mechanical Dimensions 3-3
Copyright © 2016 Marvell Doc No. MV-S108467-00 Rev. CJanuary 27, 2016 Document Classification: Proprietary
3.2 Mechanical Dimensions
The package mechanical drawing is shown in Figure 3-2.
Figure 3-2 Package Mechanical Diagram
88SE9235 R1.1 Two-Lane PCIe 2.0 to Four-Port 6 Gbps SATA I/O Controller Datasheet
3-4 Mechanical Dimensions
Copyright © 2016 Marvell Doc No. MV-S108467-00 Rev. CJanuary 27, 2016 Document Classification: Proprietary
The package mechanical dimensions are shown in Figure .
Figure 3-3 Package Mechanical Dimensions
Package
Signal Descriptions 3-5
Copyright © 2016 Marvell Doc No. MV-S108467-00 Rev. CJanuary 27, 2016 Document Classification: Proprietary
3.3 Signal Descriptions
This section contains the following information:
Signal Descriptions Overview
Pin Type Definitions
Signal Descriptions
3.3.1 Signal Descriptions Overview
This section contains the pin types and signal descriptions for the 88SE9235 package.
3.3.2 Pin Type Definitions
Pin type definitions are shown in Table 3-1.
Table 3-1 Pin Type Definitions
Pin Type Definition
I/O Input and Output
I Input Only
O Output Only
A Analog
PU Internal Pull-Up when Input
PD Internal Pull-Down when Input
OD Open-Drain Pad
Ground Ground
Power Power
88SE9235 R1.1 Two-Lane PCIe 2.0 to Four-Port 6 Gbps SATA I/O Controller Datasheet
3-6 Signal Descriptions
Copyright © 2016 Marvell Doc No. MV-S108467-00 Rev. CJanuary 27, 2016 Document Classification: Proprietary
3.3.3 Signal Descriptions
This section outlines the 88SE9235 pin descriptions. All signals ending with the letter N indicate an active-low signal.
Table 3-2 PCIe Interface Signals
Signal Name Signal Number Type Description
PERST_N 61 I, PU PCI Platform Reset.
Active low, indicates when the applied power is within the specified tolerance and stable.
WAKE_N 60 O, OD PCI Wake-Up.
An open-drain, active low signal that is driven low by a PCIe function to reactivate the PCIe Link hierarchy’s main power rails and reference clocks.+
Note: For applications that support a wake-up function, connect this pin to the WAKE# signal of a PCIe card slot or system board. Connect an external pull-up resistor from the PCIe card slot or system board to the 3.3V auxiliary supply. For applications that do not support a wake-up function, keep the WAKE_N pin on the 88SE9235 open.
CLKP
CLKN
58
59
I, A Reference Clock.
Low voltage differential signals. The clock frequency has to be 100 MHz.
PRXP0
PRXN0
PRXP1
PRXN1
55
54
50
49
I, A PCIe differential signals to the controller’s receiver.
PTXP0
PTXN0
PTXP1
PTXN1
52
51
47
46
O, A PCIe differential signals from the controller’s transmitter.
Package
Signal Descriptions 3-7
Copyright © 2016 Marvell Doc No. MV-S108467-00 Rev. CJanuary 27, 2016 Document Classification: Proprietary
Table 3-3 Serial ATA Interface Signals
Signal Name Signal Number Type Description
TXN_0
TXP_0
TXN_1
TXP_1
TXN_2
TXP_2
TXN_3
TXP_3
33
34
27
28
12
13
6
7
O, A Serial ATA Transmitter Differential Outputs.
RXN_0
RXP_0
RXN_1
RXP_1
RXN_2
RXP_2
RXN_3
RXP_3
31
30
25
24
10
9
4
3
I, A Serial ATA Receiver Differential Inputs.
Table 3-4 Reference Signals
Signal Name Signal Number Type Description
ISET 42 I/O, A Reference Current for Crystal Oscillator and PLL.
This pin has to be connected to an external 6.04 kΩ 1% resistor to Ground.
XTLOUT 41 O, A Crystal Output.
XTLIN_OSC 40 I, A Reference Clock Input.
This signal can be from an oscillator, or connected to a crystal with the XTLOUT pin. The clock frequency must be 25 MHz ± 80 ppm.
Table 3-5 General Purpose I/O Signals
Signal Name Signal Number Type Description
GPIO0
GPIO1
GPIO2
GPIO3
GPIO5
GPIO4
GPIO6
GPIO7
63
69
70
18
21
20
75
76
I/O, PU General Purpose I/O.
88SE9235 R1.1 Two-Lane PCIe 2.0 to Four-Port 6 Gbps SATA I/O Controller Datasheet
3-8 Signal Descriptions
Copyright © 2016 Marvell Doc No. MV-S108467-00 Rev. CJanuary 27, 2016 Document Classification: Proprietary
Table 3-6 SPI Flash Interface Signals
Signal Name Signal Number Type Description
SPI_CLK 17 O SPI Interface Clock.
SPI_DI 15 I, PU Serial Data In.
Connect to the serial flash device’s serial data output (DO).
SPI_CS 14 O SPI Interface Chip Select.
SPI_DO 2 O Serial Data Out.
Connect to the serial flash device’s serial data input (DI).
Table 3-7 Test Mode Interface Signals
Signal Name Signal Number Type Description
TP 38 I/O, A Analog Test Point for PCIe PHY, SATA PHY, crystal oscillator, and PLL.
TST0 64 I/O Test Pin 0.
TST1 65 I/O Test Pin 1.
TST2 66 I/O Test Pin 2.
This pin is reserved for chip test purposes only. Keep floating.
TST3 67 I/O Test Pin 3.
This pin is reserved for chip test purposes only. Keep floating.
TST4 72 I/O Test Pin 4.
This pin is reserved for chip test purposes only. Keep floating.
TST5 73 I/O Test Pin 5.
This pin is reserved for chip test purposes only. Keep floating.
TST6 74 I/O Test Pin 6.
This pin is reserved for chip test purposes only. Keep floating.
TESTMODE 22 I, PD Test Mode.
Enables chip test modes.
Table 3-8 Power and Ground Pins
Signal Name Signal Number Type Description
VAA2_0
VAA2_1
VAA2_2
VAA2_3
32
26
11
5
Power Analog Power.
1.8V analog power supply for SATA PHY.
VAA1 39 Power Analog Power.
1.8V analog power for crystal oscillator, reference current generator, and PLL.
Package
Signal Descriptions 3-9
Copyright © 2016 Marvell Doc No. MV-S108467-00 Rev. CJanuary 27, 2016 Document Classification: Proprietary
AVDD0
AVDD1
53
48
Power Analog Power.
1.8V analog power supply for PCIe PHY.
VDDIO 16, 68 Power I/O Power.
3.3V analog power supply for digital I/Os.
VDD 1, 19, 23, 36, 44, 62, 71
Power 1.0V Core Digital Power.
VSS 8, 29, 45, 56 Power Ground.
The main ground is the exposed die-pad (ePad) on the bottom side of the package.
Table 3-9 No Connect Signals
Signal Name Signal Number Type Description
N/C 35, 37, 43, 57 N/A No Connect.
Table 3-8 Power and Ground Pins (continued)
Signal Name Signal Number Type Description
88SE9235 R1.1 Two-Lane PCIe 2.0 to Four-Port 6 Gbps SATA I/O Controller Datasheet
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3-10 Signal Descriptions
Copyright © 2016 Marvell Doc No. MV-S108467-00 Rev. CJanuary 27, 2016 Document Classification: Proprietary
4-1
Copyright © 2016 Marvell Doc No. MV-S108467-00 Rev. CJanuary 27, 2016 Document Classification: Proprietary
Layout Guidelines
4 LAYOUT GUIDELINES
The chapter contains the following information:
Layout Guidelines Overview
Board Schematic Example
Layer Stack-Up
Power Supply
PCB Trace Routing
Recommended Layout
Refer to Chapter 3, Package, for package information.
88SE9235 R1.1 Two-Lane PCIe 2.0 to Four-Port 6 Gbps SATA I/O Controller Datasheet
4-2 Layout Guidelines Overview
Copyright © 2016 Marvell Doc No. MV-S108467-00 Rev. CJanuary 27, 2016 Document Classification: Proprietary
4.1 Layout Guidelines Overview
This chapter describes the system recommendations from the Marvell Semiconductor design and application engineers who work with the 88SE9235. This chapter is written for those who are designing schematics and printed circuit boards for an 88SE9235-based system. Whenever possible, the PCB designer should try to follow the suggestions provided in this chapter.
The information in this chapter is preliminary. Please consult with Marvell Semiconductor design and application engineers before starting your PCB design.
Layout Guidelines
Board Schematic Example 4-3
Copyright © 2016 Marvell Doc No. MV-S108467-00 Rev. CJanuary 27, 2016 Document Classification: Proprietary
4.2 Board Schematic Example
The board schematic consists of the major interfaces of the 88SE9235 including SATA and PCIe. Figure 4-1 shows an example of board schematic.
Figure 4-1 SE9235 Example Board Schematic
S_TX
P0S0
_TXP
S0_T
XN
S0_R
XP
S_TX
N0
S_R
XN0
S_R
XP0
S0_R
XN
S1_T
XPS1
_TXN
S1_R
XP
S_TX
N1
S_R
XN1
S_R
XP1
S1_R
XN
PRX_1P
S_TX
N0
TEST
MO
DE
PTX_1P
PRX_1NAVDD1
S_R
XN0
S_R
XP0
S_TX
P1
VDD
_10
VDD
_10
VAA1
PRX_0PPRX_0N
XTLI
PTX_1N
VDD_10
PER
ST_N
AVDD0
PTX_0NPTX_0P
S_TX
P0
S_R
XP1
GN
D
VAA2
_0
S_TX
N1
VAA2
_1
GND
S_R
XN1
ISET
GN
D
S_TX
P1
PER
ST_N
PCLK
PPC
LKN
S2_T
XPS2
_TXN
S2_R
XP
S_TX
N2
S_R
XN2
S_R
XP2
S2_R
XN
S_TX
P2
S3_T
XPS3
_TXN
S3_R
XP
S_TX
N3
S_R
XN3
S_R
XP3
S3_R
XN
S_TX
P3
XTLOUT
PRX_
1NPR
X_1P
PTX_
1N
PTX_
0P
PTX_
1P
XTLI
WAK
E_N
PCLK
P
PCLK
N
GPI
O2
GPI
O1
GPI
O4
PRX_
0PPR
X_0N
VDD
_10
VDD
_10
VDD
IO
VDD
IOPTX_
0N
XTLO
UT
XTLO
UT
SPI_
CLK
SPI_
CS
SPI_
DO
SPI_
DI
GPI
O1
GPI
O2
GPI
O3
GPI
O4
GPIO3
SPI_
CS
SPI_
CLK
SPI_
DO
VDD_10
S_TXN2VAA2_2
S_RXN2
GND
S_TXN3
S_RXN3S_RXP3
VDD_10
S_TXP3
S_TXP2
VAA2_3
VDDIO
SPI_
DI
S_RXP2
3V3
1V8
1V8
VCC
IN
VCC
IN
1V8
1V8
1V8
VAA2
_0
VAA2
_1
VAA2
_2
VAA2
_3
VAA1
AVD
D0
AVD
D1
VDD
_10a
VDD
_10
3V3
3V3
3V3
SATA Interface
PCIE Interface
VDD_10a is 1V power
(Contact Marvell for SPI AVL)
LEDs for SATA activity
PCIe_3.3V
C631000pF
C631000pF
C58.01uF
C58.01uF
KE
YS3
S-AT
AK
EY
S3S-
ATA
1 2 3 4 5 6 78 9
C73.1uFC73.1uF
C62.01uF
C62.01uF
C6
.01u
FC
6.0
1uF
R8
100R
R8
100R
C281000pF
C281000pF
C16
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9235
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9235
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N/C_3 57VSS_4 56PRXP0 55PRXN0 54AVDD0 53PTXP0 52PTXN0 51PRXP1 50PRXN1 49AVDD1 48PTXP1 47PTXN1 46VSS_3 45VDD_5 44N/C_4 43ISET 42XTLOUT 41
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B21
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D16
B18
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D17
B16
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B13
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D19
B7
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D20
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C47.1uFC47.1uF
C52.1uFC52.1uF
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8.0
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C342.2uF
C342.2uF
C64
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C64
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C23.1uFC23.1uF
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7
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C55.01uF
C55.01uF
C54.01uF
C54.01uF
C371000pF
C371000pF
KE
YS2
S-AT
AK
EY
S2S-
ATA
1 2 3 4 5 6 78 9
C31.01uF
C31.01uF
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FB04
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1
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C53.01uF
C462.2uF
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ATA
1 2 3 4 5 6 78 9
C19
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C21.1uFC21.1uF
C10
.1uF
C10
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C51.01uF
C51.01uF
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AK
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S1S-
ATA
1 2 3 4 5 6 78 9
R9
100R
R9
100R
C1
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R5
100R
R5
100R
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C50.01uF
C681000pF
C681000pF
C12
.1uF
C12
.1uF
FB8
FB04
02
80oh
m_7
00m
aFB
8
FB04
02
80oh
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a
+
C69100 uF6.3V
+
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ACT_
S4
Gre
en
ACT_
S4
Gre
en
C49.01uF
C49.01uF
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FB04
02
80oh
m_7
00m
aFB
3
FB04
02
80oh
m_7
00m
a
C18
.01u
FC
18.0
1uF
C67.01uF
C67.01uF
C40.01uF
C40.01uF
C4
.01u
FC
4.0
1uF
C26.1uFC26.1uF
C35.1uFC35.1uF
C48.01uF
C48.01uF
C7
.01u
FC
7.0
1uF
ACT_
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Gre
en ACT_
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Gre
en
R6
NA
R04
02R
6N
AR
0402
C17
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FC
17.0
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FB5
80_1
.5A
FB04
02
FB5
80_1
.5A
FB04
02
C66.1uFC66.1uF
C652.2uF
C652.2uF
C3
.01u
FC
3.0
1uF
C591000pF
C591000pF
C321000pF
C321000pF
C74.1uFC74.1uF
88SE9235 R1.1 Two-Lane PCIe 2.0 to Four-Port 6 Gbps SATA I/O Controller Datasheet
4-4 Board Schematic Example
Copyright © 2016 Marvell Doc No. MV-S108467-00 Rev. CJanuary 27, 2016 Document Classification: Proprietary
Note: This diagram is for reference only. Contact your Marvell field applications engineer for the latest schematics.
Layout Guidelines
Layer Stack-Up 4-5
Copyright © 2016 Marvell Doc No. MV-S108467-00 Rev. CJanuary 27, 2016 Document Classification: Proprietary
4.3 Layer Stack-Up
This section contains the following information:
Layer Stack-Up Overview
Layer 1–Topside, Parts, Slow and High Speed Signal Routes, and Power Routes
Layer 2–Solid Ground Plane
Layer 3–Power Plane
Layer 4–Bottom Layer, Slow and High-Speed Signal Routes, and Power Routes
4.3.1 Layer Stack-Up Overview
The following layer stack up is recommended:
Layer 1–Topside, Parts, Slow and High Speed Signal Routes, and Power Routes
Layer 2–Solid Ground Plane
Layer 3–Power Plane
Layer 4–Bottom Layer, Slow and High-Speed Signal Routes, and Power Routes
5 mil traces and 5 mil spacing are the recommended minimum requirements.
4.3.2 Layer 1–Topside, Parts, Slow and High Speed Signal Routes, and Power Routes
All active parts are to be placed on the topside. Some of the differential pairs for SATA and PCIe are routed on the top layer, differential 100 ohm impedance needs to be maintained for those high speed signals.
4.3.3 Layer 2–Solid Ground Plane
A solid ground plane should be located directly below the top layer of the PCB. This layer should be a minimum distance below the top layer in order to reduce the amount of crosstalk and EMI. There should be no cutouts in the ground plane. Use of 1 ounce copper is recommended.
4.3.4 Layer 3–Power Plane
Use solid planes on layer 3 to supply power to the ICs on the PCB. Avoid narrow traces and necks on this plane.
4.3.5 Layer 4–Bottom Layer, Slow and High-Speed Signal Routes, and Power Routes
Some of the differential pairs for SATA and PCIe are routed on the top layer, differential 100Ω impedance needs to be maintained for those high speed signals. The high speed signals have the return current on the third layer, which is the power plane. Make sure there is no cut-out under the signal path.
88SE9235 R1.1 Two-Lane PCIe 2.0 to Four-Port 6 Gbps SATA I/O Controller Datasheet
4-6 Power Supply
Copyright © 2016 Marvell Doc No. MV-S108467-00 Rev. CJanuary 27, 2016 Document Classification: Proprietary
4.4 Power Supply
This section contains the following information:
Power Supply Overview
VDD Power (1.0V)
Analog Power Supply (1.8V)
Bias Current Resistor (RSET)
4.4.1 Power Supply Overview
The 88SE9235 operates using the following power supplies:
VDD Power (1.0V) for the digital core
Analog Power Supply (1.8V)
4.4.2 VDD Power (1.0V)
All digital power pins (VDD pins) must be connected directly to a VDD plane in the power layer with short and wide traces to minimize digital power-trace inductances.
Use vias close to the VDD pins to connect to this plane and avoid using the traces on the top layer. Marvell recommends placing capacitors around the three sides of the PCB near VDD pins with the following dimensions:
1 µF (1 capacitor)
0.1 µF (2 capacitors)
2.2 µF (1 ceramic capacitor)
The 2.2 µF ceramic decoupling capacitor is needed to filter the lower frequency power-supply noise.
To reduce system noise, the use of high-frequency surface-mount monolithic ceramic bypass capacitors should be placed as close as possible to the channel VDD pins. At least one decoupling capacitor should be placed on each side of the IC package.
Short and wide copper traces should be used to minimize parasitic inductances. Low-value capacitors (1,000–10,000 pF) are preferable over higher values because they are more effective at higher frequencies.
4.4.3 Analog Power Supply (1.8V)
The PCIe analog supply provides power for the PCIe link’s high speed serial signals. To ensure high speed link operation, use a series of bypass capacitors for the supplies. A typical capacitor value combination is 1 µF, 0.1µF, and 2.2 µF.
Layout Guidelines
Power Supply 4-7
Copyright © 2016 Marvell Doc No. MV-S108467-00 Rev. CJanuary 27, 2016 Document Classification: Proprietary
4.4.4 Bias Current Resistor (RSET)
Connect a 6.04KΩ (1%) resistor between the ISET pin and the adjacent top ground plane. This resistor should lie as close as possible to the ISET pin.
88SE9235 R1.1 Two-Lane PCIe 2.0 to Four-Port 6 Gbps SATA I/O Controller Datasheet
4-8 PCB Trace Routing
Copyright © 2016 Marvell Doc No. MV-S108467-00 Rev. CJanuary 27, 2016 Document Classification: Proprietary
4.5 PCB Trace Routing
The stack-up parameters for the reference board are shown in Table 4-1.
Table 4-1 PCB Board Stack-up Parameters
LayerLayer
DescriptionCopper Weight
(oz)Target Impedance
(±10%)
1 Signal 0.5 50
2 GND 1 N/A
3 Power 1 N/A
4 Signal 0.5 50
Layout Guidelines
Recommended Layout 4-9
Copyright © 2016 Marvell Doc No. MV-S108467-00 Rev. CJanuary 27, 2016 Document Classification: Proprietary
4.6 Recommended Layout
Solid ground planes are recommended. However, special care should be taken when routing VAA and VSS pins.
The following general tips describe what should be considered when determining your stack-up and board routing. These tips are not meant to substitute for consulting with a signal-integrity expert or doing your own simulations.
Note: Specific numbers or rules-of-thumb are not used here because they might not be applicable in every situation.
Do not split ground planes.
Keep good spacing between possible sensitive analog circuitry on your board and the digital signals to sufficiently isolate noise. A solid ground plane is necessary to provide a good return path for routing layers. Try to provide at least one ground plane adjacent to all routing layers (see Figure 4-2).
Keep trace layers as close as possible to the adjacent ground or power planes.
This helps minimize crosstalk and improve noise control on the planes.
Figure 4-2 Trace Has At Least One Solid Plane For Return Path
When routing adjacent to only a power plane, do not cross splits.
Route traces only over the power plane that supplies both the driver and the load. Otherwise, provide a decoupling capacitor near the trace at the end that is not supplied by the adjacent power plane.
Critical signals should avoid running parallel and close to or directly over a gap.
This would change the impedance of the trace.
Separate analog powers onto opposing planes.
This helps minimize the coupling area that an analog plane has with an adjacent digital plane.
For dual strip-line routing, traces should only cross at 90 degrees.
Avoid more than two routing layers in a row to minimize tandem crosstalk and to better control impedance.
Planes should be evenly distributed in order to minimize warping.
Calculating or modeling impedance should be made prior to routing.
This helps ensure that a reasonable trace thickness is used and that the desired board thickness is available. Consult with your board fabricator for accurate impedance.
GND
V2
V1
88SE9235 R1.1 Two-Lane PCIe 2.0 to Four-Port 6 Gbps SATA I/O Controller Datasheet
4-10 Recommended Layout
Copyright © 2016 Marvell Doc No. MV-S108467-00 Rev. CJanuary 27, 2016 Document Classification: Proprietary
Allow good separation between fast signals to avoid crosstalk.
Crosstalk increases as the parallel traces get longer.
When packages become smaller, route traces over a split power plane
Smaller packages force vias to become smaller, thereby reducing board thickness and layer counts, which might create the need to route traces over a split power plane. Some alternatives to provide return path for these signals are listed below.
Caution must be used when applying these techniques. Digital traces should not cross over analog planes, and vice-versa. All of these rules must be followed closely to prevent noise contamination problems that might arise due to routing over the wrong plane.
By tightly controlling the return path, control noise on the power and ground planes can be controlled.
Place a ground layer close enough to the split power plane in order to couple enough to provide buried capacitance, such as SIG-PWR-GND (see Figure 4-3). Return signals that encounter splits in this situation simply jumps to the ground plane, over the split, and back to the other power plane. Buried capacitance provides the benefit of adding low inductance decoupling to your board. Your fabricator may charge for a special license fee and special materials. To determine the amount of capacitance your planes provide, use the following equation:
Where ER is the dielectric coefficient, L • W represents the area of copper, and H is the separation between planes.
Provide return-path capacitors that connect to both power planes and jumps the split. Place them close to the traces so that there is one capacitor for every four or five traces. The capacitors would then provide the return path (see Figure 4-4).
Allow only static or slow signals on layers where they are adjacent to split planes.
Figure 4-3 shows the ground layer close to the split power plane.
Figure 4-3 Close Power and Ground Planes Provide Coupling For Good Return Path
Figure 4-4 shows the thermal ground plane in relation to the return-path capacitor.
Figure 4-4 Suggested Thermal Ground Plane On Opposite Side of Chip
C 1.249 10 13–• Er• L• W H⁄•=
V2 PLANE
GND PLANE
V1 PLANEH
V1
V2
5-1
Copyright © 2016 Marvell Doc No. MV-S108467-00 Rev. CJanuary 27, 2016 Document Classification: Proprietary
Electrical Specifications
5 ELECTRICAL SPECIFICATIONS
This chapter contains the following information:
Absolute Maximum Ratings
Recommended Operating Conditions
Power Requirements
DC Electrical Characteristics
Thermal Data
88SE9235 R1.1 Two-Lane PCIe 2.0 to Four-Port 6 Gbps SATA I/O Controller Datasheet
5-2 Absolute Maximum Ratings
Copyright © 2016 Marvell Doc No. MV-S108467-00 Rev. CJanuary 27, 2016 Document Classification: Proprietary
5.1 Absolute Maximum Ratings
Table 5-1 defines the absolute maximum ratings for the 88SE9235.
Table 5-1 Absolute Maximum Ratings*
* Estimated values are provided until characterization is complete.
Parameter Symbol Minimum Maximum Units
Absolute Analog Power for PCIe PHY AVDD0abs -0.5 1.98 V
Absolute Analog Power for PCIe PHY AVDD1abs -0.5 1.98 V
Absolute Analog Power for Crystal Oscillator and PLL VAA1abs -0.5 1.98 V
Absolute Analog Power for SATA PHY VAA2_0abs -0.5 1.98 V
Absolute Analog Power for SATA PHY VAA2_1abs -0.5 1.98 V
Absolute Digital Core Power VDDabs -0.5 1.10 V
Absolute Digital I/O Power VDDIOabs -0.5 3.63 V
Electrical Specifications
Recommended Operating Conditions 5-3
Copyright © 2016 Marvell Doc No. MV-S108467-00 Rev. CJanuary 27, 2016 Document Classification: Proprietary
5.2 Recommended Operating Conditions
Table 5-2 defines the recommended operating conditions for the 88SE9235.
Table 5-2 Recommended Operating Conditions*
* Estimated values are provided until characterization is complete.
Parameter Symbol Minimum Type Maximum Units
Analog Power for PCIe PHY AVDD0op 1.71 1.8 1.89 V
Analog Power for PCIe PHY AVDD1op 1.71 1.8 1.89 V
Analog Power for Crystal Oscillator and PLL VAA1op 1.71 1.8 1.89 V
Analog Power for SATA PHY VAA2_0op 1.71 1.8 1.89 V
Analog Power for SATA PHY VAA2_1op 1.71 1.8 1.89 V
Digital Core Power VDDop 0.95 1.0 1.05 V
Digital I/O Power VDDIOop 3.135 3.3 3.465 V
Internal Bias Reference ISETop 5.738 6.04 6.342 KΩ
Ambient Operating Temperature, Commercial
N/A 0 N/A 85 °C
Ambient Operating Temperature, Industrial N/A -40 N/A 85 °C
Junction Operating Temperature, Commercial
N/A 0 N/A 125 °C
Junction Operating Temperature, Industrial N/A -20 N/A 125 °C
88SE9235 R1.1 Two-Lane PCIe 2.0 to Four-Port 6 Gbps SATA I/O Controller Datasheet
5-4 Power Requirements
Copyright © 2016 Marvell Doc No. MV-S108467-00 Rev. CJanuary 27, 2016 Document Classification: Proprietary
5.3 Power Requirements
Table 5-3 defines the power requirements for the 88SE9235.
Table 5-3 Power Requirements*
* Estimated values are provided until characterization is complete.
Parameter Symbol Maximum Units
Analog Power for PCIe PHY Transmitter IAVDD0 55 mA
Analog Power for PCI-E Phy Transmitter IAVDD1 55 mA
Analog Power for Crystal Oscillator and PLL IVAA1 10 mA
Analog Power for SATA PHY IVAA2_0 70 mA
Analog Power for SATA PHY IVAA2_1 70 mA
Digital Core Power IVDD 1500 mA
Digital I/O Power (3.3V)†
† The digital I/O power supply can be either 3.3V or 1.8V.
IVDDIO 50 mA
Electrical Specifications
DC Electrical Characteristics 5-5
Copyright © 2016 Marvell Doc No. MV-S108467-00 Rev. CJanuary 27, 2016 Document Classification: Proprietary
5.4 DC Electrical Characteristics
Table 5-4 defines the DC electrical characteristics for the 88SE9235.
Table 5-4 DC Electrical Characteristics*
* Estimated values are provided until characterization is complete.
Parameter Symbol Test Condition Minimum Maximum Units
Input Low Level Voltage VIL N/A -0.4 0.25 × VDDIO V
Input High Level Voltage VIH N/A 0.8 x VDDIO
5.5 V
Output Low Level Current IOL VPAD = 0.4V 5 N/A mA
Output High Level Current IOH VPAD = VDDIO – 0.4V 5 N/A mA
Pull Up Strength IPU VPAD = 0.5 x VDDIO 10 N/A µA
Pull Down Strength IPD VPAD = 0.5 x VDDIO 10 N/A µA
Input Leakage Current ILK 0 < VPAD < VDDIO N/A 10 µA
Input Capacitance CIN 0 < VPAD < 5.5V N/A 5 pF
88SE9235 R1.1 Two-Lane PCIe 2.0 to Four-Port 6 Gbps SATA I/O Controller Datasheet
5-6 Thermal Data
Copyright © 2016 Marvell Doc No. MV-S108467-00 Rev. CJanuary 27, 2016 Document Classification: Proprietary
5.5 Thermal Data
It is recommended to read application note AN-63 Thermal Management for Selected Marvell® Products (Document Number MV-S300281-00) and the ThetaJC, ThetaJA, and Temperature Calculations White Paper, available from Marvell, before designing a system. These documents describe the basic understanding of thermal management of integrated circuits (ICs) and guidelines to ensure optimal operating conditions for Marvell products.
Note: In addition to the airflow requirement, a heat sink is required to assist the thermal dissipation.
Table 5-5 provides the thermal data for the 88SE9235. The simulation was performed according to JEDEC standards.
Table 5-5 shows the values for the package thermal parameters for the 76-lead Quad Flat Non-Lead package (QFN 76) mounted on a 4-layer PCB.
Table 5-5 Package Thermal Data
Parameter DefinitionAirflow Value
0 m/s 1 m/s 2 m/s 3 m/s
θJA Thermal resistance: junction to ambient
29.9 C/W 26.6 C/W 25.5 C/W 24.8 C/W
ΨJB Thermal characterization parameter: junction to bottom surface center of the package.
15.60 C/W 15.59 C/W 15.58 C/W 15.57 C/W
ψJT Thermal characterization parameter: junction to top center
0.63 C/W 0.93 C/W 1.17 C/W 1.34 C/W