Mark Raymond - 7/9/06 1 TFB hardware status – 7/9/06 some things to discuss and questions to address TFB PCB layout status LV power, connector and cabling signal connectors (RJ45 + what to use for trig.) slow control/monitoring functionality component procurement timescale
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Mark Raymond - 7/9/061 TFB hardware status – 7/9/06 some things to discuss and questions to address TFB PCB layout status LV power, connector and cabling.
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Mark Raymond - 7/9/06 1
TFB hardware status – 7/9/06
some things to discuss and questions to address
TFB PCB layout statusLV power, connector and cablingsignal connectors (RJ45 + what to use for trig.)slow control/monitoring functionalitycomponent procurementtimescale
Mark Raymond - 7/9/06 2
cooled Al mounting plate
thermal gap filler
TFB
TFB mounting plan for ECAL
TFB mounted on cooled Al plate with cutouts through which SiPM cables are fed
min. coax connectors (and other connectors) on top surface
chips to be cooled on bottom surface, in thermal contact with platethermal gap filler allows for differences in chip thicknesses
power regs. on top side – dissipating heat to board – so will need to provide good thermal pathwayto mounting plate in this area of TFB
to SiPM
coax socket~2 mm dia.
terminated coax cable (1.3 mm dia.)
Mark Raymond - 7/9/06 3
coaxial connectors on top surface
trip-t, FPGA, HVtrimDACs on bottom (can be thermally coupled to cooling)
ADCs, regulators, connectors on top surface
6 routing layers top, bottom + 4 internal
+ power and ground layersso maybe 10 layers overall?
signal routing ~ complete
TFB PCB layout status~
9 c
m
~ 14.5 cm
not yet implemented FPGA config. cct, JTAG I/F, LEDs, mounting holes, test points, power and ground planes, …
board may have to grow in the long direction – maybe back to 16 cm or more – is that acceptable?
~ 16 cm
Mark Raymond - 7/9/06 4
TFB onboard LV power regulators
supply after reg. component current [A] circuitry supplied power on TFB [W]
1.5 -1.7 1.2 LP38843ES-1.2 < 3 FPGA core 3.6
2.5 A <0.5 trip-t 1.32.95 - 3.1 LP3856ES-2.5
2.5 D ~1.05 FPGA 2.5 2.6
3.8 3.3 D LP3856ES-ADJ ~0.95 FPGA I/O 3.1
5.5 5 A LP3856ES-5.0 <0.2 ADCs / HVtrimDACs 1
5.7 return 11.6
all TO263-5 packages with shutdown inputs (=> one line from outside (where?) couldbe used to power down an individual TFB)
some other small regulators on board to supply PROM, slow control cct., but low power requirementsand can take inputs from above supply levels
dropout depends oncurrent – should prob.take worst case
Mark Raymond - 7/9/06 5
power connector
propose 26 way, dual row, 0.1” pitch MOLEX connector, 3A/pin rated doesn’t have to be but this is relatively compact
HVHV1.21.2
1.2 sense2.52.5
2.5 sense3.33.3
3.3 sense55
gndgndgndgndgndgndgndgndgndgndgndshutdown5 sense
some questions
who provides the cabling – do we make it ourselves?
48 TFBs per power group – how/where do we split the incomingpower lines to feed individual TFBs?
how can we make use of regulator shutdown to disable individual TFBs?
fuses? (regulators include overcurrent/overtemperature protection)
HV only decoupled on entering board – no onboard disconnect switchat present. A shorted SiPM will draw current but series resistancewill limit.
voltages after regulation on TFB – actual levels will be higheruse 2 pins/supplyabove distribution an example – not final
Mark Raymond - 7/9/06 6
signal connectors
datascreened RJ45 - 4 twisted pairs
data indata out100 MHz clocktriggering line (spill start, spill no., cosmic, calibration?)
trigger outonly one twisted pair/TFBhas to eventually feed RJ45 on GTMcan we use small connector on TFB and merge signals into RJ45 cable using anintermediate board?what small connector can we use? any ideas? firewire?
Mark Raymond - 7/9/06 7
slow control (monitoring)
single channel AD5321 DAC 0 -> 5V, 12 bit resolution, for trip-t electronic calibration
8 channel AD7998ADC, 0 -> 4.096 (external AD1584 ref.), 12 bit resolution, for monitoring
both chips with I2C interface controlled by FPGA
allocation of ADC inputs
1 1.2V supply2 2.5V supply3 3.3V supply4 5V supply (divided down)5 HV global (divided down)6 electronic cal voltage (divided down)7 LM335 temperature sensor on TFB pcb8 not yet allocated
is this enough? do we need connector for external temperature sensor?
Mark Raymond - 7/9/06 8
active component procurement
compnt. function #/TFB supplier/comments
tript 4 Fermilab can supply 100 packaged and tested chips, $20 each (payment details need attention)
AD9201 tript O/P ADC 2 FarnellSpartan3 FE-FPGA 1 in stock at ICPROM for FPGA config. 1 RSAD5308 8 bit HVtrimDAC 8 FarnellFDV303N CAL FET 16 FarnellAD5321 CAL DAC 12 bit 1 FarnellAD7998 12 bit ADC monitoring 1 FarnellAD1584 monitoring Vref 1 FarnellLP38843S-1.2 1.2 V reg. 1 FarnellLP3856ES-2.5 2.5V reg. 1 FarnellLP3856ES-5.0 5 V reg. 1 FarnellLP3856ES-ADJ 3.3 V reg. 1 FarnellLM335 temp. sensor 1 FarnellBSN20 mosfets I2C level shift 2 Farnell
+ some others
Need to think about quantities to buy now, may need to 2nd source if stock problemswhat budget to use?do we need to worry about RoHS compliance?
Mark Raymond - 7/9/06 9
timescale
still a few weeks work left on layout
need to procure components now (for ~ 20 boards)
suggest to produce 2 boards quickly - hopefully by end October
produce more, on slower timescale, after no major (electrical) problems identified
testing needs some thought….
Mark Raymond - 7/9/06 10
Mark Raymond - 7/9/06 11
Trip-t and TFB status
Trip-t brief description of internal architecture and interfacesproposed Trip-t operation at T2KSiPM connection, gain and discriminator threshold considerations
Results from latest Tript versionlinearity and discriminator measurements
TFB prototype statusresults from prototyping elements
ADC functionality and test results HVtrim functionality and test results Calibration circuitt description and test results
TFB layout statusTFB firmware status
future plansDRAFT TALK – NOT YET FINISHED
Mark Raymond - 7/9/06 12
Trip-t single channel front end architecture
preamp
very simplified – neglecting features not relevant to ND280 operation
integrate/reset
gain 1 or 4
gain adjust1,2,3,…8
x10
Vth
analogue pipeline
disc. O/P
Qin
only preamp gain affects signal feeding discriminator – no fine control (x1 or x4)Vth common to all channels on chipanalog bias settings, gain, Vth, programmable via serial interface
discriminator
1pF
3pF
reset
Mark Raymond - 7/9/06 13
Trip-t full chip
32 channel chip -> 1 serial output, 48 deep analogue pipeline to store sampled front end outputs (note: pipeline operated using 2 timeslices/preamp integration period, so length reduced to 23
see http://www.hep.ph.ic.ac.uk/~dmray/pdffiles/FIFOtalk_1_3_06 for detailed explanation)
have to select either top or bottom 16 disc. O/Ps to transmit off-chip
~ 12 digital control/programming inputs, 16 disc. outputs => ~ 30 I/O lines/chip (2.5 V CMOS)
32front end
chans
top16 IP/s
bottom16 I/Ps
analogue memory(pipeline)
48
3232 analogoutputs
top 16 disc. O/Ps
bottom 16 disc. O/Ps
top or bottom16 disc. O/Ps
32
32:1analogMUX
serialanalogoutput
dig.MUX32:16
bias, control, reset control
control control
serial programminginterface, bias gen.,control interface, …
dig.control
simplified and neglecting features not relevant to operation in ND280
Mark Raymond - 7/9/06 14
Proposed mode of Trip-t operation for beam spill data acquisition is as follows
during spillintegrate signal for each bunch and store result in pipeline* (15 timeslices for 15 bunches)timestamp high gain channel discriminator outputs that fire
after spillcontinue running in same way, for a while, to catch late signals ( decay)readout entire contents of pipelineassemble data block containing hit timestamps and all digitized analogue data and transmit
transmitting all info in this way allows histogramming of single p.e. events to monitor SiPM gainvast majority of data is pedestal + single/double p.e. hits only
Trip-t operation at T2K
5.25 sspill period
2.8 safter spill
active period
74 s (23 cell) readout period(if O/P mux running at 10 MHz)
start of spill end of spillat this time trip-t switches
to inter-spill operational mode(cosmic trigger)
Mark Raymond - 7/9/06 15
Tript for ND280, gain considerations
need ~ 500 p.e. dynamic range, while simultaneously discriminating signals at the ~ 1p.e. levelcan’t be done with one gain range => split signal between high/low gain ranges (channels)Signal shared between Cadd, Chi and Clo (also some strays), Chi/Clo = high/low gain ratio
HVglobal
1 M
50
thin coax
SiPM
trip-tChi100pF
Clo10pF
Cadd330pFHVtrim
Choose Cadd to match final SiPM gain (330pF about right for 5x105)Cadd also helps with gain discontinuity when hi gain channel saturates(see http://www.hep.ph.ic.ac.uk/~dmray/pdffiles/tript_talk_1_3_06)
don’t know what final SiPM gain will be, but assume production devices will be quite well matchedin any case will have individual channel gain adjustment by HVtrimDACs
simplified single SiPM channel schematic
Mark Raymond - 7/9/06 16
Discriminator threshold (Vth) considerations
x10
1pF
reset
Vth
disc. O/P
analoguepipeline
Qin
Vth only relevant to the 16 high gain channels - remember only 16 channels can be selected for transmission off-chip, so just arrange for these to be the high gain channels
(Vth also applied to low gain channels, but we don’t need to look at the outputs of these)
Vth needs to be set high enough to prevent single p.e. events triggering discriminator (otherwise single p.e. triggers will dominate and will lose ability to timestamp real signals)
uncertainty in threshold setting given by spread in discriminator turn-on curves across chip
can choose high gain channel value (external capacitor division ratio) but trade-off between threshold adjustment range and uncertainty in threshold value
Mark Raymond - 7/9/06 17
x10
1pF
reset
Vth
disc. O/P
analoguepipeline
Qin
~ 1V dynamic range available at preamp O/P ~ similar voltage range
at x10 amp O/P~ similar disc. thresh.
voltage adjustment range
2.5 V CMOS so can assume dynamic ranges of internal circuits ~ 1V
this has implications for discriminator threshold range
if want 0 – 5 p.e. adjustment range then 5 p.e. ≡ 1V at x10 O/P=> 1V ≡ 50 p.e. at preamp O/Pso high gain channel will saturate at ~ 50 p.e.
this translates to threshold uncertainty ~ +/- 0.5 p.e. (measured – see later)
Gain and gain ratio considerations (1)
single triptchannel
Mark Raymond - 7/9/06 18
So discriminator threshold range adjustment 0 -> 5 p.e.
High gain channel saturates at 50 p.e.
Choose Chi/Clo so low gain channel saturates at 500 p.e.
Note: These values are examples and can change, but need to take care withthreshold adjustment range/uncertainty trade-off
Gain and gain ratio considerations (2)
HV(TFB)
1 M
50
thin coax
SiPM
Trip-tChi100pF
Clo10pF
Cadd330pF
HVtrim
simplified single SiPM channel schematic
Mark Raymond - 7/9/06 19
Latest Trip-t test results from final version
2nd (final) tript version very similar to 1st
minor architecture change to improve O/P stage linearity
version 2 linearity clearly better but still some gain reduction for small signals
will need electronic calibration to correct for linearity
significant timewalk and chan-to-chan spread for small signals
can set threshold at 1.5 p.e. and discriminator will fire, but timestamp for low amplitude signals will not be reliable
OK for signals > ~ 3 p.e.
can correct for timewalk off-line
Mark Raymond - 7/9/06 24
TFB (Tript Front-end Board) prototype status
main functionality:
4 Tript’s/TFB => 64 SiPM channels (for ECAL) individual programmable HVtrim (5 V range) for each SiPM channel tript O/P signal digitisation front end electronic calibration FPGA to program tript, sequence operation, timestamp hits, control digitisation, format and transmit data, … local LV power regulation
prefer to prototype designs for individual functions as much as poss. before committing to final TFB prototype
results here for on-board ADC, HVtrim and electronic calibration circuits
Mark Raymond - 7/9/06 25
cal cct
HVtrimDACAD9201
SiPM
Tript
miniature coax and connectors
prototyping elements of TFB
necessary to proove as much of TFB circuitry as possible before committing to layouthelps to identify where extra layout care is neededimproves chances of TFB prototype working successfully
Mark Raymond - 7/9/06 26
47k50V, 0402
220pF50V0402
330pF100V0603
10pF100V0603
100pF100V0603
51RLV
0603
100nFLV
0402
1kLV, 0402
trip-t
10pF100V, 0603
HVglobal
HVtrim(0-5V)
cal testpulse
coax sheath not DCcoupled to GND
SiPM
SiPM -> TFB connection - details
47k50V, 0402
HVglobal: common to all SiPM channels on TFBHVtrim: individual for each SiPM channel, 5V adjustment range (choice of 8/10/12 bit DAC precision)HVtrim applied to coax sheath – AC but not DC coupled to GND
significant no. of passives/channel – need careful, high
density layout
Mark Raymond - 7/9/06 27
ADC for the TFB
AD9201 – used by D-zero
dual-channel => 2 tript’s/ADC
28 pin SSOP package
separate analog and digital supplies
5V analogue – needed to accommodate tript O/P range
3.3 V digital
Mark Raymond - 7/9/06 28
analog supply and ADC reference voltage configuration optimised so that tript output signals well matchedto 10 bit ADC range
1000
900
800
700
600
500
400
300
200
100
0
AD
C u
nits
4035302520151050
Qin [pC]
high gain channel low gain channel
tript linearity measured with AD9201
Mark Raymond - 7/9/06 29
SiPM signals measured with tript/AD9201
3000
2500
2000
1500
1000
500
0
coun
ts (
with
LE
D)
260240220200180160140
ADC units
14x103
12
10
8
6
4
2
0
counts (no LED
)
with LED pulse no LED pulse
Russian SiPM: gain 5.6x105
275 ns preamp integration period
100,000 events in each spectrum
~ 10 ADC units / p.e.=> 0.1 p.e. ADC resolution
Mark Raymond - 7/9/06 30
HV trim circuit for TFB
51RLV
0603
100nFLV
0402
1kLV, 0402
HVtrim(0-5V)
coax sheath carriesHVtrim voltage
SiPM
HVglobal
8 channel DAC chip => 2 / tript, 8 / TFB
8/10/12 bit versions availableidentical chips, just different resolution(price difference but negligible to us)
TSSOP 16 pin SM package
serial interface to program (from FE FPGA)
output voltage variable 0 -> 5 V20 mV resolution for 8 bit version
Mark Raymond - 7/9/06 31
TFB HV trim circuit linearity
5
4
3
2
1
0
Out
put
volta
ge
250200150100500
DAC value
-4
-2
0
2
4
residuals [mV
]
8 bit DAC version used here
gives 20 mV precision for 5 V range should be enough?