March 9, 2011 CS152, Spring 2011 CS 152 Computer Architecture and Engineering Lecture 12 - Advanced Out-of- Order Superscalars Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley http://www.eecs.berkeley.edu/~krste http://inst.eecs.berkeley.edu/~cs152
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March 9, 2011CS152, Spring 2011 CS 152 Computer Architecture and Engineering Lecture 12 - Advanced Out-of-Order Superscalars Krste Asanovic Electrical.
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March 9, 2011 CS152, Spring 2011
CS 152 Computer Architecture and
Engineering
Lecture 12 - Advanced Out-of-Order
Superscalars
Krste AsanovicElectrical Engineering and Computer Sciences
In-order execution machines:– Assume no instruction issued after branch can write-back before
branch resolves– Kill all instructions in pipeline behind mispredicted branch
– Multiple instructions following branch in program order can complete before branch resolves
Out-of-order execution?
March 9, 2011 CS152, Spring 2011 4
In-Order Commit for Precise Exceptions
• Instructions fetched and decoded into instruction reorder buffer in-order• Execution is out-of-order ( out-of-order completion)• Commit (write-back to architectural state, i.e., regfile & memory, is in-order
Temporary storage needed in ROB to hold results before commit
Fetch Decode
Execute
CommitReorder Buffer
In-order In-orderOut-of-order
KillKill Kill
Exception?Inject handler PC
March 9, 2011 CS152, Spring 2011 5
Branch Misprediction in Pipeline
Fetch Decode
Execute
CommitReorder Buffer
Kill
Kill Kill
• Can have multiple unresolved branches in ROB• Can resolve branches out-of-order by killing all the instructions in ROB that follow a mispredicted branch• Must also kill instructions in-flight in execution pipelines
BranchPrediction
PC
Inject correct PC
BranchResolution
Complete
March 9, 2011 CS152, Spring 2011 6
t vt vt v
Take snapshot of register rename table at each predicted branch, recover earlier snapshot if branch mispredicted
Rename Snapshots
Recovering ROB/Renaming Table
Register File
Reorder buffer Load
UnitFU FU FU Store
Unit
< t, result >
t1
t2
.
.tn
Ins# use exec op p1 src1 p2 src2 pd dest data
Commit
Rename Table r1
t v
r2
Ptr2 next to commit
Ptr1 next available
rollback next available
March 9, 2011 CS152, Spring 2011 7
“Data-in-ROB” Design(HP PA8000, Intel Pentium Pro, Core2 Duo & Nehalem)
• On dispatch into ROB, ready sources can be in regfile or in ROB dest (copied into src1/src2 if ready before dispatch)
• On completion, write to dest field and broadcast to src fields.• On issue, read from ROB src fields
Reorder buffer used to hold exception information for commit.
The instruction window holds instructions that have been decoded and renamed but not issued into execution. Has register tags and presence bits, and pointer to ROB entry.
op p1 PR1 p2 PR2 PRduse ex ROB#
ROB is usually several times larger than instruction window – why?
Rd LPRd PC Except?Ptr2
next to commit
Ptr1 next available
Done?
March 9, 2011 CS152, Spring 2011 22
Reorder Buffer Holds Active Instructions(Decoded but not Committed)
Superscalar Register Renaming• During decode, instructions allocated new physical destination register• Source operands renamed to physical register with newest value• Execution unit only sees physical register numbers
Rename Table
Op Src1 Src2Dest Op Src1 Src2Dest
Register Free List
Op PSrc1 PSrc2PDestOp PSrc1 PSrc2PDest
UpdateMapping
Does this work?
Inst 1 Inst 2
Read Addresses
Read Data
Wri
te
Port
s
March 9, 2011 CS152, Spring 2011 24
Superscalar Register Renaming
Rename Table
Op Src1 Src2Dest Op Src1 Src2Dest
Register Free List
Op PSrc1 PSrc2PDestOp PSrc1 PSrc2PDest
UpdateMapping
Inst 1 Inst 2
Read Addresses
Read Data
Wri
te
Port
s=?=?
Must check for RAW hazards between instructions issuing in same cycle. Can be done in parallel with rename lookup.