Marc Riedel The Synthesis of Stochastic The Synthesis of Stochastic Logic for Nanoscale Logic for Nanoscale Computation Computation IWLS 2007, San Diego May 31, 2007 A B C { { N W ires M W ires Weikang Qian and John Backes Circuits & Biology Lab, University of Minnesota joint work with
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Marc Riedel The Synthesis of Stochastic Logic for Nanoscale Computation IWLS 2007, San Diego May 31, 2007 Weikang Qian and John Backes Circuits & Biology.
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Marc Riedel
The Synthesis of Stochastic Logic for The Synthesis of Stochastic Logic for Nanoscale ComputationNanoscale Computation
The Synthesis of Stochastic Logic for The Synthesis of Stochastic Logic for Nanoscale ComputationNanoscale Computation
IWLS 2007, San Diego May 31, 2007
A
B
C {
{
N Wires
M Wires
Weikang Qian and John Backes Circuits & Biology Lab, University of Minnesota
joint work with
5/31/07 IWLS 2007 2
Computing Beyond CMOSComputing Beyond CMOS
Intense research into novel materials and devices:
Carbon Nanotubes…
Molecular Switches…
Biological Processes…
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Computing Beyond CMOSComputing Beyond CMOS
Many technologies still in exploratory phase:
b
a
XOR(a, b) !
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Nanoscale CircuitsNanoscale Circuits
• Topological constraints.• Inherent randomness.• High defect rates.
Features:
Challenges:
• High density of bits.
Identify general traits that impinge upon logic synthesis:
{
{
N Wires
M Wires
carbon nanowire crossbar
Circuit Modeling Circuit Modeling
logic
0
1
0
0
1
Characterize probability of outcomes.
inputs outputs
Model defects, variations, uncertainty, etc.:
Circuit Modeling Circuit Modeling
logic
),,( 11 mxxf a
),,( 12 mxxf a
),,( 1 mn xxf a
1x
2x
mx
Functional description is Boolean:
inputs outputs
1x
2x
mx
Consider a probabilistic interpretation:
),,( 11 mxxp
),,( 12 mxxp
),,( 1 mn xxp
logicstochastic
logic
inputs outputs
Circuit Modeling Circuit Modeling
stochasticlogic
Stochastic Logic Stochastic Logic
inputs outputs
0
1
0
0,1,1,0,1,0,1,1,0,1,…
1,0,0,0,1,0,0,0,0,0,…
p1 = Prob(one)
p2 = Prob(one)
serial bit streams
Consider a probabilistic interpretation:
stochasticlogic
Stochastic Logic Stochastic Logic
inputs outputs
0
1
0 51
52
Consider a probabilistic interpretation:
stochasticlogic
Stochastic Logic Stochastic Logic
0
1
0
01001
01000
p1 = Prob(one)
p2 = Prob(one)
parallel bit streams
Consider a probabilistic interpretation:
stochasticlogic
Stochastic Logic Stochastic Logic
0
1
0
parallel bit streams
51
52
Consider a probabilistic interpretation:
stochasticlogic
Stochastic Logic Stochastic Logic
Interpret outputs according to fractional weighting:
0
1
0
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Synthesis of Stochastic LogicSynthesis of Stochastic Logic
• Circuit that computes a probability distribution corresponding to a logical specification.
Given a technology characterized by:
Synthesize:
• High degree of structural parallelism.• Inherent randomness in logic/interconnects.
• Cast problem in terms of arithmetic operations.• Perform synthesis with binary moment diagrams.
Strategy:
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A real value x in [0, 1] is encoded as a stream of bits X.For each bit, the probability that it is one is: P(X=1) = x.
Probabilistic BundlesProbabilistic Bundles
01001
xX
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Arithmetic OperationsArithmetic Operations
AND
A
BC
A
BC
MUX
S
Multiplication (Scaled) Addition
ba
BPAP
CPc
)()(
)(
)
)1(
()](1[)()(
)(
bsas
BPSPAPSP
CPc
5/31/07 IWLS 2007 16
When A is a high, a FET-like region causes high resistance between the VDD and A.