Maintaining Data Integrity in Maintaining Data Integrity in Programmable Logic in Atmospheric Programmable Logic in Atmospheric Environments through Environments through Error Detection Error Detection Joel Seely Technical Marketing Manager Military & Aerospace Business Unit
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Maintaining Data Integrity in Programmable Logic in Atmospheric Environments through Error Detection Joel Seely Technical Marketing Manager Military &
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Maintaining Data Integrity in Maintaining Data Integrity in Programmable Logic in Atmospheric Programmable Logic in Atmospheric
Environments through Environments through Error DetectionError Detection
Joel SeelyTechnical Marketing Manager
Military & Aerospace Business Unit
Single Event Upset (SEU) Single Event Upset (SEU) Overview for SRAM-Based Overview for SRAM-Based
SER Improvements/MitigationSER Improvements/Mitigation
Chip Design Enhancements New Materials & Process Enhancements Larger CRAM Structure Increase in Capacitance on Critical Node Smaller Process => Smaller Die => Lower
SEU Probability Built-In Error Detection/Correction Circuitry
On-Chip SEU Detection Dedicated Comparison Circuitry
e.g. CRC Engine Comparing Stored CRC with That Calculated from Configuration RAM
Detection Circuitry Running Continuously Error Detection Rate Variable Based on Implementation of
Hardware, Number of CRAM Bits & Input Clock Frequency Error Signal Available Internally or ExternallyCaveat: Cannot Determine Where in Configuration Error Occurred
Single System Detection & CorrectionSingle System Detection & Correction
Step One: Detect the Soft Error 75% of Reported Errors Are “Don’t Care” Errors
Step Two: Alert the System Step Three: Fix the Error
In Some Cases, Re-Program the FPGA In Some Cases, Reboot the Sub-System In Some Cases, Reboot the System
Need to Focus on System “Downtime” Each System Has Unique Requirements Re-Programming FPGA Takes < 250 ms Rebooting Time Varies & Can Be Fast “by Design”