Mahin Arm Ppt

RISC CONCEPTS WITH

BY : MAHIN BASHA SYED 1005-10-744406

EVOLUTION OF CISC AND RISC CONCEPTSRISC VS CISC INTRODUCTION TO ARM PROCESSOR FAMILY OF ARM BLOCK DIAGRAM OF ARM REGISTERS DIAGRAM3 STAGE PIPELINED ARM 5 STAGE PIPELINED ARM INSTRUCTION SETS OF ARMDEVELOPMENTS IN ARM ADVANTAGES OF WHY PREFER ARMAPPLICATION REFERENCES

Out lines

THE ART OF PROCESSOR DESIGN IS TO DEFINE AN INSTRN SET THAT SUPPORTS FUNCTIONS

WHAT SORT INSTRN SET MAKES A GOOD COMPILER TARGET

cisc evolution

WHY DOES COMPILER NEEDED???

THE SEMANTIC GAP BETWEEN A HIGH LEVEL LANGUAGE CONSTRUCT AND A MACHINE INSTRN IS BRIDGED BY COMPILER

COMPILER

HIGH LEVEL

LANGUAGE

MACHINE INSTRN SET

COMPILER TARGET ??

THE AIM OF PROCESSOR DESIGN SHOULD DEFINE HIS OR HER INSRTN SET TO BE GOOD COMPILER TARGET

COMPLEXITY

THIS LEDS TO THE CISC DEVELOPMEENT

SEMANTIC GAP BY COMPILER

MINI COMPUTERS DEVELOPED WHICH

HAS MAIN MEMORY CONTROLLED BY MICRO CODE ROMS WHICH ARE FASTER THAN MAIN MEMORY

MINI COMPUTERS USES CISCIN 1970, MICRO PROCESSORS

DEVEL0PED FASTLY IN SEMICONDUCTOR INDUSTRY BUT MICRO CODE ROM IS NEEDED FOR ALL COMPLEX ROUTINES

CISC IS NOTHING BUT MP WITH MINICOMPUTER INSTRN SET

CISC is an acronym for Complex Instruction Set Computer and are chips that are easy to program and which make efficient use of memory. Since the earliest machines were programmed in assembly language and memory was slow and expensive,

WHAT IS CISC ??

RISC evolution INSTRN TYPE

DYNAMIC USAGE

IN %DATA MOVEMENT 43 CONTROL FLOW 23 ARITHMETIC OPERATION 15COMPARISIONS 13

LOGICAL OPERATIONS 5`OTHERS 1

RISC, or Reduced Instruction Set Computer. is a type of microprocessor architecture that utilizes a small, highly-optimized set of instructions, rather than a more specialized set of instructions often found in other types of architectures.

WHAT IS RISC ??

RISC VS CISC Sr. No

RISC CISC

1 Simple instructions taking 1 cycle.

Complex instructions taking multiple cycles.

2 Only LOADS/STORES reference memory.

Any instruction may reference memory.

3 Highly pipelined Not pipelined or less pipelined.

4 Instructions executed by the hardware.

Instructions interpreted by the microprogram.

5 Fixed format instructions.

Variable format instructions.

6 Few instructions and modes.

Many instructions and modes.

7 Complexity is in the compiler.

Complexity is in the microprogram.

8 Multiple register sets.

Single register set.

FIXED LENTH INSTRUCTION 32 BIT

LOAD STORE ARCHITECTUREFEWER ADDRESSING MODES INSTRUCTION PIPELINE LARGE NUMBER OF REGISTERSDELAYED LOADS AND BRACHESSEPARATE INSTRN AND DATA STREAMS

RISC ARCHITECTURAL FEATURES

EVOLUTION OF ARM

Founded in 1990. ARM -Advanced Risc Machines

32bit RISC processor from ARM Holdings.

ARM Holding is a joint venture between Acron computers, Apple computers and VLSI Technology.

Features used

Features rejected

Load - strore architecture

Register window

Fixed length 32 bit instructions

Delayed branches

3 –address instruction formats

Single cycle excution of all instructions

features

The combination of the simple hardware with an instruction set that is grounded in risc ideas but retains a few key cisc features

The ARM achieves a significantly better code density and power efficiency and its smalll core size.

cont…

ARM:• 32-bit RISC-processor core (32-bit instructions)• 37 pieces of 32-bit integer registers (16 available)• Pipelined (ARM7: 3 stages)• Cached (depending on the implementation)• Von Neuman-type bus structure (ARM7), Harvard

(ARM9)• 8 / 16 / 32 -bit data types• 7 modes of operation (usr, fiq, irq, svc, abt, sys,

und)• Simple structure -> reasonably good speed / powerconsumption ratio

ARM REVISION PROSCESSORS CORE

ARM V 1 ARM 1

ARM V2 ARM 2

ARM V 2a ARM 3

ARM V 3 ARM 6 and ARM 7DI

ARM V 3M ARM 7M

ARM V4 STORNG ARM

ARM V 4T ARM 7 TDMI and ARM 9T

ARM V5 TE ARM 9E and ARM 10 E

ARM V STEJ ARM 7EJ and ARM 926EJ

ARM V6 ARM 11

family of arm

T: Thumb D: On-chip debug support M: Enhanced multiplierI: Embedded ICE hardware T2: Thumb-2 S: Synthesizable code E: Enhanced DSP instruction set J: JAVA support, Jazelle Z: Should be TrustZone? F: Floating point unit H: Handshake, clockless design for synchronous orasynchronous design

NOMENCLATURE

ARM {X}{Y}{Z}{T}{D}{M}{I}{E}{J}{F}{S}

ARM TDM7I

CD

MAC

SIGN EXTENDED

REGISTER FILES R0 R15

BARREL SHIFTER

ADDRESS REGISTER

INCREMENT

ALU

INSTRN DECODERWRIT

EREAD

Rd

ADDRESS

DATA

CD BASIC MODEL OF ARM

3 STAGE PIPELINING

REGISTERS OF ARM

ARM7 register set thirty-seven 32bit registers.30 are general purpose registers 16 general purpose registers(R0 to R15) are

available in ARM-mode (user mode)• Register structure depends on mode of operation• R13 - Stack Pointer (SP)• R14 - subroutine Link Register for branch and link

instructions• R15 - Program Counter (PC)• R16 - state register (CPSR, Current Program

Status Register)

Abort Mode

r0 r1 r2 r3 r4 r5 r6 r7 r8 r9

r10 r11 r12

r15 (pc)

cpsr

r13 (sp) r14 (lr)

spsr

r13 (sp) r14 (lr)

spsr

r13 (sp) r14 (lr)

spsr

r13 (sp) r14 (lr)

spsr

r8 r9

r10 r11 r12

r13 (sp) r14 (lr)

spsr

Current Visible Registers

Banked out Registers U

ser

FIQ

IRQ

SVC

Undef

r13 (sp) r14 (lr)

Register Organization Summary

CPSR-Current program status register

CPSR holds execution status of the processor,processor operation mode,interrupt enable bit status,etc.

N=1:The result of ALU operation is negative. Z=1:The result of ALU operation is zero. C=1:carry generated as a result of the operation executed in

ALU. V=1:ALU operation resulted in overflow. ‘J’ bit : whether the processor is Jazelle state or not . ‘T ‘ bit : whether the ARM is using 32-bit ARM instructions or

16-bit Thumb instructions. ‘I’ and ‘F’ flags are used for disabling interrupts. If I= 1,NORMAL interrupts are disabled. If F=1 ,FAST interrupts are disabled.

B31

B30 B29 B28 B27

B25 to B26

B24

B8 to B23

B7 B6 B5

B0 to B4

N Z C V Q J I F T Mode Select

OPERATING MODES 1. User Mode- Normal program execution state2. Fast Interrupt Processing (FIQ) Mode - when a high

priority interrupt is raised.3. Normal Interrupt Processing (IRQ) Mode- when a

normal priority interrupt is raised. 4. Supervisor /Software Interrupt Mode- Protected

mode for operating system support . Eg: when reset /software interrupt instruction is executed.

5. Abort Mode - when data or instruction fetch is aborted.

6. System Mode – for running Operating system tasks.7. Undefind Instruction Mode-when processor tries to

execute an undefined instruction.

7 MODES

Usermoder0-r7,r15,andcpsr

r8 r9

r10 r11 r12

r13 (sp) r14 (lr)

spsr

FIQ

r8 r9

r10 r11 r12

r13 (sp) r14 (lr) r15 (pc)

cpsr

r0 r1 r2 r3 r4 r5 r6 r7

User

r13 (sp) r14 (lr)

spsr

IRQ

Usermoder0-r12,

r15,andcpsr

r13 (sp) r14 (lr)

spsr

Undef

Usermoder0-r12,

r15,andcpsr

r13 (sp) r14 (lr)

spsr

SVC

Usermoder0-r12,

r15,andcpsr

r13 (sp) r14 (lr)

spsr

Abort

Usermoder0-r12,

r15,andcpsr

Thumb stateLow registers

Thumb stateHigh registers

Note: System mode uses the User mode register set

BARALLEL SHIFTER

Single bit rotate with wrap aroundfrom CF to MSB

DestinationCF 0 Destination CF

LSL : Logical Left Shift ASR: Arithmetic Right Shift

Multiplication by a power of 2 Division by a power of 2, preserving the sign bit

Destination CF...0 Destination CF

LSR : Logical Shift Right ROR: Rotate Right

Division by a power of 2 Bit rotate with wrap aroundfrom LSB to MSB

Destination

RRX: Rotate Right Extended

CF

BARREL SHIFTER

Result

Operand 1

BarrelShifter

Operand 2

ALU

Register, optionally with shift operationShift value can be either be:

5 bit unsigned integerSpecified in bottom byte of another

register.Used for multiplication by

constant

Immediate value8 bit number, with a range of 0-

255.Rotated right through even number

of positions Allows increased range of 32-bit

constants to be loaded directly into registers

Fetch instructionDecode instructionExecute instructionAccess operandWrite result

Note: Slight variations depending on processor

PIPELINE CONCEPT IN ARM

PIPELINE CONCEPT IN ARM

Clock Cycle 1 2 3 4 5 6 7 8 9 10

WITH OUT PIPELING

The processor is able to perform each stage simultaneously.

If the processor is decoding an instruction, it may also fetch another instruction at the same time.

WITH PIPELING

Clock Cycle 1 2 3 4 5 6 7 8 9

Instr 1

Instr 2

Instr 3

Instr 4

Instr 5

3 STAGE PIPELING

FETCH DECODE

FETCH

EXECUTE

FETCH

DECODE

EXECUTE

DECODE

EXECUTE

– Tprog: the time that executes a given program– Ninst: the number of ARM instructions executed

in theprogram => compiler dependent– CPI: average number of clock cycles per

instructions =>hazard causes pipeline stalls– fclk: frequency

INCREASE THE CLK RATES REDUCE THE AVERAG4E NUMBER OF CLK

CYCLES PER INSTRNS

Tprog = Ninst * CPI / fclk

WHY 5 STAGE PIPELING

FETCHDECOD

E ACCESS

OPERAND EXECUTE WRITE

FETCHDECOD

E ACCESS

OPERAND EXECUTE WRITE

FETCHDECOD

E ACCESS

OPERAND EXECUTE WRITE

5 STAGE PIPELING

5 STAGE PIPELING

V

INSTRN SETS OF ARM INSTRN SET

ARM THUMB JAZELLE

1. ARM Instruction Set-The original ARM

instruction.Here all instruction are 32bit wide and word aligned.since all instructions are word aligned,one single fetch reads four 8bit memory locations.

2. Thumb Instruction Set-These instructions can be considered as a 16bit compressed form of the orginal 32bit ARM instruction. These instructions can be executed by decompressing the instruction to the original 32bit ARM instructions

3. 3.Jazelle Instruction Set- Jazelle is a technique that allows Java Bytecode to be executed directly in the ARM architecturea.

Thumb is a 16-bit instruction setOptimised for code density from C code (~65% of ARM code size)Improved performance from narrow memorySubset of the functionality of the ARM instruction set

Core has additional execution state - ThumbSwitch between ARM and Thumb using BX instruction

015

31 0ADDS r2,r2,#1

ADD r2,#1

32-bit ARM Instruction

16-bit Thumb Instruction

For most instructions generated by compiler: Conditional execution is not used Source and destination registers identical Only Low registers used Constants are of limited size Inline barrel shifter not used

ARM10(TDMI)• ARM10TDMI processor core:• Realizes the ARM instruction set with

binary compatibility including the Thumbextension• Instruction set expanded to version 5

(v5TE), 32x16 MAC-multiplier• 6-stage pipeline for fixed point instructions42 © Ville Pietikäinen 2002

Embedded_3_ARM_2003.ppt / 19112002

HIGH CODE DENSITY PRICE SENSITIVEHARD WARE DEBUG TECHNOLOGYSMALL AREA

ADVANTAGES OF ARM

APPLICATIONS

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