This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
NXP and the NXP logo are trademarks of NXP B.V. All other product or service names are the property
• Minimize output voltage ringing caused by high rate of current change [di/dt] and parasitic components
(RLC) of the MOSFET packages, PCB traces
• Protect the MCU from damage caused by overvoltage on analogue power pins
• Tradeoff between speed of switching and EMC
• Thermal performance
• PCB manufacturing technology
• Cooling using passive heat-sink
• Price
• Optimize schematic and PCB layout such as to achieve required performance while keeping cost of
manufacturing as low as possible
PUBLIC 5
Project evolution• 1st Generation
Standard six layer stack-up PCB with increased cooper weight to 70um.
• 2nd Generation
Optimized layout regarding to the trace inductance
Standard four layer stack-up PCB with extended tin areas
• 3rd Generation
ICBERG PCB technology used to extend PCB current capability and thermal performance
Standard PCB material FR4
Varying copper thickness on one layer to increase current carrying capability of PCB traces
Updated layout, shorted MOSFET gate control signals
Small compact design
PUBLIC 6
HC PCB Design - Considerations02.
PUBLIC 7
PCB Traces Inductance
• All traces, pads and vias on PCB have some parasitic resistance, inductance and
capacitance (with respect to other traces/vias/planes)
• Inductance of a trace can be directly reduced by:
increased cross-sectional area of the trace
decreased length of the trace
• Thickness of PCB trace is limited, hence increasing cross-sectional area usually
means making the traces wider (plates)
parallel plate vs. coplanar plate
XX
PUBLIC 8
Power Inverter – High Current Path
PUBLIC 9
MOSFET Half Bridge with
Parasitic Components• Parasitic inductances LPCB_D and LPCB_S are affected by layout of power
traces and can be mitigated by
routing of power traces as close to each other as possible (preferable in different layers one on top of another) so that magnetic fields of forward and return currents will cancel out
• Parasitic inductances LG, LD and LS are MOSFET device internal and are affected by device package.
• Parasitic inductance LPCB_S carries commutation as well as load currents and forms a negative feedback to the input GS circuitry
reducing electrical field across GS capacitor, affecting ton/toff
can be mitigated by connecting the input gate-source traces as close to the MOSFET Source pin as possible
• Gate-Source parasitic inductance LPCB_GS , can be minimized by:
routing GS traces as close to each other as possible (preferable in different layers one on top of another) so that magnetic fields of forward and return currents will cancel out
minimizing the number of vias in GS loop
making the whole GS loop as short as possible
making GS traces as wide as possible
• Parasitic inductance of the current sensing shunt LSHUNT, can be reduced by routing positive DC power trace directly under the shunt resistor (same applies for LESR if power traces are one on top of another)
Magnetic fields of forward and return currents will cancel out
• To minimize crosstalk between top/bot GS circuitries, parasitic capacitance CPCB_GS_TOPBOT should be minimized, i.e. routing of top and bot GS loops shall be spatially separated
LOAD
+
D
S
G
LS
LD
LG
LPCB_S
D
S
G
LS
LD
LG
LPCB_D
LPCB_S
LPCB_GS
CPCB_GS
LPCB_D
LESR
RESR
CDCB
RSHUNT LSHUNT
UGS_BOTOM
UGS_TOP
LPCB_GS
LPCB_GS
Parasitic components
due to layout
Internal device
parasitic components
Preferred connection
of input source traces
LPCB_GS
CPCB_GS
CPCB_DCBUS
CPCB_GS_TOPBOT
PUBLIC 10
Example of Parallel Plate vs. Coplanar Plate Configuration
• Example of arrangement 30mils wide 5mils thick cooper traces with 5mils separation @ 50A current
• Total magnetic field energy of coplanar plate configuration is 3x larger than in parallel plate configuration
magnetic fields of forward and return currents cancel out