MA_Dalton.pdf - Hochschule Bochum

Masterthesis

zur Erlangung des akademischen GradesMaster of Science (M.Sc.)

Design and Implementation of

High-Speed Electronics for a

Spatial Filter Velocimeter

Autor: Sean William [email protected]: 013208208

Erstgutachter: Prof. Dr.-Ing. Arno BergmannZweitgutachter: M. Sc. Robert Schedlik

Abgabedatum: 9. October 2018

Eidesstattliche Erklärung

Eidesstattliche Erklärung zur Abschlussarbeit:

Design and Implementation of High-Speed

Electronics for a Spatial Filter Velocimeter

Ich versichere, die von mir vorgelegte Arbeit selbstständig verfasst zu haben.

Alle Stellen, die wörtlich oder sinngemäÿ aus veröentlichten oder nicht veröf-

fentlichten Arbeiten anderer entnommen sind, habe ich als entnommen kenntlich

gemacht. Sämtliche Quellen und Hilfsmittel, die ich für die Arbeit benutzt habe,

sind angegeben. Die Arbeit hat mit gleichem Inhalt bzw. in wesentlichen Teilen

noch keiner anderen Prüfungsbehörde vorgelegen.

Unterschrift : Ort,Datum :

Contents

Contents ii

Acronyms iii

1 Introduction 1

2 Foundations/Theory 3

2.1 LVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.2 Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.3 Transmission Line . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3.1 S-Parameters . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.3.2 Signal Delay . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.3.3 Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.4 Eye-diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3 Requirements 15

4 System Design 17

4.1 Field-Programmable Gate Array (FPGA) selection . . . . . . . . . 20

4.2 DSP selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.3 Data storage Interface . . . . . . . . . . . . . . . . . . . . . . . . 22

4.4 Camera Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.5 System Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 25

5 Implementation 28

5.1 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.2 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.2.1 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.2.2 FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

i

Contents

5.2.3 DDR3 Memory Interface . . . . . . . . . . . . . . . . . . . 35

5.2.4 Camera Link Base . . . . . . . . . . . . . . . . . . . . . . 36

5.3 PCB Planning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5.4 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

5.4.1 FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

5.4.2 DDR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

5.4.3 Camera Link Base . . . . . . . . . . . . . . . . . . . . . . 46

5.5 Resulting PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

6 Simulation 49

6.1 DDR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

6.2 Sata RX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

6.3 Camera Link base . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

7 Verication 59

7.1 Power-Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

7.2 FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

7.3 Camera Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

7.4 DDR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

7.5 Low-speed interfaces . . . . . . . . . . . . . . . . . . . . . . . . . 64

8 Conclusions 67

List of Figures II

List of Tables III

Bibliography IV

A Appendix XI

A.1 Data-CD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XI

A.2 Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XII

A.3 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XII

ii

Acronyms

BGA Ball Grid Array

CBA Cost Benet Analysis

CONSENS CONceptual design Specication technique for the ENgineering

of complex Systems

DSP Digital Signal Processor

EMC Electromagnetic Compliance

EMI Electromagnetic Interference

FFT Fast Fourier Transform

FPGA Field-Programmable Gate Array

LVDS Low-voltage dierential signaling

McASP Multichannel Audio Serial Port

PCB Printed Circiut Board

PDN Power Distribution Network

PLC Programmable Logic Controller

SFV Spatial Filtering Velocimeter

SPI Serial Peripheral Interface

SSI Synchronous Serial Interface

VADER Velocimeter using ADvanced spatial ltER

iii

1 Introduction

The aim of this thesis is the development of a custom hardware prototype

used for the advancement of the spatial ltering algorithm. The derivation of

the overall system requirements and the system design phase are carried out

according to the CONceptual design Specication technique for the ENgineering

of complex Systems (CONSENS) method, created by the Heinz Nixdorf Institut

in Paderborn [1].

This project is conducted at the Institute of Systems engineering at the

Bochum University of Applied Sciences in cooperation with Smart Mechatron-

ics GmbH. The agreed project scope is attached to the data-cd (Appendix A.1.1).

A typical measuring task in an industrial environment is the determination of

the velocity and length of produced material, such as wire. This task is often

fullled by rotary encoders, or similar contact based instruments. However

some surfaces prohibit the usage of contact based sensors, requiring non contact

measurement [2].

Two concurring techniques for non contact measurement are established: the

Laser-Doppler-Velocimetry (LDV) and the Spatial Frequency Velocimetry (SFV)

[3]. The Institute of Systems engineering focuses on the research of improving

spatial frequency algorithms. The introduction to the spatial ltering algorithm

is only briey described in this thesis, for a detailed explanation refer to the

literature [3, 4, 5, 6].

Figure 1.1 shows the principal working of the spatial lter, showing a single

particle moving perpendicular to an optical grid located in front of a camera.

Light is reected from the surface of the measured object and is projected onto

the optical grid.

1

1 Introduction

The resulting radiated power generates the spatial lter function g(t), shown in

gure 1.1 as a sinusoidal function. With the optical grid properties and the known

cameras frame rate, the spatial lter function can be analysed regarding the

frequency components which correlate to the measured velocity v of the object.

Figure 1.1: Spatial lter signal of a single particle [3]

As the project is carried out according to the v-model, the structure of the thesis is

arranged similarly, describing the overall system requirement, the system design,

the implementation and the verication in chronological order [7].

2

2 Foundations/Theory

This chapter gives a brief introduction into the principles and theoretical foun-

dations utilised for the thesis. The main focus lies on techniques and principles

utilised to describe and analyse systems consisting of high speed digital signaling.

2.1 LVDS

Low-voltage dierential signaling (LVDS) denes a unidirectional data transmis-

sion standard for high speed data transfer. The physical layer is standardised by

ANSI/TIA/EIA-644 as well as by IEEE, without dening the application layers

to ensure usability for multiple purposes [8, 9].

The schematic circuit structure of a typical LVDS interface is shown in gure 2.1.

The driver consists of a current source and two pairs of switches, limiting

the output current per channel to 3.5 mA, resulting in an odd mode signal.

The receiving end is terminated with a resistor of matching impedance to the

transmission line, that produces the dierential voltage signal for the receiver.

The signal currents are limited to the wire pair resulting in a minimised loop

area. This reduces coupling mechanisms and results in an improved noise

immunity compared to single ended signaling.

In addition, the driver current limitation allows for hot plugging and also

prevents spike currents occurring during level transitions, allowing data rates of

up to 3.25 Gbit s−1 per channel [8].

3


A

B

B

A

UDrive

3.5 mA

100 Ω Receiver

Figure 2.1: Schematic circuit structure of LVDS physical layer

Due to the minimised voltage swings, typically 300 mV, low slew rates of less than

1 V ns−1 can be achieved, which is considered as non critical for Electromagnetic

Interference (EMI) [8]. Typical LVDS-receivers tolerate up to ±1 V ground shift,

leading to a common mode range of 0.3 V to 2.3 V [10, 11].

2.2 Decoupling

In the supply of digital systems, current transients occur due to switching logic

components. To minimise resulting voltage ripples, bypass capacitors are placed

next to switching components. To estimate the necessary amount and type of

decoupling, the capacitors impedance has to be modelled as a function of capac-

ity, frequency, package type and mounting style to estimate the resulting ripple

voltages caused by current transients. Therefore an equivalent circuit according

to gure 2.2 is introduced. It consists of the ideal capacity C, the parasitic induc-

tance LESL and the resistance RESR. To account for leakage currents, the parallel

resistance RLEAK is typically modelled, but is ignored for the decoupling analysis,

as its inuence is mainly limited to static behaviour.

4


C LESL RESR

RLEAK

Figure 2.2: Equivalent circuit of a real capacitor

According to the equivalent circuit, the magnitude of the equivalent impedance

can be calculate using equation 2.1.

|Z(ω,RESR, LESL, C)| =

√R2

ESR +

(ωLESL −

1

ωC

)2

(2.1)

To visualise the impact of dierent casing dimensions and therefore package

impedances, two capacitors in dierent casings and with dierent capacitance

are simulated and compared. Firstly a 100 nF capacitor in a 0402 package, with

an inductance of 840 pH and an RESR of 0.2 Ω is simulated. Secondly a 1 µF

capacitor in a 1206 casing, with a parasitic inductance of 1.2 nH and an RESR of

0.3 Ω is analysed. [12]

Both impedances are plotted in gure 2.3, as well as the resulting impedance

of both capacitors in parallel conguration. The behaviour is mainly inuenced

by the change in capacitance, but also the change in inductance inuences the

resulting impedance.

5


10-5 10-4 10-3 10-2 10-1 100

Frequency in GHz

10-1

100

101

102

103Z

in O

hmImpedance Simulation

Simulated Impedance 0402-packageSimulated Impedance 1206-packageSimulated Impedance combined

Figure 2.3: Simulated Impedances of 0402 and 1206 Ceramic Capacitors

The simulation does not include the estimation for the inductances caused by vias,

connecting the capacitors to the actual power plane. To estimate this inductance,

the geometry according to gure 2.4 for two spaced vias of equal diameter needs

to be analysed analysed.

6


z = 0

z = h

x = sx = 0 x = d2

Figure 2.4: Inductance estimation of spaced vias

The magnetic eld B between the vias is approximated by the following equation

as a function of the distance x to the radius d/2 of the via.

B =µ · I2πx

x ≥ d/2

In The dening formula of inductance, the magnetic ux Φ can be substituted

as the surface integral of the magnetic eld B. The surface integral is dened as

the spanned area between the vias. Equation 2.2 yields the formulated geometry-

dependant estimation of the vias.

LVia =Φ

I=

2

I

∫BdA =

2

I

∫ h

0

∫ s− d2

d2

µI

2πxdxdz =

µ

π· h · ln

(2s

d− 1

)(2.2)

With this inductance estimation as well as the parasitic properties taken from

data sheets, the quality of the proposed decoupling array can be estimated [13].

7


2.3 Transmission Line

As signaling speed increases the properties of electrical circuitries can no longer

be accounted for as purely resistive but rather estimated as segments containing

parasitic impedances. As these properties are described in great detail in the

literature such as Heuermann in [14], only a brief introduction is given here.

The electrical properties of a conductor section ∆z can be modelled according

to gure 2.5 by a serial inductance to model the generated magnetic eld , a

capacitor to account for generated electrical elds and an admittance to account

for the isolation resistance.

∆u

u u+ ∆u

i i+ ∆i

∆iR′∆z L′∆z

C ′∆z G′∆z

Figure 2.5: Schematic transmission line characteristics for a conductor section∆z, [14]

Applying Kirchho's laws and rearranging them to equal ∆i and ∆u yields the

following equations:

∆i = −G′∆z · (u+ ∆u)−C ′∆z · d(u+ ∆u)

dtand ∆u = −R′∆z · i−L′∆z · di

dt

As the limit of ∆z approaches 0, the two equations yield a dierential change in

voltage and current:

∂i

∂z= −G′u− C ′∂u

∂tand

∂u

∂z= −R′u− L′∂i

∂t(2.3)

These dierential equations can easily be solved for the case of sinusoidal steady-

state, using the following phasors:

8


U =u√2· ej(ωt+φu) and I =

i√2· ej(ωt+φi) (2.4)

Inserting these phasors into equations 2.3 and applying the rules of derivation

results in:∂I

∂z= −(G′ + jωC ′)U and

∂U

∂z= −(R′ + jωL′)I

Combining both rst order dierential equations into a single second order dif-

ferential equation results in:

∂2U

∂z2− (R′ + jωL′)(G′ + jωC ′)U

=∂2U

∂z2− γ2U

= 0 (2.5)

The propagation constant γ comprises the real part attenuation constant α and

the imaginary part β.

γ :=√

(R′G′ − ω2L′C ′) + jω(R′C ′ + L′G′)) = α + jβ

Solving equation 2.5 a generalised solution consists of the initial conditions U r0

and U v0 with a rst and third quadrant solution of the complex root, that repre-

sent the incident voltage U v and the reected voltage U r as functions of z.

U(z) = U r0 · eγz + U v0 · e−γz = U r + U v (2.6)

To nd an equation for the impedance of a conductor segment, equation 2.3 is

utilise to nd a substitution for I as a function of U , which yields:

I = − 1

R′ + jωL′· ∂U∂z

= −γ

R′ + jωL′U(z) (2.7)

Using Ohm's law, this results in the familiar equation for the impedance of a

conductor segment, equation. 2.8:

Z0 =R′ + jωL′

γ=

√R′ + jωL′

G′ + jωC ′(2.8)

For the pre-layout trace impedance calculation, estimative equations 2.9 and 2.10,

proposed by Johnson in [13] are used.

9


In addition to the estimation by the above formulae, a numerical solver (Saturn

PCB) is used to verify the plausibility of the results.

Z0(Microstrip) =60√

0.475 εR + 0.67ln

(4h

0.67 · (0.8w + t)

)(2.9)

Z0(Stripline) =60

εRln

(4b

0.67π · (0.8w + t)

)(2.10)

The physical dimensions for the formulae 2.9 and 2.10 are depicted in gure 2.6

ws

t

εR

Microstrip

w s

h

Stripline

Figure 2.6: Transmission Line Geometry [15, 16]

2.3.1 S-Parameters

As shown in the calculation of transmission lines, voltages and currents in trans-

mission lines are highly dependant on the location of measurement. For high fre-

quency signals, it is therefore convenient to describe networks in terms of waves

[14]. The incident waves ai are dened as incident voltage Up wave, normalised

over the root of the reference impedance√ZLi, gure 2.7, while the reected wave

bi is the reected voltage Ur normalized to√ZLi.

10


ZL2ZL1 ZL

I2I1

U1 U2

Up

Ur

Ip

Ir

a1 a2

b1 b2

ZL1 ZL2

[S]

Figure 2.7: Transformation of 4-pole network with currents and voltages to 2-portwave network

If the internal impedance of the network diers from the reference impedance,

the denition for ai and bi are given as equation 2.11:

ai =U i + ZLi · Ii2√

Re (ZLi)and bi =

U i − ZLi · Ii2√Re (ZLi)

(2.11)

The relationship of ai and bi can then be written as a linear equation system, as

equation 2.12 depicts for a 2-port network, with the coecient matrix referred to

as the scattering matrix: [b1

b2

]=

[S11 S12

S21 S22

][a1

a2

](2.12)

The matrix coecients can be briey described as:

S11: Input port reection coecient

S12: Reverse transmission coecient

S21: Forward transmission coecient

S22: Output port reection coecient

The parameters S11 and S22 can be described as reection coecients for matched

loads. The parameter S21 denes the forward transmission coecient and the

parameter S12 the reverse transmission coecient. To qualify networks in regard

to their attenuation and reection, distortion return losses RL and insertion losses

IL are often used, calculated as follows, equation 2.13.

RL = 20 log

(1

|Sii|

)and IL = 20 log

(1

|Sij|

)(2.13)

11


Typically conductors are considered good for less than 3 dB attenuation and no

more than −10 dB reection [14].

2.3.2 Signal Delay

To determine the propagation speed of a signal through a transmission line, equa-

tion 2.6 can be used under the assumption that after time ∆t at ∆z the phase of

the signal is the same as at t = 0 and z = 0.

U v(∆z) = U v0 · e−α∆z (2.14)

For a sinusoidal voltage this leads to the following equation:

Uv0 · e−α∆z · cos(ω∆t+ φv − β∆z) = Uv0 · cos(φv) · e−α∆z (2.15)

For the equation to be true, the cosine argument must equal zero, meaning that

ω∆tmust also equal β∆z. Solving for the deviation of distance over time produces

the denition of the propagation speed vph:

vph =∆z

∆t=ω

β(2.16)

For approximated lossless conductors, assuming β ≈ ω ·√L′C ′ , the propagation

speed can be estimated as follows:

vph =ω

β=

ω

ω ·√L′C ′

=1√L′C ′

To match trace length in the implementation, it is ecient to think of propagation

speed as the propagation delay per length. Johnson [13] gives the following delay

estimations for PCB traces as function of the dielectric constant:

TD(Microstrip) = 33.36√

0.475 εR + 0.67ps

cm(2.17)

TD(Stripline) = 33.36√εR

ps

cm(2.18)

12


2.3.3 Skew

As signal speed increases, the timing constraints between data setup time and

sampling time decrease. This increases the impact of timing imperfections, such

as skew induced by driver circuit switching time variations or unbalanced trace

lengths.

To ensure that valid data is present at the receiver during the data sampling

window, g. 2.8, a worst-case jitter estimation based on the given specications

from the receiver data sheet is mandatory.

sample window

Clock

tjitter

tskew

Data

trmsk

Figure 2.8: Example timing diagram, showing jitter and skew

Adding up the available skews, such as the transmitter jitter and the jitter in-

duced by cables, then subtracting these from the receiver sampling time trmsk, an

estimation of remaining skew for the Printed Circiut Board (PCB) traces tskewPCB

can be derived, eq. 2.19:

tskewPCB = trsmk − tjitter − tskewCable (2.19)

Using the propagation delay formulae, the maximum trace length derivation for

a given interface can be calculated.

In addition to the timing imperfections, eects such as crosstalk, impedance dif-

ferences in traces or electromagnetic noise in general inuence the signal quality.

A common tool to measure the overall signal quality is the eye-diagram.

13


2.4 Eye-diagrams

The data eye diagram is a technique to qualify high speed data signals. It

shows multiple important characteristics of the signal so that its quality can be

determined.

It is constructed by laying individual bits of a high speed signal into a single

graph, with signal amplitude as the vertical axis and time as the horizontal axis.

The resulting graph is a statistical representation of the high speed signal. [17]

The characterising elements of the measurement are shown in gure 2.9. The rise

time trise and fall time tfall are dened as the average transition duration from

one logical state to another, measured from 10 % to 90 % level of the slope.

The eye width is dened as the time between two mean crossing from one logical

state to another. The eye height denes the minimal voltage between the two

logical states within the diagram. It determines the eye closure caused by noise

and thereby how well the logic states can be distinguished from another. The

crossing percentage represents the mean height of the level transition and is an

indicator for asymmetry in bit durations. Jitter is dened as the derivation of

the actual timing of transitions to the ideal transition eg. caused by clock skew

or pulse width distortion. It can be random or deterministic depending on the

source of the interference.

trise

Eye height

Eye widthtjitter

Unit interval tUI

Zero level

One level

Amplitude

tfall

Figure 2.9: Typical eye-diagram [17]

14

3 Requirements

According to the CONSENS method, the rst step during the requirements

engineering is the denition of an environment-model. It allows for an overview

of all inuencing environmental elements linked to the system [1].

The specic environment-model for the Velocimeter using ADvanced spatial

ltER (VADER) is shown in gure 3.1. It is evaluated in collaboration with

the all involved project parties to aim for completeness of linked elements.

The requirements document is then derived from the environment-model (see

Appendix A.1.2).

Describing the specic environmental elements, A key element is the surface area

of the measured object. It interacts with the VADER-system via the optics and

the camera.

The length measurement interface and the incremental encoder describe two

industry standard interfaces, commonly used for rotary encoders. As VADER

is intended to replace these in existing processes, the usage of the quadratic

incremental encoder and the Synchronous Serial Interface (SSI) are predetermined

by the customer. Furthermore VADER has to be able to identify process borders,

instigated by material entering the cameras scanned area, to implement the

length measurement. As a result of this, photo electric sensor interfaces are

necessary, as they are used in industrial processes to indicate the start or end of

a process.

The industrial environment necessitated requirements regarding ambient temper-

ature, dust concentration, humidity, power supply quality and Electromagnetic

Compliance (EMC). Specic standards that the VADER system has to comply

with are stated in the requirements document, Appendix A.1.2.

15

3 Requirements

VADER PLC

Videodata

logging

Measured

object

Manufacturing

test

User

Engineer

service

Length

measurement

Photo-electric

sensors

Standards

PC GUI

Temperature, humidity

dust

24V DC

Camera frames

Optical measurement

installation, calibration

Assembly states

Diagnostics, maintenance

Object speed

Process information

Configuration

Specification

Object edgesObject length

Additional

VADERSynchronised measurement

Incremental

encoder

Power

supply

Environment

Figure 3.1: Derived environment-model for the VADER-system

To be able to set the correct ltering values for every application, it is necessary

to store the raw optical data of the process for later analysis. For this purpose a

logging system with the capability of storing raw process data with durations of

up to 20 min is required.

For communication with a host in a given production environment such as a Pro-

grammable Logic Controller (PLC), VADER must be equipped with a universal

eld bus interface, to allow for easy implementation of an interface to a predeter-

mined communication protocol.

The conguration of the system by a service engineer as well as the readout of

parameters and debugging of the software requires a specic communication in-

terface. Furthermore status LEDs visible during the normal operation of VADER

in the process are required, to indicate the state of operation to the user.

16

4 System Design

With the overall system requirements determined, a suiting system architecture

is derived, as shown in Fig. 4.1. The electronics system element consists of the

necessary circuitry to communicate with all interfacing elements and hosts the

hardware purposed for the computing of the spatial lter algorithm. External

connections through the casing are depicted within the diagram as hexagons

on the casing boundary, representing a connector that has to comply with the

environmental requirements.

Casing

Environment

SSI

Interface

Object

Electronics

Power

Supply

SPS

Incremental

Encoder

User

PC

GUI

Service

Engineer

Photo

Sensor

Data

Storage

Camera

Optics

Pattern

Projection

Pilot

Light

Illumination

LEDs

additional

VADER

ANYBUS

Converter

Figure 4.1: Proposed system architecture VADER

Explanation of the system elements:

• Camera: Implementing the spatial lter algorithm with a camera is set by

project specications.

17

4 System Design

• Optics: Optical system mounted to camera, the elaboration of a suitable

solution is not part of this thesis.

• Pattern Projection and Pilot Light: Future extensions to the optical system,

are not part of this thesis.

• Illumination: Light source to illuminate the measured objects structural

features.

• Data Storage: Device to store raw video images as specied in the require-

ments.

• LEDs: External indication for users.

• ANYBUS: Universal eld bus interface to ensure versatility.

• Converter: External voltage converter and lter.

• Casing: Mechanical enclosure housing all system elements and protection

from environmental inuences.

To minimise the utilised PCB area, an external voltage converter for the 24 V

external supply to a 12 V level is chosen, which also handles the EMC ltering.

Furthermore the outsourcing of the converter minimises the design risks of the

hardware development.

As solution for the required universal eld bus interface, the Anybus M40 module

system is chosen, which consists of a standardised PCB connector and oers a

variety of eld bus implementations [18].

External LEDs are added to meet the requirements of externally visible state

indicators for both the user and service-engineer.

The data storage device is housed within the casing of the VADER system, as the

necessity of raw image data extractions only arises during the initial setup of the

sensor in a given environment.

Due to the requirements regarding the maximum camera data rate and the

implementation of the spatial ltering algorithm, the usage of a FPGA alongside

a dedicated Digital Signal Processor (DSP) is the chosen system architecture [3].

18

4 System Design

The spatial lter function, consisting of large vector multiplication and addi-

tion is optimally performed by programmable logic, whereas the Fast Fourier

Transform (FFT) and auto correlation functions are best performed by a DSP.

The selection of suitable devices for these tasks is described in the course of this

chapter.

Figure 4.2 shows the intended data ow of the resulting Spatial Filtering Ve-

locimeter (SFV)-sensor, in which the raw images are transferred from the camera

to the FPGA via a high speed interface. The interface also allows for congu-

rations to be sent from the FPGA to the camera, which is further described in

section 4.4.

The FPGA applies the spatial lter function to the raw images, transfers camera

parameters controlled by the DSP, such as the exposure time to the camera and

handles the communication to external interfaces.

The resulting spatial lter function is transferred to the DSP for the spatial anal-

ysis, yielding the velocity and length measurement results.

These results are transferred back from the DSP to the FPGA, which in turn broad-

casts it via the specic external interfaces. The external interfaces also contain

the data storage interface, allowing for raw image data storage.

A detailed description of the implemented algorithm is given by Schneider in [19].

Configuration Spatial filter

function

FPGA DSPCamera

External Interfaces

Image aquisition

Spatial filter Camera

parametrization External interfaces

Parametrization Data logging

Spatial filter-model Camera

parametrization Frequency analysis

Speed

Length

Camera settings

Image data

Configuration

data

Speed

Length

Camera settings

Figure 4.2: Block diagram of information ow of the spatial lter velocimeter [3]

19

4 System Design

4.1 FPGA selection

To decide upon the best suiting FPGA for the VADER project, multiple model

architectures are taken into account. As the project team already has experience

with the equipment and software oered by Xilinx, other vendors are not taken

into further consideration. To illustrate the selection process, two competing

device series are compared:

• The Xilinx Spartan 6 series is widely used and oers a verity of available

development-boards. It includes dedicated serial transceivers supporting

data rates of up to 3.2 Gbit s−1 and can be used with DDR2 and DDR3

RAM [20].

• The Xilinx 7 family comprises of the Artix-7 series, which are purposed

for low power applications with high logic throughput. They consist of

6.2 Gbit s−1 GTP-transceivers, supporting the SATA 6 Gbit s−1 standard.

Furthermore the DDR3 and DDR3L standard are supported as RAM in-

terfaces. [21, 22]

Table 4.1 depicts a Cost Benet Analysis (CBA), comparing two specic devices

from each series, the Artix-7 XC7A35T and the Spartan 6 XC6SLX45T, meeting

the requirement for the estimated number of IO pins. The key characteristics

are the available DSP slices needed to perform multiplications, the transceivers

maximum data rate purposed for the raw image storage as well as the experience

of the project team with the given family.

Table 4.1: CBA to elicit suiting FPGA series for the VADER project

XC7A35T XC6SLX45TCriterion % val. % val. %GTP-Transceiver 17.3% 1.8 15.6% 1.0 8.7%Logic Cells 13.3% 1.2 8.0% 1.2 8.0%DSP Slices 20.0% 1.3 13.0% 1.0 10.0%Embedded RAM 18.7% 1.0 9.3% 1.3 12.1%Price 11.3% 1.3 7.4% 1.1 6.2%Experience 19.3% 1.5 14.5% 1.2 11.6%Result 67.8% 58.6%

20

4 System Design

As the CBA in table 4.1 shows, the Artix-7 series FPGA is the best suited archi-

tecture, as the availability of the hight speed transceivers as well as the larger

amount of DSP slices are benecial for the VADER project.

4.2 DSP selection

To evaluate the best match for the data processing, information on the latest

DSPs from TI is gathered. In the domain of high performance processing, TI

oers the C66x Core, which runs on a maximum of 1.25 GHz clock frequency

and is declared as high performance xed and oating point DSP [23]. For the

computation tasks the VADER project possesses, a single core suces to perform

the DSP tasks, as the spatial ltering algorithm has little potential for parallel

executions [3].

TI uses its KeyStone Multicore Architecture to integrate multiple cores into

one package, leading to two main groups of processors, the TMS320x series

and the 66AK2x series. The TMS320x series compose of up to 8 C66x cores

with dedicated coprocessors for specic tasks, such as Ethernet. The 66AK2x

combines a C66x core with an Arm Cortex-A15 Microprocessor, allowing to

address a wide variety of peripherals.

Two specic devices are compared, that full the DSP requirements for the

VADER project, the TMS320C6655 DSP and the 66AK2G12 System-on-Chip.

The TMS320C6655 consists of one C66x core, a selection of peripherals such as

SPI, Ethernet and PCIe, and characterises as power ecient solution for DSP

tasks.

The 66AK2Gx processor consists of a C66x core alongside an A15 ARM core,

oering a variety of peripherals, including 30 IO pins, USB 3.0 support, 3 Serial

Peripheral Interface (SPI) interfaces as well as a dedicated Ethernet coprocessor.

Table 4.2 shows the CBA used to decide upon the most suiting DSP. As some

of the system elements are connected directly to the DSP, the availability of pe-

ripherals and GPIO pins is an important factor for the decision. Furthermore

the availability, the programming complexity and the availability of development

boards inuence the decision.

21

4 System Design

Table 4.2: CBA comparing the TMS320C6655 to the 66AK2G12 [23, 24]

66AK2G12 TMS320C6655Criterion % val. % val. %Peripherals 15.4% 1.6 12.3% 0.9 6.9%Availability 9.3% 1.0 4.6% 1.3 6.0%GPIOs 13.2% 1.5 9.9% 1.0 6.6%Programming complexity 11.4% 0.9 5.1% 1.3 7.4%SIMULINK support 17.1% 1.0 8.6% 1.0 8.6%Price 10.7% 1.0 5.4% 1.2 6.4%Maximal clock rate 10.4% 1.0 5.2% 1.0 5.2%Development board 12.5% 1.5 9.4% 1.2 7.5%Result 60.5% 54.7%

As table 4.2 shows, the 66AK2Gx Processor is the better suited option, as it

comprises more specic peripherals, supports a larger number of dedicated GPIO

pins and oers a better support of development boards, even though it is not yet

as broadly available as the TMS320C6655.

4.3 Data storage Interface

To select the interface between the data storage and the VADER system, the

following requirements have to be taken into account:

1. Minimum raw-image capture duration: 20 min

2. Maximum data rate of camera interface

3. Data storage system removable

The maximum data rate of the camera interface fData derives from the require-

ments of a maximum camera frame rate fFramerate of 200 kHz, and the number of

pixels per frame NPixel of 1024 using 12 bit per pixel, equation 4.1.

fData = NBitsPerPixel ·NPixel · fFramerate = 410 MB s−1 (4.1)

Taking into consideration the storage duration of 20 min and the camera data

rate, a minimum storage capacity of 492 GB is needed.

22

4 System Design

Table 4.3 lists a selection of commonly used high speed interfaces, that support

a removable data storage system. It lists the maximum supported write speed as

well as the main advantages and disadvantages.

Table 4.3: Data storage interface benchmark

Interfacemax.

Storage

max.

write speedPro Con

SDXC 2 TB 25 MB s−1 easy assemblydoesn't meetspeed requirements

USB 2.0 1 TB 60 MB s−1 common interfacepower and dataover same connector

USB 3.0 (Gen1) 1 TB 500 MB s−1 high writing speedpower and dataover same connector

SATA 3 Gbit s−1 30 TB 300 MB s−1 FPGA IP supporthigher powerrequirements

SATA 6 Gbit s−1 30 TB 600 MB s−1 FPGA IP supporthigher powerrequirements

The SDXC interface consists a serial interface, composed of four data lines and

a designated clock. The voltage levels of 3.3 V allow easy implementation in

embedded systems however limit the achievable data rate [25].

The USB 2.0 standard consists of a 200 mV dierential link, via which the bidi-

rectional communication between master and slave is handled. This leads to an

achievable data rate of 60 MB s−1, not meeting the writing speed requirements.

The USB 3.0 interface includes 4 additional LVDS pairs in addition to the stan-

dard dierential link, allowing for a maximum data transfer speed of 900 MB s−1

[26].

Both SATA interfaces consist of two data lanes each appointed to transmitting

or receiving. It is supported by IP-Cores within the Vivado IDE, and the SATA

6 Gbit s−1 is backward compatible to the 3 Gbit s−1 standard. The key advantage

of the SATA interface towards the USB 3.0 standard is the separation of power

supply and data transfer into two separate cables, making the integration of con-

nectors less critical.

Therefore the SATA interface is chosen as interface between VADER and the data

storage device.

23

4 System Design

4.4 Camera Interface

For the decision upon a suitable camera interface, high speed line scan cameras

from dierent vendors are evaluated. The most common interfaces for these

are Camera Link and Gigabit Ethernet (GigE Vision), however cameras with

Thunder Wire and USB 3.1 interfaces are also available [27, 28, 29].

Table 4.4 lists the proposed interfaces with the maximum achievable data rate,

the number of cables as well as the proposed cable lengths and the connector type.

Table 4.4: Camera Interface Benchmark [30, 29]

Digital System

Interface

Data Transfer

Rate

Cable

LengthConnector # Cables

GigEVision

125 MB s−1 100 m RJ45 1

Camera LinkBase

255 MB s−1 10 m 26Pin 1

Camera LinkMedium

510 MB s−1 10 m 26Pin 2

Camera LinkFull

680 MB s−1 10 m 26Pin 2

USB 3.1 900 MB s−1 3 m USB type 3 1

The necessary transfer rate of 410 MB s−1 limits the selection to Camera Link

Full, Camera Link Medium and USB 3.1.

As USB 3.1 is a recent standard, not many cameras are supported at the time of

the project [27, 28], therefore the decision to use Camera Link Medium as link

between FPGA and camera is made.

The Camera Link standard cable consists of four data LVDS pairs, a clock

pair for the data lines, four control pairs for a general camera control interface

as well as two pairs reserved for an asynchronous serial communication link.

This cable can be used for the Camera Link base connection [30]. The second

cable, used additionally for the Camera Link medium standard, contains two

additional data ports, each consisting of one clock and four data LVDS pairs. Fig-

ure 4.3 shows the cable conguration according to the Camera Link standard [30].

24

4 System Design

Figure 4.3: Camera Link cable conguration according to standard [30]

The Camera Link standard [30] recommends the usage of TIs DS90CR287 Chan-

nel Link receivers, which converts the four LVDS channels into 28 parallel data

signals of TTL levels. Even though the chosen Artix-7 FPGA consist of pin pairs

supporting the LVDS standard, it is decided to use the dedicated channel link

chips, so that the FPGA is not directly connected to a connector.

4.5 System Architecture

With the selected solutions for the critical system elements in place, the detailed

system architecture can be produced.

25

4 System Design

In order to minimise the design risk, a split system architecture is proposed,

which separates the electronics system element at the link between the DSP and

the FPGA. As the DSP is intended primarily to full the computational eort

and the FPGA is supposed to handle external interfaces, the decision is made to

develop the FPGA related hardware in the course of this project and use one

of the already available DSP development boards. This ensures a functioning

prototype as a result of this thesis, and a platform to optimise the spatial lter

algorithms.

The EVMK2GX development, shown in Fig. 4.4, is chosen for the prototype, as it

comprises suitable peripherals for communication such as multiple SPI, Ethernet

and a Multichannel Audio Serial Port (McASP) interfaces. To ensure that all nec-

essary communication between DSP and FPGA, specied in Appendix A.1.2 can

be handled by the selected bus, the McASP interface is chosen, as the EVMK2GX

board has enough channels connected to an external header to achieve the esti-

mated necessary data rate of 10 MB s−1. [31]

Figure 4.4: Chosen 66AK2Gx DSP development board from TI

The chosen development board determines the rst system element for the FPGA

board, as the McASP interface is connected to an external pin header, which is

used as a physical link between development board and the custom hardware.

26

4 System Design

The data storage system is also designed onto the custom electronics, with an

additional RAM storage device connected to the FPGA to act as data buer for

the storage interface.

The external interfaces for photo sensors, incremental encoders, ANYBUS and

SSI are also part of the custom electronics.

Taking these considerations into account, a system architecture, referred to as

the FPGA board, according to gure 4.5 is derived.

PCB

Mounting

Holes

Sata SSDSata

Power

Supply

SSD

Casing

CameraLVDS

Receiver

LVDS

Receiver

FPGA

DSP Board

Flash

JTAG

Camera Link

Medium

Temperature

Sensor

Boot

Select

Clocks

Watchdog

Voltage

Converter

McASP

Connector

ANYBUS

PC

GUIUSBFTDI

LEDs

RAM

LVDS

Transceiver

Camera Link

Base

Inkremental-

Encoder

Encoder

Circuit

SSI InterfaceSSI

Circuit

Photo SensorsIsolating

Circuit

Figure 4.5: Proposed system architecture of the FPGA board

As the proposed system architecture is agreed upon with the customer, the de-

tailed elaboration and analysis of all system elements is performed in the imple-

mentation phase.

27

5 Implementation

Documenting the implementation phase is sequenced according to the determined

milestones of the project, rstly describing the power supply design, followed by

the derivation of the schematic elements and then the implementation of the ac-

tual hardware. Each milestone is subject to a review, which is held in cooperation

with Smart Mechatronics.

The iterative work-ow for the PCB design begins with the pre-route calculations,

the routing of the layout, simulation of the high speed circuits and optimisation

of the layout, as described in chapter 6. The nal step is the verication of the

physical hardware, see chapter 7 [7].

5.1 Power Supply

The rst step of the implementation phase is the evaluation of the power sup-

ply scheme starting with the analysis of all used components regarding their

required supply voltage and corresponding supply current. Table 5.1 shows the

accumulated currents for the main supply levels, the detailed calculation and the

complete list of consumers is attached in Appendix A.1.6.

In addition to the worst-case currents the absolute minimum and maximum volt-

ages for each level are recorded, to estimate the output voltage tolerances.

The generated power supply requirements document is attached in Ap-

pendix A.1.3.

28

5 Implementation

Table 5.1: Current estimation for power supplies, detailed in Appendix A.1.6

Supply Rail Output Current Output Power

12.0 V 2.53 A 30.39 W5.0 V 1.45 A 7.27 W3.3 V 1.63 A 5.37 W1.8 V 1.02 A 1.84 W1.35 V 0.80 A 1.08 W1.0 V 2.10 A 2.10 W

With the voltage margins and the estimated current consumption of the power

rails, specic power supply solutions can be derived. Using the TI-WEBENCH

as well as LTspice to conrm the correct dynamic behaviour, specic solutions

according to gure 5.1 are chosen [32]. Each converter is subject to dimensioning

calculation, worst-case estimation and thermal analysis, which are documented

in Appendix A.1.6.

The LTC3636 dual-synchronous buck converter is used to provide the 1.0 V core

voltage for the FPGA as well as the 3.3 V peripheral level, with a maximum out-

put current of 6 A per channel. The start-up ramps can be adjusted separately

for each channel and two power-good-outputs are available [33].

The voltages for the remaining auxiliary levels are provided by the three

TPS82140 converters, which contain an integrated inductor, minimising the ex-

ternal component count. The maximum output current of 2 A is also sucient

for the selected voltage rails [34].

For the supply of the GTP-transceiver of the Artix-7 device two TPS7A7001 low-

drop linear regulators are used. These allow for a calculated maximum voltage

ripple per rail of 2 mV, thereby staying within the required voltage ripple of

10 mV [35, 36], Appendix A.1.3.

29

5 Implementation

FTDI SSD

Increment

SSI

Photo Sensors

RAM

FPGAFPGA FPGAFPGA FPGA FPGA

Clocks

Camera Link

LTC3636

12V 4A

1V35 2A

1V0 530mA 1V2 300mA

5V0 1A4

FPGA

TPS7A7001

1V0 6A

TPS7A7001 TPS7A7001

3V3 6A

LTC3636TPS82140 TPS82140

Board Supply

Photo Sensors

1V8 1A4

TPS82140

Figure 5.1: Implemented power-supply scheme

The voltage start-up sequence is primarily dened by the recommendation for the

Artix-7 devices, described in [35], however the maximum slew rate of all voltage

levels is veried for the remaining components on the PCB. Additionally Xilinx

species the allowable maximum voltage between distinct rails during the start-

up as 2.625 V to prevent increased current demand of the FPGA.

To comply with these requirements, there are two commonly used techniques to

implement the start-up sequence, briey described in the following: [37]

• Coincident: All voltages are ramped with constant slew rate, keeping volt-

age dierence as small as possible, however increasing inrush currents as all

decoupling capacitors get charged simultaneously.

• Sequential: voltage levels enabled after one another, leading to a reduc-

tion of supplying currents, however increasing dierential voltages between

dierent levels.

To balance the resulting inrush currents and dierential voltages between rails,

a combination of both start-up methods is chosen. The 1.0 V core rail and the

auxiliary levels are started up coincidentally, while still reaching their target

voltage in the recommended sequence as given by [35].

30

5 Implementation

The 1.35 V supply is ramped with a reduced slew rate, to comply with the

start-up recommendation of the chosen DDR3L chips data sheet specication

[38]. Using this method, the maximum dierential voltage of 2.625 V is never

exceeded. As the recommended supply sequence for the GTP-transceiver is

VCCINT, MGTAVCC, MGTAVTT, given by [35], the linear regulators are

enabled in a sequential manner.

To ensure a deterministic start-up behaviour of the GTP-transceivers, the linear

regulators for the MGTAVCC and MGTAVTT rails are enabled when both the

1.8 V and 5 V rail reach their specied operating voltage, by using the power-

good-outputs to enable the linear regulators, gure 5.2.

The resulting start-up sequence of all implemented voltage levels and the RESET

signal enabling the FPGA are depicted in gure 5.2.

t/ ms0 1 3 5 7 9 11 13 15

12V

1V0 VCCINT

1V8 VCCAUX

3V3 VCCO

5V0

1V35

1V0-GTP MGTAVCC

1V2-GTP MGTAVTT

RESET

Figure 5.2: Power supply start-up timing diagram

31

5 Implementation

5.2 Schematic

The schematic is created according to the system architecture, gure 4.5. Thereby

all system elements are designed into hierarchical schematic sheets, allowing

for traceability of all elements throughout the project. The description of the

schematic derivation is done representatively for the key elements Camera Link

base interface, power supply, DDR3 memory interface as well as the FPGA con-

guration and decoupling.

The completed schematic, cleared for implementation after the reviews is attached

in Appendix A.3. The dimensioning and worst-case calculations are attached in

Appendix A.1.7.

5.2.1 Power supply

The conception of the power supply schematic elements is documented for the

LTC3636 dual buck converter, as the described steps transfer to all used convert-

ers. The implemented schematic section showing the LTC3636 and the connected

external components is depicted in gure 5.3.

Figure 5.3: Schematic of the LTC3636 dual buck converter

The supply and output nets are connected via net ties, to allow the system to be

isolated during the verication phase for testing.

32

5 Implementation

Furthermore capacitors are placed close to the net ties connected to the outputs

of the power supply elements, to set up a low pass lter if the output ripple

requirements should not be met during the verication phase.

The power-good-outputs are connected to the reset circuit which generates the

master-reset signal for the FPGA taking all voltage levels into account.

The worst-case calculation and component selection conducted for each power

supply element is attached in Appendix A.1.6, as well as the simulation le used

to verify the component behaviour for load transitions.

5.2.2 FPGA

The design of the FPGA schematic is a large part of the schematics milestone.

The st step is the conguration of the start-up boot circuitry. The FPGA can

be congured to boot from a number of interfaces, however the selected boot

options are JTAG and quad SPI. The JTAG is primarily intended to be used

during debugging and testing, while the SPI interface is to be used during normal

operation. Jumper J12 is connected to the FPGAs MODE2 pin and determines

which interface is selected as boot option. The INIT_B-pin is connected to the

reset signal which is generated by the power good circuit. In case a reset request

has to be sent from the DSP, the RESET signal is also connected to one of the

McASP signal pins via an optional resistor, to allow for the aforementioned

option.

For debugging an LED is connected to the DONE_0 pin, which indicates the

completed boot sequence. The resulting schematic section regarding the boot

circuitry is shown in gure 5.4.

33

5 Implementation

Figure 5.4: Schematic of the FPGA conguration circuit

To provide the system clock for the FPGA during debugging, an external 100 MHz

oscillator is connected to bank 34 of the FPGA. The clock source for the main

application can be chosen from either the camera pixel clock or the external

oscillator.

The planning of the IO connection is done using a Vivado 18.0 pin-planning

project, to minimise the risk of errors while connecting all schematic elements to

the FPGA. To decide which elements are connected to which banks, the data

ow within the FPGA as well as the planned PCB layout have to be taken into

account, to minimise the length of the connecting traces. The documents created

for this purpose are attached in Appendix A.1.15.

To optimise the eort of routing the low speed interface signal traces connected

to the FPGA, the pin-swapping feature the Altium Designer oers is used,

grouping all pins of a given bank into a pin-swapping group, allowing for

optimised trace routing without trace crossings.

34

5 Implementation

The initial conguration of the local decoupling network for the dierent power

levels is implemented according to the Artix-7 PCB design guide [39].

It includes recommendations for specic capacitor values and packages for each

of the used banks, and is intended to be used as a starting point. Figure 5.5

shows the placed decoupling capacitors for the core voltage VCCINT and the

PLL-power supply VCCAUX. The simulation of the decoupling network as

verication of adequate decoupling is described in the layout section 5.4.

Figure 5.5: Schematic section decoupling capacitors FPGA VCCINT and VC-CAUX

5.2.3 DDR3 Memory Interface

The selected DDR3 memory chip is the MT41K128M16JT-125 manufactured

by Micron, supporting the DDR3LP standard, which reduces the logic voltage

levels from 1.5 V to 1.35 V for better EMC [38]. It is supported by the memory

interface generator (MIG-7) included in the Vivado 18 design suite and is used

in the Digilent Arty development board [40].

The device is interfaced with a data bus width of 16 bit, and is addressed by a

14 bit wide address bus, allowing for a total 2 Gbit of volatile storage [38].

The MIG-7 generator is used to provide a IO constraint le, which is used to

connect the required signals for the interface to the corresponding FPGA pins.

The resulting schematic section regarding the interface connection of the memory

chip is shown in gure 5.6

35

5 Implementation

Figure 5.6: Schematic section of the DDR3 memory device

5.2.4 Camera Link Base

The Camera Link receiver chosen is the TI DS90CR288, which supports TTL

clock rates of up to 85 MHz [11]. The data input consists of one LVDS pair clock

input and four pairs of LVDS data inputs, which are terminated according to

[8] with 100 Ω resistors. The LVDS nets are assigned into dierential pairs and

combined into the net-list LVDS_Base to allow for layout rules to be applied to

all included signals.

To ensure local decoupling, ceramic capacitors are provided for each power pin.

Furthermore a 4.7 µF tantalum bulk capacitor is added, as is recommended by

the data sheet [11].

The resulting schematic section regarding the Camera Link base receiver is

shown in gure 5.7.

36

5 Implementation

Figure 5.7: Schematic section of the Camera Link base receiver circuit

The implementation of the general control interface is done by using the TI

DS90LV047, which is a four channel LVDS driver. It supports 3.3 V power supply

and achieves data rates of up to 400 Mbit s−1 [41].

The asynchronous serial communication is handled by the DS90LV019 chip from

TI, that consists of one LVDS line driver and one receiver. It supports data

rates of 100 Mbit s−1 and complies with the Camera Link standard regarding

the serial communication, which requires minimum data rates of 76.8 Mbit s−1

for the serial interface. [42]

5.3 PCB Planning

The aim of this section is the design of a suitable layer stackup for the PCB. This

requires dierent factors to be taken into account, such as the required signal

impedances, power supply layers and necessary via types.

Firstly, all high speed interfaces are evaluated regarding their requirements to-

wards delay matching and trace impedances. Table 5.2 lists these interfaces and

their physical layer specications.

37

5 Implementation

Table 5.2: Physical layer specication of high speed interfaces [8, 43, 44, 45]

Signal

Type

Trace

Length

Pair

Matching

Group

Matching

Trace

Impedance

Dierential

Impedance

SATA ≤ 150 mm 2 ps 75 ps 55 Ω± 15% 90 Ω± 15%LVDS ≤ 150 mm 2 ps 60 ps 55 Ω± 15% 100 Ω± 15%USB ≤ 150 mm 25 ps - 50 Ω± 15% 90 Ω± 15%DDR3Address

25-75 mm - 25 ps 50 Ω± 10%

DDR3Data

25-75 mm - 15 ps 50 Ω± 10%

The pair and group matching parameters are determined by the skew margin

proposed for the PCB. The trace impedances are determined to ensure min-

imised reection losses induced by impedance mismatching, as specied in the

corresponding data sheet.

The overall trace length recommendations are derived from the best practice

guidelines [8, 46, 47].

Another aspect inuencing the assessment of the layer stackup is the number of

required signal layers.

Xilinx provides an estimative equation to determine the recommended minimal

number of signal layers NSignalLayers for the BGA fanout, equation 5.1. The

number of routing channels NRoutingChannels therein denes the total number of

clearances between pads on the circumference of the selected BGA package.

The routes per channel NRoutesperChannel determine how many traces can be tted

between two neighbouring pads [46].

For the chosen 484-pad BGA package and the available number of signal pins

NSignalPins being 220, at least three signal layers should be provided.

NSignalLayers =NSignalPins

NRoutingChannels ·NRoutesperChannel=

220

84 · 1≤ 3 (5.1)

According to the estimation given in equation 5.1, the minimum number of

signal layers is three.

38

5 Implementation

Before specic layer stackups can be compared and evaluated, criteria for the

rating of characteristics have to be dened. A conclusive system to rate and

compare dierent stackups is presented by Ott in [48]:

1. Signal layers have an adjacent to plane.

2. Signal layers are close to an adjacent plane.

3. Power and ground planes are closely coupled together.

4. High-speed signals are routed on buried layers located between planes.

5. Multiple-ground planes are used, as they lower the impedance of the board

and reduce common-mode radiation.

6. Critical signals routed on more than one layer are conned to two layers

adjacent to the same plane.

With the amount of dierent power levels to supply the FPGA, a split plane is

dedicated to the purpose of power supply adjacent to a solid ground plane.

To ensure the availability of buried signal layers purposed for high speed signals,

signal layers between ground planes or between ground and power planes are

required. To achieve a symmetrical stackup, with low speed routing layers on top

and bottom, a minimum of four four signal layers is required. As a compromise

between total number of layers and sucient ground planes, an eight-layer

stackup is proposed.

Ott in [48] provides the rating of two eight-layer stackups, gure 5.8. The high

speed signal layers shown in gure 5.8a are not close to planes on either side.

Also these signal layers are not located between planes, as they are situated

beside a split power plane on one side.

The inner signal layers in gure 5.8b however are located between two solid

planes, thereby complying with ve out of six criteria.

39

5 Implementation

(a) An acceptable eight-layer board stackup

with four signal layers and two split

power planes. This conguration satis-

es four of the six objectives.

(b) An excellent eight-layer PCB stackup

with good signal integrity and EMC per-

formance. This conguration satises

ve of the six objectives.

Figure 5.8: Comparison of two dierent eight-layer stackups [48]

Taking these considerations into account, the stackup for the VADER project is

chosen according to gure 5.9.

The inner core is bordered by a solid ground plane and the split power plane,

while the outer cores contain the strip line layer and additional ground layers.

The sandwiched cores are spaced by three layers of 1080 prepreg material. The

outermost layers, intended for low frequency signals are also spaced by prepreg

material, completing the eight layer stackup.

40

5 Implementation

Figure 5.9: Layer stackup exported from the Altium Designer project

The given stackup fulls four out of the criterion for all layers. However the

rst internal signal layer Sig2 intended for high speed signals complies with the

demand for two adjacent planes, meeting criterion six for same plane ground

reference, fullling ve out of six criteria.

To minimise EMI eects the high speed signals are preferentially routed on Sig2.

To minimise parasitic eects of via stubs, staggered micro vias are inserted into

the design, inherent to the physical dimensions of the dielectrics and the given

1:1 size ratio, gure 5.9 [49]. With the dimensions of the layers determined

and the producibility veried by the PCB manufacturer [50], the necessary trace

geometries can be calculated.

The estimations provided in chapter 2 are used to determine the required widths.

The results are then compared to the output of Saturn PCB. The resulting trace

geometries for the four signal layers and the high speed interface signals are listed

in table 5.3.

41

5 Implementation

Table 5.3: Trace dimensions for critical interfaces per layer

SATA LVDS USB DDR3

55 Ω 90 Ω 55 Ω 100 Ω 50 Ω 90 Ω 50 ΩWidth Spacing Width Spacing Width Spacing Width

Sig1 220 µm 143 µm 220 µm 240 µm 270 µm 270 µm 270 µmSig2 100 µm 120 µm 100 µm 230 µm 150 µm 220 µm 150 µmSig3 100 µm 120 µm 100 µm 230 µm 150 µm 220 µm 150 µmSig4 220 µm 143 µm 220 µm 240 µm 270 µm 270 µm 270 µm

5.4 Layout

The description of the layout phase is done for the key system elements, the

decoupling and fanout of the FPGA, the DDR3 memory interface as well as the

Camera Link base circuitry.

As the development of the layout is an iterative process being subject to common

sense optimisation and simulation based verication, the layout sections dis-

cussed in the following are the results of the implementation after aforementioned

optimisations. The documentation of the simulation-based optimisations are

described in chapter 6.

5.4.1 FPGA

The layout implementation of the FPGA section is done in the following iterative

sequence [39]:

1. PWR-plane polygons

2. Capacitor placement

3. Power Distribution Network (PDN) analysis

4. GTP transceiver circuits

5. DDR3 interface

6. Camera Link interface

7. Fanout low speed signals

42

5 Implementation

Firstly, the PWR plane polygons are created, making sure the vias connecting

the FPGA pads are embedded within the according plane. The resulting polygon

arrangement under the FPGA is shown in gure 5.10. The vias connecting the

supply and GND pads of the BGA package are laid out to be 1 mm spaced to

adjacent power pins to ensure that the 100 nF 0402 capacitors can be placed

directly beneath the package with minimal parasitic inductance. All further

capacitors are placed in the perimeter of the FPGA, also to minimise the

resulting parasitic inductance.

1V35 3V3

1V0

1V2-GTP

Figure 5.10: Implemented PWR-plane, showing net polygons as well as placeddecoupling capacitors

To verify the eectiveness of the decoupling, a PDN analysis is conducted [51].

To estimate the amount of AC-voltage ripple on a given power rail, a LTspice

simulation is used (Appendix A.1.10). It consists of the capacitor modelling

according to section 2.2 with a calculated via inductance according to section 2

of 0.6 nH for the implemented stackup. Furthermore, the capacitance of the

given power supply polygons is taken into account according to equation 5.2, as

a function of the polygons area Apolygon, the core thickness dcore and the dielectric

constant εR of the core material.

43

5 Implementation

Cpolygon = ε0εRApolygon

dcore(5.2)

To estimate the target impedance, Bogatin in [52] gives equation 5.3, which di-

vides the maximum ripple voltage for the supply rail VACripple by the estimated

maximum ripple current set at 50 % of the maximum current consumption.

Ztarget(f) ≤ VACripple0.5 · Imax

(5.3)

The power consumption for the 1V0 rail is estimated with the power supply

estimation tool provided by Xilinx (Appendix A.1.6) with a fabric usage of

70 %. The resulting maximum supply current for the core-voltage Imax is thereby

given as 2 A. Taking the allowable AC ripple of 50 mV for the core voltage

into account, the target impedance of the 1V0 net is calculated to be 50mΩ

(Appendix A.1.3).

To nd the maximum frequency at which the board level decoupling is eective, as

opposed to the die-decoupling, Bogatin [52] gives an estimation based on the ratio

of lead inductance of the FPGA supply to target impedance. With a calculated

lead inductance for the FPGA of 0.6 nH and target impedance of 50 mΩ the

maximum board level decoupling frequency of 100 MHz is adopted [52].

The resulting impedance plot for the 1V0 net as a function of frequency as a

result of the simulation is shown in gure 5.11. The target impedance of 50 mΩ

up to a frequency of 100 MHz is depicted as dashed line.

The impedance curve for frequencies below 1 kHz is not further analysed, as

the switch mode power supplies can compensate voltage ripples within these

frequencies.

As the target impedance is met for the specied frequency range up to 100 MHz,

the amount of decoupling for the 1V0 power rail is considered to be sucient.

44

5 Implementation

10-5 10-4 10-3 10-2 10-1 100

Frequency in GHz

10-3

10-2

10-1

100Z

in O

hmPDN Impedance Simulation

Target ImpedanceSimulated Impedance 1V0

Figure 5.11: Simulated impedance of the 1V0 PDN

5.4.2 DDR3

The next step in the layout process is the routing of the DDR3 traces.

As recommended in [53] the data group and the address and control group are

routed on dierent stripline layers, with the data lanes traced on the Sig2 layer,

as they posses the highest bandwidth signals and the shielding provided by two

adjacent GND planes is benecial. They are grouped into data bytes with the

dierential data strobe pairs in the middle. The crosstalk eects as a function of

spacing between adjacent signal traces is analysed in section 6.

Address lines, control signals and the dierential clock signal are routed on layer

Sig3. They are matched to ±1 mm according to the skew margin, table 5.2.

As Sig3 is located between a GND plane and the split power-plane, the signals

are only traced under the 1.35 V supply polygon, gure 5.12, to ensure noise

suppression.

45

5 Implementation

The placement of the decoupling capacitors for the memory chip is done according

to the recommendations given by the manufacturer, [43]. Figure 5.12 shows

the implemented layout of the DDR3 signal traces on layers Sig2 and Sig3 with

stashed polygons for better visibility of the traces.

Figure 5.12: Implemented data traces (green) and address traces (purple) betweenDDR3 memory chip U1 and FPGA U2

5.4.3 Camera Link Base

The Camera Link Base circuitry consists mainly of the receiver chip, connector,

the control and serial interface chips, with the critical traces being the LVDS

pairs.

The termination resistors, required by the LVDS standard are placed as close as

possible to the receivers to minimise the unterminated stub lengths. To meet the

length matching requirements, table 5.2, the dierential pair length matching

rules are set to ±2.54 mm (Appendix A.1.7), calculated with the propagation

delay estimation for layer Sig1.

46

5 Implementation

To minimise propagation dierences within the channels caused by partial traces

on inner layers, the staggered micro vias in the traces connecting Sig2 to the top

layer Sig1 are placed as close as possible to the connector, gure 5.13.

As described in the schematic section, decoupling capacitors are placed at every

power pin. To minimise the loop area, they are placed on the back side of the

PCB. The 3.3 V are provided through the power plane. Figure 5.13 shows the

resulting layout section of the Camera Link base circuitry, showing traces on

layers and polygons Sig1 and Sig2 with stashed polygons.

Figure 5.13: PCB section of the Camera Link base group

5.5 Resulting PCB

With the critical high speed interfaces in place, the low speed signal traces are

routed. Firstly the remaining signals are fanned out from the FPGA and then

connected to the system elements. The resulting PCB layout is shown in g-

ure 5.14. To display all placed signal traces, all polygons are stashed. Also for

traceability of the system elements, the components of a given system element

are enclosed by silkscreen rectangles.

47

5 Implementation

PAC101 PAC102

COC1

PAC201 PAC202

COC2

PAC301

PAC302

COC3

PAC401

PAC402

COC4

PAC501

PAC502

COC5

PAC601

PAC602

COC6

PAC701

PAC702

COC7

PAC801

PAC802

COC8

PAC901

PAC902

COC9

PAC1001 PAC1002

COC10

PAC1101 PAC1102

COC11

PAC1201 PAC1202

COC12

PAC1301 PAC1302

COC13

PAC1401 PAC1402

COC14

PAC1501

PAC1502

COC15

PAC1601

PAC1602

COC16

PAC1701 PAC1702

COC17

PAC1801 PAC1802

COC18 PAC1901 PAC1902

COC19

PAC2001

PAC2002

COC20

PAC2101

PAC2102

COC21

PAC2201 PAC2202 COC22

PAC2301

PAC2302 COC23



PAC2601

PAC2602 COC26



PAC2901

PAC2902 COC29


PAC3101

PAC3102

COC31

PAC3201

PAC3202 COC32

PAC3301

PAC3302 COC33

PAC3401

PAC3402 COC34

PAC3502

PAC3501 COC35 PAC3602 PAC3601

COC36 PAC3702 PAC3701

COC37

PAC3802 PAC3801

COC38

PAC3901

PAC3902 COC39

PAC4001

PAC4002 COC40

PAC4101

PAC4102

COC41

PAC4201

PAC4202

COC42

PAC4301

PAC4302 COC43

PAC4401

PAC4402

COC44

PAC4501

PAC4502 COC45

PAC4601

PAC4602

COC46

PAC4701 PAC4702

COC47

PAC4801 PAC4802

COC48

PAC4901

PAC4902

COC49

PAC5001 PAC5002

COC50

PAC5101 PAC5102

COC51

PAC5201

PAC5202

COC52

PAC5301

PAC5302

COC53

PAC5401 PAC5402

COC54

PAC5501 PAC5502

COC55

PAC5601

PAC5602

COC56

PAC5702

PAC5701

COC57

PAC5802 PAC5801

COC58

PAC5902 PAC5901

COC59

PAC6002 PAC6001

COC60

PAC6102 PAC6101

COC61

PAC6202 PAC6201

COC62

PAC6302 PAC6301

COC63

PAC6402

PAC6401

COC64

PAC6502 PAC6501

COC65

PAC6601

PAC6602

COC66

PAC6701

PAC6702

COC67

PAC6802 PAC6801

COC68

PAC6902 PAC6901

COC69

PAC7001 PAC7002

COC70

PAC7101 PAC7102

COC71

PAC7202 PAC7201

COC72

PAC7301

PAC7302

COC73 PAC7401

PAC7402

COC74 PAC7501

PAC7502

COC75

PAC7601

PAC7602 COC76

PAC7701

PAC7702

COC77

PAC7802

PAC7801 COC78

PAC7902

PAC7901 COC79

PAC8002

PAC8001

COC80

PAC8101

PAC8102

COC81

PAC8201 PAC8202

COC82

PAC8301 PAC8302

COC83

PAC8402 PAC8401

COC84

PAC8502 PAC8501

COC85

PAC8601 PAC8602

COC86

PAC8701

PAC8702 COC87

PAC8801

PAC8802

COC88

PAC8901

PAC8902 COC89

PAC9002 PAC9001

COC90

PAC9101

PAC9102 COC91

PAC9201

PAC9202

COC92

PAC9301

PAC9302

COC93

PAC9401

PAC9402

COC94

PAC9501 PAC9502

COC95

PAC9601

PAC9602

COC96

PAC9701

PAC9702

COC97

PAC9801

PAC9802

COC98


PAC10001

PAC10002

COC100 PAC10102 PAC10101

COC101

PAC10201 PAC10202

COC102

PAC10302 PAC10301

COC103

PAC10402 PAC10401

COC104

PAC10502 PAC10501

COC105

PAC10602 PAC10601

COC106

PAC10701 PAC10702

COC107

PAC10801 PAC10802

COC108

PAC10901 PAC10902

COC109

PAC11001 PAC11002

COC110

PAC11101 PAC11102

COC111

PAC11201 PAC11202

COC112

PAC11302 PAC11301 COC113

PAC11402 PAC11401 COC114

PAC11501 PAC11502

COC115

PAC11601 PAC11602

COC116

PAC11701 PAC11702

COC117

PAC11801 PAC11802

COC118

PAC11901 PAC11902

COC119

PAC12001 PAC12002

COC120

PAC12102 PAC12101

COC121

PAC12202 PAC12201

COC122

PAC12302 PAC12301

COC123

PAC12402

PAC12401

COC124 PAC12501

PAC12502

COC125 PAC12601

PAC12602

COC126

PAC12701

PAC12702

COC127

PAC12801

PAC12802

COC128

PAC12901

PAC12902

COC129

PAC13001

PAC13002

COC130

PAC13102 PAC13101

COC131

PAC13202 PAC13201

COC132

PAC13302 PAC13301

COC133

PAC13402 PAC13401

COC134

PAC13502 PAC13501

COC135

PAC13602

PAC13601

COC136

PAC13701

PAC13702

COC137

PAC13801

PAC13802

COC138

PAC13901

PAC13902

COC139

PAC14001

PAC14002

COC140

PAC14101

PAC14102

COC141

PAC14201

PAC14202

COC142 PAC14302

PAC14301

COC143

PAC14402

PAC14401

COC144

PAC14501

PAC14502

COC145

PAC14601

PAC14602

COC146

PAC14701

PAC14702

COC147

PAC14801

PAC14802

COC148

PAC14901

PAC14902

COC149

PAC15001

PAC15002

COC150 PAC15102 PAC15101

COC151

PAC15202 PAC15201

COC152

PAC15302 PAC15301

COC153

PAC15402 PAC15401

COC154

PAC15502 PAC15501

COC155

PAC15602 PAC15601 COC156

PAC15701

PAC15702

COC157

PAC15801

PAC15802

COC158

PAC15901

PAC15902

COC159

PAC16001

PAC16002

COC160

PAC16101

PAC16102

COC161

PAC16201

PAC16202

COC162 PAC16302

PAC16301

COC163

PAC16401 PAC16402

COC164

PAC16501 PAC16502

COC165

PAC16601 PAC16602

COC166

PAC16702 PAC16701

COC167

PAC16802 PAC16801 COC168

PAC16901 PAC16902

COC169

PAC17001 PAC17002

COC170

PAC17101 PAC17102

COC171

PAC17201 PAC17202

COC172

PAC17301 PAC17302

COC173

PAC17402 PAC17401

COC174

PAC17502 PAC17501

COC175

PAC17601 PAC17602

COC176

PAC17701 PAC17702

COC177

PAC17801 PAC17802

COC178

PAC17901 PAC17902

COC179

PAC18001 PAC18002

COC180

PAC18101 PAC18102

COC181

PAC18201 PAC18202

COC182 PAC18302 PAC18301 COC183

PAC18402 PAC18401

COC184

PAC18502 PAC18501

COC185

PAC18602 PAC18601

COC186

PAC18702 PAC18701

COC187

PAC18802 PAC18801

COC188

PAC18902

PAC18901

COC189

PAC19002 PAC19001

COC190

PAC19101 PAC19102 COC191

PAC19202 PAC19201 COC192

PAC19301

PAC19302

COC193

PAC19402 PAC19401

COC194

PAC19502 PAC19501

COC195

PAC19602 PAC19601

COC196

PAC19702 PAC19701

COC197

PAC19801

PAC19802

COC198

PAC19901 PAC19902

COC199

PAC20001 PAC20002

COC200

PAC20101 PAC20102

COC201

PAC20201 PAC20202

COC202

PAC20302 PAC20301

COC203

PAC20402 PAC20401

COC204

PAC20502 PAC20501

COC205

PAC20602 PAC20601

COC206

PAC20702

PAC20701 COC207 PAC20801

PAC20802

COC208 PAC20901

PAC20902

COC209

PAC21001 PAC21002

COC210

PAC21101 PAC21102 COC211

PAC21202

PAC21201 COC212

PAC21301 PAC21302 COC213 PAC21401 PAC21402 COC214

PAC21502 PAC21501

COC215

PAC21602 PAC21601

COC216

PAC21702 PAC21701

COC217

PAC21802 PAC21801

COC218 PAC21902 PAC21901

COC219 PAC22002 PAC22001

COC220 PAC22102 PAC22101

COC221

PAC22202 PAC22201

COC222

PAC22302 PAC22301

COC223 PAC22402 PAC22401

COC224 PAC22502 PAC22501

COC225 PAC22602 PAC22601

COC226

PAC22702 PAC22701

COC227

PAC22802 PAC22801

COC228

PAC22902 PAC22901

COC229

PAC23001

PAC23002

COC230

PAC23101

PAC23102

COC231

PAC23201

PAC23202

COC232

PAC23302

PAC23301

COC233 PAC23402

PAC23401

COC234

PAC23501 PAC23502 COC235

PAC23601 PAC23602 COC236

PAC23702 PAC23701

COC237

PAC23802 PAC23801

COC238

PAC23902 PAC23901

COC239

PAD103

PAD102 PAD101

COD1

PAD203

PAD202 PAD201

COD2

PAD302 PAD301 COD3

PAD402 PAD401 COD4

PAD502 PAD501 COD5

PAD602 PAD601 COD6

PAD703 PAD702

PAD701

COD7

PAD803 PAD802

PAD801 COD8

PAD903 PAD902

PAD901

COD9

PAD1003 PAD1002

PAD1001

COD10

PAD1103 PAD1102

PAD1101

COD11

PAD1203

PAD1202 PAD1201

COD12

PAD1302 PAD1301 COD13

PAD1401 PAD1402 PAD1403 PAD1404

PAD1405 PAD1406

COD14

PAD1501 PAD1502 PAD1503 PAD1504

PAD1505 PAD1506

COD15

PAD1602

PAD1601

COD16

PAD1701 PAD1703 PAD1702

PAD1704 PAD1705 PAD1706

COD17

PAD1902 PAD1901 COD19

CODIV1

PADIV200 CODIV2

PADIV300 CODIV3

PADIV400 CODIV4

PADIV500 CODIV5

PADIV600 CODIV6 PADIV700 CODIV7

PADIV800 CODIV8

PADIV900 CODIV9

PADIV1000 CODIV10

PADIV1100 CODIV11

CODIV12

PAF101 PAF102 COF1

PAIC1028 PAIC1027 PAIC1026

PAIC1025

PAIC1024 PAIC1023

PAIC1022 PAIC1021 PAIC1020 PAIC1019 PAIC1018 PAIC1017 PAIC1016 PAIC1015 PAIC1014 PAIC1013 PAIC1012

PAIC1011

PAIC1010 PAIC109

PAIC108 PAIC107 PAIC106 PAIC105 PAIC104 PAIC103 PAIC102 PAIC101


PAIC1031 PAIC1030

PAIC1029

COIC1

PAIC209 PAIC205 PAIC206 PAIC207 PAIC208

PAIC204 PAIC203 PAIC202 PAIC201 COIC2 PAIC309

PAIC305 PAIC306 PAIC307 PAIC308

PAIC304 PAIC303 PAIC302 PAIC301 COIC3 PAIC409


PAIC404 PAIC403 PAIC402 PAIC401 COIC4

PAIC5029 PAIC5030 PAIC5031 PAIC5032 PAIC5033 PAIC5034 PAIC5035 PAIC5036 PAIC5037 PAIC5038 PAIC5039 PAIC5040 PAIC5041 PAIC5042 PAIC5043


PAIC5048 PAIC5049 PAIC5050 PAIC5051 PAIC5052 PAIC5053 PAIC5054 PAIC5055 PAIC5056


PAIC5014

PAIC5013


PAIC5018 PAIC5017


PAIC509

PAIC5020 PAIC5019

PAIC5016 PAIC5015

COIC5

PAIC6011

PAIC6012

PAIC6015

PAIC6016 PAIC601

PAIC602

PAIC603

PAIC604

PAIC605

PAIC608

PAIC606

PAIC607 PAIC6010

PAIC609

PAIC6014

PAIC6013

COIC6

PAIC701

PAIC702

PAIC703

PAIC704

PAIC705

PAIC706

PAIC707

PAIC7014

PAIC7013

PAIC7010

PAIC709

PAIC708

PAIC7012

PAIC7011

COIC7

PAIC8019 PAIC8020

PAIC8015 PAIC8016

PAIC8011 PAIC8012

PAIC809 PAIC8010



PAIC8038 PAIC8039 PAIC8040 PAIC8041 PAIC8042 PAIC8043 PAIC8044 PAIC8045 PAIC8046 PAIC8047 PAIC8048 PAIC8049 PAIC8050 PAIC8051 PAIC8052 PAIC8053 PAIC8054 PAIC8055 PAIC8056



PAIC8014 PAIC8013


PAIC8018 PAIC8017

COIC8


PAIC905

PAIC906 PAIC907 PAIC908 PAIC909 PAIC9010 PAIC9011



PAIC9021

COIC9


PAIC1005

PAIC1006 PAIC1007 PAIC1008 PAIC1009 PAIC10010 PAIC10011



PAIC10021

COIC10

PAIC1107 PAIC1108

PAIC11065 PAIC11064

PAIC11063




PAIC11053


PAIC11049

PAIC11048 PAIC11047 PAIC11046 PAIC11045 PAIC11044 PAIC11043 PAIC11042 PAIC11041 PAIC11040 PAIC11039 PAIC11038 PAIC11037 PAIC11036 PAIC11035 PAIC11034 PAIC11033 PAIC11032

PAIC11031


PAIC11027




PAIC11017

PAIC11016 PAIC11015 PAIC11014 PAIC11013 PAIC11012 PAIC11011 PAIC11010 PAIC1109 PAIC1106 PAIC1105 PAIC1104 PAIC1103 PAIC1102 PAIC1101

COIC11



COIC12


PAIC1303 PAIC1302 PAIC1301 COIC13

PAIC1401 PAIC1402 PAIC1403 PAIC1404 PAIC1405 PAIC1406 PAIC1407 PAIC1408 PAIC1409 PAIC14010

PAIC14020 PAIC14019 PAIC14018 PAIC14017 PAIC14016 PAIC14015 PAIC14014 PAIC14013 PAIC14012 PAIC14011

COIC14

PAIC1505


COIC15



COIC16 PAIC1705 PAIC1706 PAIC1707 PAIC1708


COIC17

PAIC1804

PAIC1802

PAIC1803

PAIC1801

COIC18



COIC19 PAIC2005 PAIC2006 PAIC2007 PAIC2008


COIC20



COIC21



COIC22



PAIC2309

COIC23


PAIC2508 PAIC2505 PAIC2507 PAIC2506 COIC25

PAJ1027

PAJ1028

PAJ101 PAJ102

PAJ103 PAJ104

PAJ105 PAJ106

PAJ107

PAJ109 PAJ1010

PAJ1011 PAJ1012

PAJ1013

PAJ1014 PAJ1015

PAJ1016 PAJ1017

PAJ1018 PAJ1019

PAJ1020

PAJ1022 PAJ1023

PAJ1024 PAJ1025

PAJ1026

PAJ108 PAJ1021

COJ1

PAJ2073 PAJ2074

PAJ2075 PAJ2076

PAJ2065 PAJ2066

PAJ2067 PAJ2068

PAJ2069 PAJ2070

PAJ2071 PAJ2072

PAJ2057 PAJ2058 PAJ2059 PAJ2060

PAJ2061 PAJ2062

PAJ2063 PAJ2064

PAJ2049 PAJ2050

PAJ2051 PAJ2052

PAJ2053 PAJ2054

PAJ2055 PAJ2056

PAJ2041 PAJ2042

PAJ2043 PAJ2044

PAJ2045 PAJ2046

PAJ2047 PAJ2048

PAJ2033 PAJ2034

PAJ2035 PAJ2036

PAJ2037 PAJ2038

PAJ2039 PAJ2040

PAJ2025 PAJ2026

PAJ2027 PAJ2028

PAJ2029 PAJ2030

PAJ2031 PAJ2032

PAJ2017 PAJ2018

PAJ2019 PAJ2020

PAJ2021 PAJ2022

PAJ2023 PAJ2024

PAJ209 PAJ2010

PAJ2011 PAJ2012

PAJ2013 PAJ2014

PAJ2015 PAJ2016

PAJ208 PAJ207

PAJ206 PAJ205

PAJ204 PAJ203

PAJ202 PAJ201

PAJ2079 PAJ2080

PAJ2090 PAJ2089

PAJ2088 PAJ2087

PAJ2086 PAJ2085

PAJ2084

PAJ2091 PAJ2092

PAJ2093 PAJ2094

PAJ2095 PAJ2096

PAJ20100 PAJ2099

PAJ2098 PAJ2097

PAJ2077

PAJ2082 PAJ2081

PAJ2083

PAJ2078

COJ2 PAJ3027

PAJ3028

PAJ301 PAJ302

PAJ303 PAJ304

PAJ305 PAJ306

PAJ307 PAJ308

PAJ309 PAJ3010

PAJ3011

PAJ3013

PAJ3014 PAJ3015

PAJ3016 PAJ3017

PAJ3018 PAJ3019

PAJ3020 PAJ3021

PAJ3022 PAJ3023

PAJ3024

PAJ3026 PAJ3012 PAJ3025

COJ3

PAJ405 PAJ404 PAJ401 PAJ402 PAJ403

PAJ400

COJ4 PAJ5026

PAJ5025

PAJ5024

PAJ5023

PAJ5022

PAJ5021

PAJ5020

PAJ5019

PAJ5018

PAJ5017

PAJ5016

PAJ5015

PAJ5014

PAJ5013

PAJ5012

PAJ5011

PAJ5010

PAJ509

PAJ508

PAJ507

PAJ506

PAJ505

PAJ504

PAJ503

PAJ502

PAJ501

COJ5

PAJ601

PAJ602

COJ6

PAJ701

PAJ702

PAJ703

PAJ704

PAJ705

PAJ706 COJ7

PAJ801

PAJ802

COJ8

PAJ905 PAJ904 PAJ902 PAJ901 PAJ903 PAJ906

COJ9

PAJ1008 PAJ1007 PAJ1006 PAJ1003 PAJ1001 PAJ1002 PAJ1004 PAJ1005

COJ10

PAJ1102 PAJ1101

COJ11

PAJ1201 PAJ1202

PAJ1203 PAJ1204

PAJ1205 PAJ1206

COJ12

PAJ1307

PAJ1304

PAJ1301

PAJ1308

PAJ1309

PAJ1306 PAJ1305

PAJ1303 PAJ1302

COJ13

PAJ1407

PAJ1404

PAJ1401

PAJ1408

PAJ1409

PAJ1406 PAJ1405

PAJ1403 PAJ1402

COJ14

PAJ1503 PAJ1501 PAJ1502 PAJ1504

COJ15

PAJ1601 PAJ1602 PAJ1603 PAJ1604 PAJ1605 PAJ1606

COJ16

PAJ1703

PAJ1702

PAJ1701

COJ17

PAJ1802 PAJ1801

COJ18

PAL101 PAL102

COL1

PAL201 PAL202

COL2

PAL301

PAL302

COL3

PAL401

PAL402

COL4

PAL501

PAL502

COL5

PAL701 PAL702

COL7

PAL801 PAL802

COL8

PAL901 PAL902

COL9

PAMH101 COMH1

PAMH201 COMH2

PAMH301 COMH3

PAMH401 COMH4

PAMH501 COMH5

CON? CON?1

PANT101

PANT102

CONT1

PANT201 PANT202

CONT2

PANT301 PANT302

CONT3

PANT401 PANT402 CONT4

PANT501

PANT502 CONT5


PANT701

PANT702 CONT7


PANT901

PANT902 CONT9

PANT1001

PANT1002

CONT10

PANT1101

PANT1102

CONT11

PANT1201

PANT1202 CONT12


PAR101

PAR102

COR1

PAR201

PAR202

COR2

PAR301

PAR302

COR3

PAR401 PAR402 COR4

PAR501 PAR502 COR5

PAR601

PAR602

COR6

PAR701

PAR702

COR7

PAR801

PAR802

COR8

PAR901

PAR902

COR9

PAR1001

PAR1002

COR10

PAR1101

PAR1102

COR11

PAR1202

PAR1201

COR12

PAR1301 PAR1302 COR13

PAR1401 PAR1402 COR14 PAR1501 PAR1502 COR15

PAR1602

PAR1601

COR16



PAR2002

PAR2001

COR20

PAR2102

PAR2101

COR21

PAR2202

PAR2201

COR22


PAR2402

PAR2401

COR24

PAR2502

PAR2501

COR25

PAR2602 PAR2601

COR26

PAR2702

PAR2701

COR27

PAR2802 PAR2801

COR28 PAR2901 PAR2902

COR29

PAR3002 PAR3001

COR30



PAR3302 PAR3301

COR33

PAR3402

PAR3401 COR34

PAR3502

PAR3501

COR35

PAR3602 PAR3601 COR36 PAR3702 PAR3701

COR37

PAR3801 PAR3802

COR38

PAR3901

PAR3902

COR39

PAR4001 PAR4002

COR40

PAR4101 PAR4102

COR41

PAR4201 PAR4202

COR42

PAR4302 PAR4301

COR43

PAR4402 PAR4401

COR44

PAR4502 PAR4501

COR45

PAR4602 PAR4601

COR46

PAR4702 PAR4701

COR47

PAR4802 PAR4801

COR48


PAR5001 PAR5002

COR50

PAR5101 PAR5102

COR51

PAR5201

PAR5202

COR52

PAR5301 PAR5302

COR53

PAR5401

PAR5402

COR54


PAR5601 PAR5602

COR56

PAR5701 PAR5702

COR57

PAR5801 PAR5802

COR58

PAR5901 PAR5902

COR59

PAR6001

PAR6002

COR60

PAR6101 PAR6102

COR61

PAR6201 PAR6202

COR62

PAR6301

PAR6302

COR63

PAR6401

PAR6402

COR64

PAR6501 PAR6502

COR65

PAR6601

PAR6602

COR66

PAR6701

PAR6702

COR67 PAR6801

PAR6802

COR68

PAR6901

PAR6902

COR69

PAR7001

PAR7002

COR70

PAR7101

PAR7102

COR71

PAR7201

PAR7202

COR72

PAR7301

PAR7302

COR73

PAR7401

PAR7402

COR74

PAR7501

PAR7502

COR75

PAR7601

PAR7602

COR76

PAR7701

PAR7702

COR77

PAR7801

PAR7802 COR78

PAR7901

PAR7902

COR79 PAR8001

PAR8002

COR80


PAR8201

PAR8202

COR82 PAR8301

PAR8302 COR83

PAR8401

PAR8402

COR84 PAR8501

PAR8502

COR85 PAR8601

PAR8602 COR86 PAR8701


PAR8802 COR88

PAR8902

PAR8901

COR89

PAR9002

PAR9001

COR90

PAR9101 PAR9102

COR91

PAR9201 PAR9202

COR92

PAR9302

PAR9301

COR93



PAR9601 PAR9602

COR96

PAR9701 PAR9702

COR97

PAR9801



PAR10002 COR100 PAR10101

PAR10102 COR101 PAR10201 PAR10202 COR102

PAR10301

PAR10302 COR103 PAR10401

PAR10402 COR104 PAR10501

PAR10502 COR105

PAR10601

PAR10602

COR106 PAR10701

PAR10702

COR107

PAR10802

PAR10801

COR108 PAR10902

PAR10901

COR109 PAR11001

PAR11002

COR110

PAR11101 PAR11102

COR111

PAR11201

PAR11202

COR112

PAR11301

PAR11302

COR113 PAR11401

PAR11402

COR114

PAR11502

PAR11501

COR115

PAR11602

PAR11601

COR116 PAR11701

PAR11702

COR117

PAR11801 PAR11802

COR118 PAR11901

PAR11902

COR119

PAR12001

PAR12002

COR120

PAR12101

PAR12102

COR121

PAR12201

PAR12202

COR122

PAR12301 PAR12302

COR123

PAR12401

PAR12402

COR124

PAR12501

PAR12502

COR125

PAR12601

PAR12602

COR126

PAR12701

PAR12702

COR127 PAR12801

PAR12802

COR128

PAR12901

PAR12902

COR129

PAR13001

PAR13002

COR130

PAR13101

PAR13102

COR131

PAR13201

PAR13202

COR132

PAR13301

PAR13302

COR133

PAR13401

PAR13402

COR134

PAR13501

PAR13502

COR135

PAR13601

PAR13602

COR136

PAR13701 PAR13702 COR137

PAR13801 PAR13802

COR138

PAR13902 PAR13901 COR139

PAR14001 PAR14002

COR140

PAR14101 PAR14102

COR141 PAR14201 PAR14202

COR142 PAR14301 PAR14302

COR143

PAR14401 PAR14402

COR144 PAR14501 PAR14502

COR145

PAR14601

PAR14602

COR146

PAR14701 PAR14702

COR147

PAR14801 PAR14802

COR148

PAR14901

PAR14902

COR149

PAR15001

PAR15002

COR150

PAR15101

PAR15102

COR151

PAR15201

PAR15202

COR152

PAR15301

PAR15302

COR153

PAR15401 PAR15402

COR154

PAR15501 PAR15502 COR155

PAR15601 PAR15602

COR156

PAR15701 PAR15702 COR157

PAR15801 PAR15802

COR158

PAR15901 PAR15902

COR159

PAR16001 PAR16002 COR160

PAR16101 PAR16102

COR161 PAR16201 PAR16202

COR162 PAR16301 PAR16302

COR163

PAR16402

PAR16401

COR164

PAR16502

PAR16501

COR165

PAR16601 PAR16602 COR166

PAR16701 PAR16702 COR167

PAR16801 PAR16802 COR168





PAR17701 PAR17702 COR177

PAR17801 PAR17802 COR178

PAR17901 PAR17902 COR179

PAR18001 PAR18002 COR180









PAR19701 PAR19702 COR197

PAR19801 PAR19802 COR198


PAR20101 PAR20102 COR201


PAT101

PAT102 PAT103

COT1

PAT201

PAT202 PAT203 COT2

PAT301

PAT302 PAT303 COT3

PAT401

PAT402 PAT403

COT4

PAT503

PAT502 PAT501

COT5

PAT601 PAT603

PAT602 COT6

PATP100

COTP1

PATP200 COTP2

PATP300

COTP3

PATP400

COTP4

PATP500

COTP5

PATP600

COTP6

PATP700 COTP7 PATP800

COTP8

PATP900

COTP9 PATP1000

COTP10 PATP1100

COTP11

PATP1200

COTP12

PATP1300

COTP13

PATP1400

COTP14 PATP1500

COTP15

PATP1600

COTP16

PATP1700

COTP17

PATP1800

COTP18 PATP1900

COTP19

PATP2000

COTP20

PATP2100

COTP21

PATP2200

COTP22

PATP2300 COTP23

PATP2400 COTP24 PATP2500 COTP25

PATP2600 COTP26 PATP2700 COTP27

PATP2800

COTP28

PATP2900

COTP29

PATP3000

COTP30

PATP3100 COTP31

PATP3200

COTP32

PATP3300

COTP33

PATP3400 COTP34

PATP3500

COTP35

PATP3600

COTP36

PATP3700 COTP37

PATP3800

COTP38

PAU10N3

PAU10T8

PAU10K7

PAU10J7

PAU10A1 PAU10A2 PAU10A3 PAU10A7 PAU10A8 PAU10A9

PAU10B1 PAU10B2 PAU10B3 PAU10B7 PAU10B8 PAU10B9

PAU10C1 PAU10C2 PAU10C3 PAU10C7 PAU10C8 PAU10C9

PAU10D1 PAU10D2 PAU10D3 PAU10D7 PAU10D8 PAU10D9

PAU10E1 PAU10E2 PAU10E3 PAU10E7 PAU10E8 PAU10E9

PAU10F1 PAU10F2 PAU10F3 PAU10F7 PAU10F8 PAU10F9

PAU10G1 PAU10G2 PAU10G3 PAU10G7 PAU10G8 PAU10G9

PAU10H1 PAU10H2 PAU10H3 PAU10H7 PAU10H8 PAU10H9

PAU10J1 PAU10J2 PAU10J3 PAU10J8 PAU10J9

PAU10K1 PAU10K2 PAU10K3 PAU10K8 PAU10K9

PAU10L1 PAU10L2 PAU10L3 PAU10L7 PAU10L8 PAU10L9

PAU10M1 PAU10M2 PAU10M3 PAU10M7 PAU10M8 PAU10M9

PAU10N1 PAU10N2 PAU10N7 PAU10N8 PAU10N9

PAU10P1 PAU10P2 PAU10P3 PAU10P7 PAU10P8 PAU10P9

PAU10R1 PAU10R2 PAU10R3 PAU10R7 PAU10R8 PAU10R9

PAU10T1 PAU10T2 PAU10T3 PAU10T7 PAU10T9

COU1

PAU20T3

PAU20R3

PAU20B18

PAU20A14

PAU20AB22 PAU20AB21 PAU20AB20 PAU20AB19 PAU20AB18 PAU20AB17 PAU20AB16 PAU20AB15 PAU20AB14 PAU20AB13 PAU20AB12 PAU20AB11 PAU20AB10 PAU20AB9 PAU20AB8 PAU20AB7 PAU20AB6 PAU20AB5 PAU20AB4 PAU20AB3 PAU20AB2 PAU20AB1

PAU20AA22 PAU20AA21 PAU20AA20 PAU20AA19 PAU20AA18 PAU20AA17 PAU20AA16 PAU20AA15 PAU20AA14 PAU20AA13 PAU20AA12 PAU20AA11 PAU20AA10 PAU20AA9 PAU20AA8 PAU20AA7 PAU20AA6 PAU20AA5 PAU20AA4 PAU20AA3 PAU20AA2 PAU20AA1

PAU20Y22 PAU20Y21 PAU20Y20 PAU20Y19 PAU20Y18 PAU20Y17 PAU20Y16 PAU20Y15 PAU20Y14 PAU20Y13 PAU20Y12 PAU20Y11 PAU20Y10 PAU20Y9 PAU20Y8 PAU20Y7 PAU20Y6 PAU20Y5 PAU20Y4 PAU20Y3 PAU20Y2 PAU20Y1

PAU20W22 PAU20W21 PAU20W20 PAU20W19 PAU20W18 PAU20W17 PAU20W16 PAU20W15 PAU20W14 PAU20W13 PAU20W12 PAU20W11 PAU20W10 PAU20W9 PAU20W8 PAU20W7 PAU20W6 PAU20W5 PAU20W4 PAU20W3 PAU20W2 PAU20W1

PAU20V22 PAU20V21 PAU20V20 PAU20V19 PAU20V18 PAU20V17 PAU20V16 PAU20V15 PAU20V14 PAU20V13 PAU20V12 PAU20V11 PAU20V10 PAU20V9 PAU20V8 PAU20V7 PAU20V6 PAU20V5 PAU20V4 PAU20V3 PAU20V2 PAU20V1

PAU20U22 PAU20U21 PAU20U20 PAU20U19 PAU20U18 PAU20U17 PAU20U16 PAU20U15 PAU20U14 PAU20U13 PAU20U12 PAU20U11 PAU20U10 PAU20U9 PAU20U8 PAU20U7 PAU20U6 PAU20U5 PAU20U4 PAU20U3 PAU20U2 PAU20U1

PAU20T22 PAU20T21 PAU20T20 PAU20T19 PAU20T18 PAU20T17 PAU20T16 PAU20T15 PAU20T14 PAU20T13 PAU20T12 PAU20T11 PAU20T10 PAU20T9 PAU20T8 PAU20T7 PAU20T6 PAU20T5 PAU20T4 PAU20T2 PAU20T1

PAU20R22 PAU20R21 PAU20R20 PAU20R19 PAU20R18 PAU20R17 PAU20R16 PAU20R15 PAU20R14 PAU20R13 PAU20R12 PAU20R11 PAU20R10 PAU20R9 PAU20R8 PAU20R7 PAU20R6 PAU20R5 PAU20R4 PAU20R2 PAU20R1

PAU20P22 PAU20P21 PAU20P20 PAU20P19 PAU20P18 PAU20P17 PAU20P16 PAU20P15 PAU20P14 PAU20P13 PAU20P12 PAU20P11 PAU20P10 PAU20P9 PAU20P8 PAU20P7 PAU20P6 PAU20P5 PAU20P4 PAU20P3 PAU20P2 PAU20P1

PAU20N22 PAU20N21 PAU20N20 PAU20N19 PAU20N18 PAU20N17 PAU20N16 PAU20N15 PAU20N14 PAU20N13 PAU20N12 PAU20N11 PAU20N10 PAU20N9 PAU20N8 PAU20N7 PAU20N6 PAU20N5 PAU20N4 PAU20N3 PAU20N2 PAU20N1

PAU20M22 PAU20M21 PAU20M20 PAU20M19 PAU20M18 PAU20M17 PAU20M16 PAU20M15 PAU20M14 PAU20M13 PAU20M12 PAU20M11 PAU20M10 PAU20M9 PAU20M8 PAU20M7 PAU20M6 PAU20M5 PAU20M4 PAU20M3 PAU20M2 PAU20M1

PAU20L22 PAU20L21 PAU20L20 PAU20L19 PAU20L18 PAU20L17 PAU20L16 PAU20L15 PAU20L14 PAU20L13 PAU20L12 PAU20L11 PAU20L10 PAU20L9 PAU20L8 PAU20L7 PAU20L6 PAU20L5 PAU20L4 PAU20L3 PAU20L2 PAU20L1

PAU20K22 PAU20K21 PAU20K20 PAU20K19 PAU20K18 PAU20K17 PAU20K16 PAU20K15 PAU20K14 PAU20K13 PAU20K12 PAU20K11 PAU20K10 PAU20K9 PAU20K8 PAU20K7 PAU20K6 PAU20K5 PAU20K4 PAU20K3 PAU20K2 PAU20K1

PAU20J22 PAU20J21 PAU20J20 PAU20J19 PAU20J18 PAU20J17 PAU20J16 PAU20J15 PAU20J14 PAU20J13 PAU20J12 PAU20J11 PAU20J10 PAU20J9 PAU20J8 PAU20J7 PAU20J6 PAU20J5 PAU20J4 PAU20J3 PAU20J2 PAU20J1

PAU20H22 PAU20H21 PAU20H20 PAU20H19 PAU20H18 PAU20H17 PAU20H16 PAU20H15 PAU20H14 PAU20H13 PAU20H12 PAU20H11 PAU20H10 PAU20H9 PAU20H8 PAU20H7 PAU20H6 PAU20H5 PAU20H4 PAU20H3 PAU20H2 PAU20H1

PAU20G22 PAU20G21 PAU20G20 PAU20G19 PAU20G18 PAU20G17 PAU20G16 PAU20G15 PAU20G14 PAU20G13 PAU20G12 PAU20G11 PAU20G10 PAU20G9 PAU20G8 PAU20G7 PAU20G6 PAU20G5 PAU20G4 PAU20G3 PAU20G2 PAU20G1

PAU20F22 PAU20F21 PAU20F20 PAU20F19 PAU20F18 PAU20F17 PAU20F16 PAU20F15 PAU20F14 PAU20F13 PAU20F12 PAU20F11 PAU20F10 PAU20F9 PAU20F8 PAU20F7 PAU20F6 PAU20F5 PAU20F4 PAU20F3 PAU20F2 PAU20F1

PAU20E22 PAU20E21 PAU20E20 PAU20E19 PAU20E18 PAU20E17 PAU20E16 PAU20E15 PAU20E14 PAU20E13 PAU20E12 PAU20E11 PAU20E10 PAU20E9 PAU20E8 PAU20E7 PAU20E6 PAU20E5 PAU20E4 PAU20E3 PAU20E2 PAU20E1

PAU20D22 PAU20D20 PAU20D19 PAU20D18 PAU20D17 PAU20D16 PAU20D15 PAU20D14 PAU20D13 PAU20D12 PAU20D11 PAU20D10 PAU20D9 PAU20D8 PAU20D7 PAU20D6 PAU20D5 PAU20D4 PAU20D3 PAU20D2 PAU20D1

PAU20C22 PAU20C21 PAU20C20 PAU20C19 PAU20C18 PAU20C17 PAU20C16 PAU20C15 PAU20C14 PAU20C13 PAU20C12 PAU20C11 PAU20C10 PAU20C9 PAU20C8 PAU20C7 PAU20C6 PAU20C5 PAU20C4 PAU20C3 PAU20C2 PAU20C1

PAU20B22 PAU20B21 PAU20B19 PAU20B17 PAU20B16 PAU20B15 PAU20B14 PAU20B13 PAU20B12 PAU20B11 PAU20B10 PAU20B9 PAU20B8 PAU20B7 PAU20B6 PAU20B5 PAU20B4 PAU20B3 PAU20B2 PAU20B1

PAU20A22 PAU20A20 PAU20A19 PAU20A18 PAU20A17 PAU20A16 PAU20A15 PAU20A13 PAU20A12 PAU20A11 PAU20A10 PAU20A9 PAU20A8 PAU20A7 PAU20A6 PAU20A5 PAU20A4 PAU20A3 PAU20A2 PAU20A1

PAU20D21

PAU20B20

PAU20A21

COU2

PAX101

PAX103

PAX102

PAX104

COX1

PAX201 PAX202 COX2 PAC1901

PAC16801

PAC16901

PAC17001

PAC17101

PAC17201

PAC17301

PAC18401 PAC18501

PAC18601

PAC18701

PAC18801

PAC18901

PAC19001

PAC19101

PAC19201

PANT302

PANT1201

PAU20H8 PAU20H10

PAU20J7 PAU20J9 PAU20J11

PAU20K8

PAU20L7 PAU20L11

PAU20M8

PAU20N7 PAU20N11

PAU20P8 PAU20P10

PAU20R7 PAU20R9

PAU20T8 PAU20T10

PAL802

PANT1002

PAL701

PANT1102

PAR14602

PAC4901 PAC5301

PAC5702 PAC5802

PAC5902

PAC6002

PAC6102

PAC16401

PAC17401

PAC17501

PAC17601

PAC17701

PAC17801

PAC17901

PAC18001

PAC18101

PAC18201

PAC18301

PAIC905



PAIC11012

PAIC11037

PAIC11064

PAL501

PANT502

PAR5302 PAR5802

PAU20E12

PAU20H12

PAU20K12

PAU20M12

PAU20P12

PAU20R11

PAC7801

PAC9001

PAC15401

PAC15501

PAC15601

PAC15701 PAC15801 PAC15901 PAC16001 PAC16101 PAC16201 PAC16301

PAC21501 PAC21601 PAC21701

PAC21801 PAC21901 PAC22001 PAC22101

PAC22201

PAC22301 PAC22401 PAC22501 PAC22601

PAC22701 PAC22801 PAC22901

PAC23001

PAC23101

PAC23201

PANT702

PAR8902

PAU10A1 PAU10A8

PAU10B2

PAU10C1 PAU10C9

PAU10D2 PAU10D9

PAU10E9

PAU10F1

PAU10G7

PAU10H2 PAU10H9

PAU10K2 PAU10K8

PAU10N1 PAU10N9

PAU10R1 PAU10R9

PAU20C1

PAU20F2

PAU20H6

PAU20J3

PAU20M4

PAU20N1

PAC1201

PAC3101

PAC3201

PAC3301

PAC3401

PAC3501 PAC3601

PAC3901

PAC4001

PAC4101

PAC4201

PAC4301

PAC4401

PAC4501

PAC4601

PAC6202

PAC6302

PAC6402

PAC6502

PAC7202

PAC7301 PAC7401 PAC7501

PAC7601

PAC8701

PAC8801

PAC8901 PAC9101

PAC9201

PAC9501

PAC9601

PAC9901

PAC10001

PAC10101 PAC10201

PAC10301

PAC10401

PAC10501

PAC10601

PAC10701

PAC10801

PAC10901

PAC11001

PAC11101

PAC11201

PAC11301

PAC11402 PAC11502

PAC11602

PAC11702

PAC11802

PAC11902

PAC12002

PAC12102 PAC12202

PAC12302


PAC13102

PAC13202

PAC13302 PAC13401

PAC13501

PAC13601



PAC15102

PAC15202

PAC15302

PAC23501

PAC23801

PAC23901

PAD1405 PAD1505

PAIC5013

PAIC5023

PAIC5025 PAIC5031

PAIC5040

PAIC5048

PAIC5056

PAIC604 PAIC7014

PAIC8013

PAIC8023

PAIC8025 PAIC8031

PAIC8040

PAIC8048

PAIC8056

PAIC11020

PAIC11031

PAIC11042 PAIC11050

PAIC11056

PAIC1206

PAIC1305

PAIC1505

PAIC1605

PAIC1708

PAIC1801

PAIC1804

PAIC1908

PAIC2008

PAIC2105

PAIC2202 PAIC2203

PAIC2308

PAJ5025

PAJ5026

PAJ701

PAJ1205

PAJ1601 PAJ1602

PAL302 PAL402

PANT201

PAR1202

PAR1602 PAR2002

PAR3502

PAR6102

PAR6202

PAR6302

PAR6402

PAR6602

PAR6702 PAR6802

PAR7302 PAR7402

PAR7502

PAR7802 PAR9802

PAR9902

PAR10002

PAR10102 PAR10202

PAR11102 PAR11802

PAR12002

PAR12702

PAR12902

PAR13002

PAR13102

PAR13702

PAR14002

PAR14102

PAR14202 PAR14302

PAR14402

PAU20A17

PAU20AA7 PAU20AA17

PAU20AB4 PAU20AB14

PAU20B14

PAU20C21

PAU20D18

PAU20E15

PAU20F12 PAU20F22

PAU20G19

PAU20H16

PAU20J13

PAU20K20

PAU20L17

PAU20M14

PAU20N21

PAU20P18

PAU20R5 PAU20R15

PAU20T2 PAU20T12 PAU20T22

PAU20U19

PAU20V6 PAU20V16

PAU20W3 PAU20W13

PAU20Y10 PAU20Y20

PAJ2010

PAJ2012

PAC5101 PAC5501

PAC23601

PAIC9010 PAIC10010

PAJ1603 PAJ1604

PAJ1701

PANT902

PAC23702 PAD1705

PAJ401

PAF101

PANT101

PANT401 PANT601 PANT801

PAR15902

PAT603

PAJ202

PAJ204

PAJ206 PAR15901

PAJ1001 PAJ1005

PAR10702 PAR11402

PAJ901

PAJ1703

PAJ5019

PAR1201

PAU20N18

PAJ5011

PAR7602

PAU20K16

PAJ5012

PAR7702

PAU20K13

PAJ5013

PAR7401

PAU20L16

PAJ5014

PAR7501

PAU20K17

PAJ5017

PAR7301

PAU20M16

PAJ508

PAU20J16

PAJ507

PAU20J15

PAJ5010

PAU20K14

PAJ509

PAU20J17

PAJ502

PAR6801

PAU20L18

PAJ504

PAU20N19

PAJ503

PAU20M18

PAJ5016

PAR2001

PAU20M17

PAJ5022

PAR7002

PAU20M13

PAJ5021

PAR7102

PAU20L13

PAJ5020

PAR7202

PAU20M15

PAJ5015

PAR6902

PAU20L15

PAJ5018

PAR1601

PAU20L14

PAJ506

PAR6701

PAU20H18

PAJ505

PAR6601

PAU20N20

PAIC2306

PAU20L12

PAR14201

PAU20U8

PAIC1803 PAJ1801

PAU20R4

PAU10N3 PAU20L3

PAU10P7 PAU20M1

PAU10P3 PAU20L1

PAU10N2 PAU20L4

PAU10P8 PAU20M3

PAU10P2

PAU20N4 PAU10R8

PAU20N2 PAU10R2

PAU20N5 PAU10T8

PAU20R1

PAU10R3

PAU20P6

PAU10L7

PAU20M5 PAU10R7

PAU20P1

PAU10N7

PAU20P2

PAU10T3 PAU20N3

PAU10M2

PAU20J6

PAU10N8

PAU20M2

PAU10M3 PAU20K6

PAU10K3

PAU20K4

PAR9101 PAU10K7

PAU20P4

PAR9102 PAU10J7

PAU20P5

PAU10K9

PAU20J4 PAU10L2

PAU20L6

PAU10E7

PAU20G2

PAU10D3

PAU20F1

PAU10E3

PAU20H4

PAU10F7

PAU20J1

PAU10F2

PAU20H2

PAU10F8

PAU20G3 PAU10H3

PAU20J5

PAU10H8

PAU20K1

PAU10G2

PAU20H5

PAU10H7

PAU20H3

PAU10D7

PAU20G1

PAU10C3 PAU20C2

PAU10C8

PAU20F3

PAU10C2

PAU20A1 PAU10A7

PAU20E2

PAU10A2

PAU20B2 PAU10B8

PAU20D2

PAU10A3

PAU20B1

PAU10G3

PAU20J2

PAU10F3

PAU20K2

PAU10B7

PAU20D1

PAU10C7

PAU20E1

PAU10K1

PAU20M6

PAU10J3

PAU20K3

PAR15802

PAU10T2

PAU20F4

PAU10L3

PAU20L5

PAIC701

PAU20D16

PAIC702

PAU20E16

PAIC602

PAU20C15

PAIC603

PAU20D15

PAIC606

PAU20F16

PAIC607

PAU20C17

PAIC9011

PAR5201

PAIC10011

PAR5401

PAIC601

PAU20C14

PAIC6014

PAJ1016

PAIC6013

PAJ103

PAIC6010

PAJ1018

PAIC609

PAJ105

PAIC11038

PAU20N17

PAIC11039

PAU20P17

PAIC11040

PAU20R18

PAIC11041

PAU20P16

PAIC11043

PAU20T18

PAIC11044

PAU20R17

PAIC11045

PAU20U18

PAIC11046

PAU20R16

PAIC11059

PAU20P14

PAIC11053

PAU20N14

PAIC11048

PAU20N15

PAIC11055

PAU20R14

PAIC11052

PAU20P15

PAIC11054

PAU20N13

PAC102 PAC202

PAC302 PAC402 PAC502

PAC602 PAC702

PAC1002 PAC1102 PAC1202

PAC1302

PAC1402 PAC1702

PAC1802

PAC1902

PAC2002 PAC2102

PAC2202

PAC2302

PAC2402

PAC2502

PAC2602

PAC2702

PAC2802

PAC2902

PAC3002

PAC3102

PAC3202

PAC3302

PAC3402

PAC3502 PAC3602

PAC3702

PAC3802

PAC3902

PAC4002

PAC4102

PAC4202

PAC4302

PAC4402

PAC4502

PAC4602

PAC4702

PAC4802

PAC4902

PAC5002

PAC5102

PAC5202

PAC5302

PAC5402

PAC5502

PAC5602

PAC5701

PAC5801

PAC5901

PAC6001

PAC6101

PAC6201

PAC6301

PAC6401

PAC6501

PAC6602 PAC6702 PAC6801

PAC6901 PAC7002

PAC7102

PAC7201

PAC7302 PAC7402 PAC7502

PAC7602

PAC7702

PAC7902 PAC8002

PAC8102 PAC8202

PAC8302

PAC8402 PAC8502

PAC8602

PAC8702

PAC8802

PAC8902

PAC9002

PAC9102 PAC9202

PAC9302 PAC9402

PAC9502

PAC9602

PAC9702 PAC9802

PAC9902

PAC10002

PAC10102 PAC10202

PAC10302

PAC10402

PAC10502

PAC10602

PAC10702

PAC10802

PAC10902

PAC11002

PAC11102

PAC11202

PAC11302

PAC11401 PAC11501

PAC11601

PAC11701

PAC11801

PAC11901

PAC12001

PAC12101 PAC12201

PAC12301


PAC13101

PAC13201

PAC13301

PAC13402

PAC13502

PAC13602



PAC15101

PAC15201

PAC15301

PAC15402

PAC15502

PAC15602


PAC16402

PAC16502

PAC16602

PAC16702

PAC16802

PAC16902

PAC17002

PAC17102

PAC17202

PAC17302

PAC17402

PAC17502

PAC17602

PAC17702

PAC17802

PAC17902

PAC18002

PAC18102

PAC18202

PAC18302

PAC18402 PAC18502

PAC18602 PAC18702

PAC18802

PAC18902

PAC19002

PAC19102

PAC19202

PAC19301

PAC19401 PAC19501

PAC19601

PAC19701

PAC19801

PAC20802 PAC20902

PAC21002

PAC21102

PAC21302 PAC21402

PAC21502 PAC21602 PAC21702

PAC21802 PAC21902 PAC22002 PAC22102

PAC22202

PAC22302 PAC22402 PAC22502 PAC22602

PAC22702 PAC22802 PAC22902

PAC23002

PAC23102

PAC23202

PAC23502 PAC23602

PAC23701

PAC23802

PAC23902

PAD103 PAD203 PAD1203

PAD1302 PAD1402 PAD1502

PAD1702

PAD1901

PAIC1012

PAIC1018 PAIC1019


PAIC1032

PAIC203 PAIC209

PAIC303 PAIC309

PAIC403 PAIC409

PAIC504

PAIC508

PAIC5014

PAIC5021 PAIC5022

PAIC5024

PAIC5028

PAIC5036

PAIC5044

PAIC5052

PAIC605

PAIC608

PAIC707

PAIC804

PAIC808

PAIC8014

PAIC8021 PAIC8022

PAIC8024

PAIC8028

PAIC8036

PAIC8044

PAIC8052






PAIC11025

PAIC11035 PAIC11047

PAIC11051

PAIC11065 PAIC1202

PAIC1302

PAIC1402

PAIC14012

PAIC1502

PAIC1602

PAIC1705

PAIC1802

PAIC1905

PAIC2005

PAIC2102

PAIC2205

PAIC2304

PAIC2309

PAIC2502

PAJ101

PAJ1013

PAJ1014

PAJ1026

PAJ201

PAJ203

PAJ205

PAJ207 PAJ208

PAJ2013 PAJ2014

PAJ2019 PAJ2020

PAJ2025 PAJ2026

PAJ2031 PAJ2032

PAJ2037 PAJ2038

PAJ2043 PAJ2044

PAJ2049 PAJ2050

PAJ2055 PAJ2056

PAJ2061 PAJ2062

PAJ2067 PAJ2068

PAJ2073 PAJ2074

PAJ2079 PAJ2080

PAJ2084

PAJ2085 PAJ2086

PAJ2091

PAJ2095 PAJ2096

PAJ2099 PAJ20100

PAJ301

PAJ3013

PAJ3014

PAJ3026

PAJ405 PAJ501 PAJ5023

PAJ5024

PAJ602

PAJ706

PAJ802

PAJ906

PAJ1102 PAJ1206

PAJ1301

PAJ1304

PAJ1307

PAJ1401

PAJ1404

PAJ1407

PAJ1605 PAJ1606

PAJ1802

PAR101 PAR501

PAR801 PAR901

PAR1401 PAR1801

PAR2101 PAR2201

PAR2901

PAR3001

PAR4101

PAR4201

PAR5101 PAR5701

PAR5901

PAR6002

PAR6901

PAR7001

PAR7101

PAR7201

PAR7601

PAR7701

PAR8301

PAR9001

PAR9301

PAR9601

PAR9701

PAR12601

PAR12801

PAR13901

PAR14501

PAR14901

PAR15401

PAR15501

PAR15601

PAR15701

PAR15801

PAT103

PAT203

PAT303

PAT403

PAT502

PATP3700

PAU10A9

PAU10B1 PAU10B3 PAU10B9

PAU10D1 PAU10D8

PAU10E1 PAU10E2 PAU10E8

PAU10F9

PAU10G1 PAU10G8 PAU10G9

PAU10J2 PAU10J8

PAU10M1 PAU10M9

PAU10P1 PAU10P9

PAU10T1 PAU10T9

PAU20A2 PAU20A3 PAU20A5 PAU20A7 PAU20A9 PAU20A10 PAU20A11 PAU20A12 PAU20A22

PAU20AA2 PAU20AA12 PAU20AA22

PAU20AB9 PAU20AB19

PAU20B3 PAU20B10 PAU20B12 PAU20B19

PAU20C3 PAU20C6 PAU20C9 PAU20C10 PAU20C12 PAU20C16

PAU20D3 PAU20D4 PAU20D8 PAU20D9 PAU20D12 PAU20D13

PAU20E4 PAU20E5 PAU20E7 PAU20E9 PAU20E11 PAU20E20

PAU20F5 PAU20F11 PAU20F17

PAU20G5 PAU20G6 PAU20G7 PAU20G8 PAU20G9 PAU20G10 PAU20G12 PAU20G14

PAU20H1 PAU20H7 PAU20H9 PAU20H11 PAU20H21

PAU20J8 PAU20J10 PAU20J12 PAU20J18

PAU20K5 PAU20K7 PAU20K9 PAU20K11 PAU20K15

PAU20L2 PAU20L8 PAU20L9 PAU20L10 PAU20L22

PAU20M7 PAU20M9 PAU20M10 PAU20M11 PAU20M19

PAU20N6 PAU20N8 PAU20N9 PAU20N10 PAU20N16

PAU20P3 PAU20P7 PAU20P9 PAU20P11 PAU20P13

PAU20R8 PAU20R10 PAU20R12 PAU20R20

PAU20T7 PAU20T9 PAU20T11 PAU20T17

PAU20U4 PAU20U14

PAU20V1 PAU20V11 PAU20V21

PAU20W8 PAU20W18

PAU20Y5 PAU20Y15

PAX102

PAX104 PAIC1401

PAR9602 PATP1500

PAU20Y22

PAC8301 PAD101

PAIC1403

PAJ902

PATP1400

PAC8401

PAD102

PAIC1404

PAJ903

PATP1600

PAIC1409

PAR9702

PATP3800

PAU20W19

PAC8501

PAD202

PAIC1407

PAJ905

PATP3500

PAC8601 PAD201

PAIC1406

PAJ904

PATP3600

PAR3402

PAR14001

PAR18001

PAU20U12

PAD702

PAJ1003

PAR10602

PAD902

PAJ1007

PAR11302

PAIC1606

PATP900

PAU20P20

PAIC1604

PATP1000

PAU20P19

PAC23302 PAC23402

PAD703

PAD803

PAD903

PAD1003

PAIC1703 PAIC1903

PAJ1004 PAJ1008

PAR11502 PAR16502 PAD701

PAJ1002

PAR11002

PAD901

PAJ1006

PAR11702

PAC20201 PAJ1306 PAC20101 PAJ1305

PAC20602 PAJ1406 PAC20502 PAJ1405

PAC20001 PAJ1303 PAC19901 PAJ1302

PAC20402 PAJ1403 PAC20302 PAJ1402

PAIC11016

PAR15001

PAU20V12

PAIC11017

PAR15102

PAU20R13

PAIC11018

PAR15302

PAU20U13

PAIC11019

PAR15201

PAU20T13

PAR16002 PAT401

PAU20E13

PAR16102

PAT101

PAU20F13

PAR16202

PAT201

PAU20E14

PAR16302

PAT301

PAU20A13

PAR18701

PAU20Y2

PAR20101

PAU20V4

PAR18402

PAU20U3

PAR19402

PAU20T1

PAR16802

PAR18002

PAU20V9

PAR18301

PAU20AA3

PAR19301

PAU20R2

PAR18802

PAU20AA1

PAR19802

PAU20U5

PAR18501

PAU20AB2

PAR17701

PAU20W7

PAR19901

PAU20T3

PAR18202

PAU20U6

PAR20202

PAU20R6

PAR20301

PAU20R3

PAR9201

PAU20Y9

PAR9202 PAR20002

PAR19501

PAU20V3

PAR18901

PAU20W1

PAR19101

PAU20U1

PAR19602

PAU20V5

PAR19002

PAU20W2

PAR19202

PAU20V2

PAR16901

PAU20V8

PAR17002

PAU20T5

PAR17602

PAU20V7

PAR9501

PAU20Y4

PAR16701

PAU20W9 PAR17202 PAU20Y7

PAR17901

PAU20Y6

PAR17402

PAU20T6 PAR17301

PAU20W5

PAR19701

PAU20U2

PAR17802

PAU20Y8

PAR18602

PAU20AB1

PAR17101

PAU20U7

PAR18101

PAU20W6

PAR17501

PAU20AA8

PAR16602

PAU20AB3

PAR14401

PAU20U11

PAR14502

PAU20U10

PAJ1101

PAR14301

PAU20U9

PAIC14010

PAU20V20

PAIC6015

PAJ102

PAIC6016

PAJ1015

PAC101 PAC201

PAIC102 PAIC107


PANT102

PAC301


PAC401

PAIC101

PAR202 PAC501

PAIC108

PAR302

PAC601

PAR201

PAC701

PAR301

PAC801

PAIC1023 PAC802 PAIC1020

PAIC1024 PAIC1033 PAL102

PAC901

PAIC1014 PAC902 PAIC1013

PAIC1017

PAIC1034 PAL201

PAC1001

PAC1301

PAC1401

PAC1502

PAL101

PANT202

PAR602

PAR1002

PATP1300 PAC1101

PAC1602

PAC1701

PAC1801

PAL202

PANT301

PAR702

PAR1102

PATP2000

PAC1501

PAIC1028

PAR601

PAR802 PATP2100

PAC1601

PAIC109

PAR701

PAR902 PATP2200

PAC2001 PAIC1026 PAC2101 PAIC1011 PAC2201

PAIC201 PAIC202

PANT402

PAC2301

PAIC204

PAIC205 PANT501

PAR1302

PAR1502

PATP2300 PAC2401

PAIC208

PAC2501

PAIC301 PAIC302

PANT602

PAC2601

PAIC304

PAIC305 PANT701

PAR1702

PAR1902

PATP2500 PAC2701

PAIC308

PAC2801

PAIC401 PAIC402

PANT802

PAC2901

PAIC404

PAIC405 PANT901

PAR402

PAR2302

PATP2700 PAC3001

PAIC408

PAC3701 PAJ1028 PAR2902

PAC3801 PAJ1027 PAR3002

PAC4701 PAJ3028 PAR4102

PAC4801

PAJ3027 PAR4202

PAC5001

PAIC901


PANT1001

PAR5002 PATP100

PAC5201 PAIC9015

PAC5401

PAIC1001


PANT1101

PAR5602 PATP300

PAC5601 PAIC10015

PAC6601 PAC6802

PAIC1109

PAL301

PAC6701 PAC6902

PAIC1104

PAL401

PAC7001 PAIC1102

PAX101

PAC7101

PAIC1103

PAX103

PAC7701

PAIC1303

PANT1202

PANT1302

PAC7802 PAC7901 PAC8001

PAR8901

PAR9002

PATP3100

PAU10H1

PAU10M8

PAC8101 PAC8201

PAIC14015 PAIC14020

PAJ1702

PAC9301

PAR12401

PAC9401

PAR12501

PAC19302

PAC19402 PAC19502

PAL702

PAU20B5 PAU20B7 PAU20B9 PAU20B11

PAU20C4 PAU20C8

PAC19602

PAC19702

PAC19802 PAL801

PAU20D6 PAU20D10

PAU20E8

PAU20F7 PAU20F9

PAC20801 PAC20901 PAL902

PAR14701

PAC21301 PAIC2503

PAR14802

PAX202

PAC21401 PAIC2504

PAR14801

PAX201

PAC23301

PAD802

PAIC1702

PAR10902

PATP1700

PAC23401

PAD1002

PAIC1902

PAR16402

PATP3300

PAD301 PAR9801 PAD302 PAT402




PAD1102

PAIC2002

PAR12102

PAD1103

PAIC2003

PAR12202

PAD1301

PAR13801

PAD1401 PAJ1201 PAD1403 PAJ1203 PAD1404

PAR15202

PAD1406

PAR15002

PAD1501

PAR15101

PAD1503

PAR15301

PAD1504 PAJ1204 PAD1506 PAJ1202

PAD1601 PAR3501

PAD1602 PAT503

PAD1902

PAJ801 PAT602 PAF102

PAJ601

PAIC104

PAR102

PAIC1010

PAR1101

PAR8801

PAIC1027

PAR1001

PAR8001

PAIC206

PAR1301

PAR1402 PATP2400

PAIC207

PAR1501

PAR8401

PAIC306

PAR1701

PAR1802 PATP2600

PAIC307

PAR1901

PAR8601

PAIC406

PAR401

PAR502 PATP2800

PAIC407

PAR2301

PAR5202 PAR5402

PAR8201

PATP200

PAIC909

PAR5301

PAR8501

PAIC9016

PAR5001 PAR5102

PATP2900

PAIC1009

PAR5801

PAR8701

PAIC10016

PAR5601 PAR5702

PATP3000

PAIC1106

PAR6001

PAIC11013

PAR5902

PAIC11014

PAR6101

PAIC11061

PAIC1203

PAR6502

PAIC11062

PAIC1204 PAR6401 PAIC11063

PAIC1205

PAR6301

PAIC1201

PAR6201

PAR6501

PAIC1304

PANT1301

PAR8302

PAIC14011 PAR2102 PAIC14019 PAR2202

PAIC1501

PAR10201

PAR10302

PAIC1503

PAR10402

PAIC1504

PAR10502

PAIC1601

PAR11202

PAIC1603

PAR11902

PAIC1706

PAR11101

PAR11201

PATP1800

PAIC1906

PAR11801

PAR11901

PATP3400

PAIC2006

PAIC2101

PAR12001

PATP1900

PAIC2103

PAIC2106 PAIC2104

PAR12301

PATP1100

PAIC2301 PAR13202

PAIC2302

PAR13302

PAIC2303

PAR13402

PAIC2305

PAR13502

PAIC2307

PAR13602

PAIC2505 PAR14902

PAJ209 PAR3102

PAJ2011 PAR4902

PAJ2015 PAR5502

PAJ2016 PAR8101

PAJ2017 PAR9402

PAJ2027 PAR9502

PAJ2028 PAR16601

PAJ2029 PAR16702

PAJ2030 PAR16801

PAJ2033 PAR16902

PAJ2034 PAR17001

PAJ2035 PAR17102

PAJ2036 PAR17201

PAJ2039 PAR17302

PAJ2040 PAR17401

PAJ2041 PAR17502

PAJ2042 PAR17601

PAJ2045 PAR17702

PAJ2046 PAR17801

PAJ2047 PAR17902

PAJ2051 PAR18102

PAJ2052 PAR18201

PAJ2053 PAR18302

PAJ2054 PAR18401

PAJ2057 PAR18502

PAJ2058 PAR18601

PAJ2059 PAR18702

PAJ2060 PAR18801

PAJ2063 PAR18902

PAJ2064 PAR19001

PAJ2065 PAR19102

PAJ2066 PAR19201

PAJ2069 PAR19302

PAJ2070 PAR19401

PAJ2071 PAR19502

PAJ2072 PAR19601

PAJ2075 PAR19702

PAJ2076 PAR19801

PAJ2077 PAR19902

PAJ2078 PAR20001

PAJ2081 PAR20102

PAJ2082 PAR20201

PAJ2083 PAR20302

PAJ702 PAR16001

PAJ703 PAR16101

PAJ704 PAR16201

PAJ705 PAR16301

PAJ1308 PAR15502

PAJ1309 PAR15402

PAJ1408 PAR15702

PAJ1409 PAR15602

PAR3401

PAR7801 PAR7902 PAR8002 PAR8202 PAR8402 PAR8502

PAR8602 PAR8702 PAR8802

PAT501

PATP500

PAR9302 PATP3200

PAU10L8

PAR10601 PAR10701

PAR10802

PAR10801

PAR10901

PAR11001

PAR11501 PAR11301 PAR11401

PAR11602

PAR11601

PAR11701

PAR16401

PAR16501

PAR13701

PAR13802

PAU20G11

PAR13902

PAT601

PAR14601

PAU20F8

PAR14101

PAU20N12

PAR12701 PAR12802 PAU20U22

PAIC708

PAU20F15

PAR4901

PAU20AB7

PAIC704

PAU20F14 PAIC5026

PAU20D17

PAIC8026

PAU20J19

PAIC5027

PAU20C18

PAIC5029 PAU20E17 PAIC5030

PAU20C19

PAIC5032

PAU20A15

PAIC5033

PAU20B16

PAIC5034

PAU20A16

PAIC5035

PAU20B17

PAIC5037

PAU20C20

PAIC5038

PAU20A18

PAIC5039

PAU20A19

PAIC5041

PAU20B18

PAIC5042

PAU20A20

PAIC5043

PAU20B20

PAIC5045

PAU20A21

PAIC5046

PAU20B22

PAIC5047

PAU20B21

PAIC5049

PAU20C22

PAIC5050

PAU20D21

PAIC5051

PAU20D22

PAIC5053

PAU20E21

PAIC5054

PAU20E22

PAIC5055

PAU20F20

PAIC501

PAU20F19

PAIC502

PAU20F18

PAIC503

PAU20E19

PAIC505

PAU20D19

PAIC506

PAU20D20

PAIC507

PAU20E18

PAIC8027

PAU20G17

PAIC8029

PAU20G20

PAIC8030

PAU20G18

PAIC8032

PAU20H20

PAIC8033

PAU20H19

PAIC8034

PAU20J20

PAIC8035

PAU20K18

PAIC8037

PAU20K19

PAIC8038

PAU20L20

PAIC8039

PAU20L19

PAIC8041

PAU20H22

PAIC8042

PAU20J21

PAIC8043

PAU20J22

PAIC8045

PAU20K21

PAIC8046

PAU20K22

PAIC8047

PAU20L21

PAIC8049

PAU20M20

PAIC8050

PAU20M22

PAIC8051

PAU20M21

PAIC8053

PAU20N22

PAIC8054

PAU20J14

PAIC8055

PAU20H17

PAIC801

PAU20H15

PAIC802

PAU20G16

PAIC803

PAU20G15

PAIC805

PAU20H14

PAIC806

PAU20H13

PAIC807

PAU20G13

PAC20202

PAU20A8

PAC20102

PAU20B8

PAC20601

PAU20C11

PAC20501

PAU20D11

PAC20002

PAU20A4

PAC19902

PAU20B4

PAC20401

PAU20C5

PAC20301

PAU20D5

PAC21201

PAU20E6

PAC20701

PAU20F6

PAC21202

PAIC2506

PAC20702

PAIC2507

PAIC7011

PAJ107

PAIC7012

PAJ1020

PAIC709

PAJ1019

PAR3301

PAIC7010

PAJ106

PAR3302

PAIC6011

PAJ104

PAIC6012

PAJ1017

PAR3101

PAU20AB8

PAR8102

PAU20AA5

PAR5501

PAU20AA6

PAR9401

PAU20AB5

PAR12302

PAU20AB22

PAJ1502

PAR12201 PAR12502

PAJ1501

PAR12101 PAR12402

PAIC2201

PAR12602 PATP1200

PAU20Y21

PAC9801

PAD1202

PAIC2204

PAJ1503

PAC9701

PAD1201

PAIC2206

PAJ1504

PAR10301 PATP600

PAU20C13

PAR10501 PATP800

PAU20B13

PAR3201

PAR10401

PATP700

PAU20D14

PAR3202

PAU20A14

PAJ3020

PAR4302

PAJ307

PAR4301

PAD1706

PAIC1107

PAD1704

PAIC1108

PAD1701

PAJ402

PAD1703

PAJ403

PAL901

PAC21001

PAC21101

PAIC2501

PAIC2508 PAR14702

PAIC1301

PAIC1306

PAR7901

PATP400

PAIC509

PAJ1025 PAR2402

PAIC5010

PAJ1012 PAR2401

PAIC5011

PAJ1024 PAR2502

PAIC5012

PAJ1011 PAR2501

PAIC5015

PAJ1023 PAR2602

PAIC5016

PAJ1010

PAR2601

PAIC5019

PAJ1021

PAR2702 PAIC5020

PAJ108

PAR2701

PAC16501

PAC16601

PAC16701

PAL502

PAU20K10 PAIC5017

PAJ1022 PAR2802

PAIC5018

PAJ109

PAR2801

PAR12901

PAR13201

PAU20T19

PAR13501

PAU20P22

PAR13301

PAU20R22

PAR13001 PAR13401

PAU20P21

PAR13101 PAR13601

PAU20R21

PAIC809

PAJ3025 PAR3602

PAIC8010

PAJ3012 PAR3601

PAIC8011

PAJ3024 PAR3702

PAIC8012

PAJ3011 PAR3701

PAIC8015

PAJ3023 PAR3802

PAIC8016

PAJ3010 PAR3801

PAIC8019

PAJ3021

PAR3902 PAIC8020

PAJ308

PAR3901

PAIC8017

PAJ3022 PAR4002

PAIC8018

PAJ309

PAR4001

PAJ3019

PAR4402

PAJ306

PAR4401

PAJ3018

PAR4502

PAJ305

PAR4501

PAJ3017

PAR4602

PAJ304

PAR4601

PAJ3015

PAR4802

PAJ302

PAR4801

PAJ3016

PAR4702

PAJ303

PAR4701

Figure 5.14: Resulting PCB highlighting traces on signal layers

48

6 Simulation

The aim of using a 3d eld simulation program as post layout validation is to

ensure that the signal integrity requirements are met with the designed PCB.

Therefore S-parameters are calculated for a given set of traces, which can be used

to generate eye diagrams for given signals [54].

The software used is the CST microwave studio version 2018. The simulation

environment is set up using the guides available in [54].

The proposed work ow is to import the layout from the Altium designer via

ODB++ manufacturing data, including layer stackups and passive component

values. To optimise the duration of the simulation, the nets that are analysed are

cut out of the full PCB, with spacing of 10 mm to the selected traces, maintaining

a rectangular cut-out [55]. The simulation analysis is described for the DDR3

crosstalk estimation, the SATA 3 Gbit s−1 signal integrity analysis as well as the

documentation of the optimisation of the Camera Link base LVDS channels.

6.1 DDR3

The simulation of the DDR3 interface is aimed to verify that the crosstalk between

data lines is within the specication, by analysing the s-parameters linked to the

crosstalk parameters. The simulation is conducted for the data lines DQ5 and

DQ7, as they are located in the center of the data line bus and the documentation

of the analysis is representative of all lines.

The schematic conguration of the crosstalk simulation is depicted in gure 6.1,

showing the conguration of the ports. The ports 1 and 3 are located on the

pads of the DDR3 memory chip, while the ports 2 and 4 are placed on the FPGA

pads. The s-parameters of interest for the crosstalk behaviour are the S41 and

S23, as they dene the far end crosstalk for two data lines.

49

6 Simulation

DQ5port 1 port 2

DQ7port 3 port 4

Figure 6.1: Port description of the crosstalk measurement

Figure 6.2 shows the highlighted data lines DQ5 and DQ7 in the CST environ-

ment. They consist of staggered micro vias connecting the BGA pads on the

top layer Sig1 to the stripline traces routed on layer Sig2. The four specied

wave-ports are referenced to the ground net, with an impedance of 50 Ω. Port

1 and port 3 emerge from the DDR3 chips pads, while port 2 and port 4 are

connected to the BGA pads associated to the FPGA chip.

Figure 6.2: Image of tested DDR3 Data Lines DQ5 and DQ7 on Signal Layer 2

To estimate the maximum bandwidth at which to ensure the crosstalk margin is

met, the maximum rise time of the data signals is necessary.

The data sheet lists the maximum occurring signal slew-rate as 12 V ns−1, which

leads to a maximum rise time of 112.5 ps, when considering the power supply

voltage of 1.35 V. [38]

Using the bandwidth estimation given as BW = 0.35/Trise by Johnson in [13],

the maximum occurring frequency of the DDR3 signals is 3.11GHz.

50

6 Simulation

The maximum crosstalk voltage injected from one channel into a neighbouring

channel is selected to be 5 %, leading to a maximum magnitude of the crosstalk

relevant s-parameters S41 and S21 as −26 dB, equation 6.1.

Smax = 20 · log(5 %) = −26.02 dB (6.1)

The results of the conducted crosstalk simulations are depicted in gure 6.3,

showing the S41 and S21 parameters for three dierent spacings between data

lines DQ5 and DQ7. The initial spacing is set to 100 µm, resulting in magnitudes

of the crosstalk parameters exceeding the −26 dB limit.

For the second iteration, the spacing rules for the data lines and address lines are

increased to 150 µm and all traces are re-routed to comply.

0 0.5 1 1.5 2 2.5 3 3.5 4

Frequency in GHz

-60

-50

-40

-30

-20

-10

0

Mag

nitu

de in

dB

S-Parameter DQ5-DQ7

S21 100 umS21 150 umS21 170 umS41 100 umS41 150 umS41 170 um

Figure 6.3: Simulated s-parameters of DQ5 to DQ7 data lines, with spacings of100 µm, 150 µm and 170 µm

51

6 Simulation

As gure 6.3 shows, the increased spacing leads to a signicant reduction of the

crosstalk parameter of almost −10 dB throughout the frequency range of interest.

Even though the required crosstalk dampening of 26 dB is now met throughout

the specied frequency range, the layout arrangement allows an increase of the

trace spacing to 170 µm. This modication is also conducted to analyse the

behaviour of the crosstalk. The result is depicted in gure 6.3 as the thickest

dotted line, which further improvements the behaviour of the crosstalk in the

frequency range up to 3.11GHz.

As the crosstalk margin for the interface is met, the next simulated analysis is

the evaluation of an eye diagram simulation for a data lines. The main parameter

of interest in this simulation is the undershooting and overshooting behaviour of

the signal.

The data sheet of the selected DDR3L memory chip species the maximum over-

shoot peak amplitude as 0.4 V with the maximum overshot area above VDD as

0.25 V ns, gure 6.4. The maximum peak undershoot amplitude and maximum

undershoot area are dened with the same numerical values.

Time in ns

Voltage in V

VDD

maximum amplitudeovershoot area

Figure 6.4: Denition of overshoot amplitude and area for DDR3L clock and datapins [38]

The simulated eye diagramm for the DQ7 data line is shown in gure 6.5. The

maximum overshoot and undershoot amplitudes are 0.31 V, meeting the re-

quired maximum of 0.4 V. The measured overshoot and undershoot areas are

0.0325 V ns, also within the dened specication.

52

6 Simulation

Figure 6.5: Simulated Eye Diagram DQ7, period: 625 ps, rise and fall time: 60 ps,amplitude: 1.35 V

6.2 Sata RX

The SATA-interfaces possess the highest requirements with regard to signal

bandwidth. The maximum bandwidth arises from the signals maximum occur-

ring rise and fall time of 67 ps for the SATA 3 Gbit s−1 Gen2 standard [47].

The resulting maximum bandwidth for the SATA signals can thereby be

estimated as 5.22 GHz.

The analysed dierential trace is highlighted in gure 6.6. The connector is

visible to the left, with ac-coupling capacitors mounted on the top side. The

stripline traces are routed on layer Sig2 due to the ground planes on both sides.

Figure 6.6: Analysed SATA traces, SATA_RX2

53

6 Simulation

To ensure correct function of the interface, the transmission parameters S21 and

S12 for the dierential data lines are to be kept below −3 dB of attenuation

up to the maximum signal bandwidth. As an example, the documentation of

the simulation process is done for the RX trace of the SATA 2 interface, as the

initial simulation results show the highest transmission attenuation exceeding

the −3 dB above frequencies of 4.5 GHz, gure 6.6.

As the set transmission requirements are not met, the proposed optimisation is

the rearrangement of the staggered micro via arrangement of the FPGAs fanout,

gure 6.7. The initial via arrangement has the second stage microvias from the

ground plane to the Sig2 layer placed directly under the corresponding BGA

pad.

The optimised fanout rotates the traces on the ground pane, leading to the posi-

tioning of the second microvias stage to be under the opposed pad of the data pair.

Figure 6.7: Optimisation of the FPGA fanout for the dierential SATA traces

The simulation results of both fanout arrangements can be compared in g-

ure 6.8. The optimisation, plotted in thicker lines, leads to an improvement in

the attenuation coecient S21, meeting the requirements up to the frequency of

maximum bandwidth of 5.22 GHz. Figure 6.8 also shows the reection coecient

limits given by the SATA standard in [47], which is fullled with the optimised

fanout of the SATA traces.

54

6 Simulation

0 1 2 3 4 5 6 7 8 9 10

Frequency in GHz

-30

-25

-20

-15

-10

-5

0M

agni

tude

in d

BS-Parameter SATA RX2 Trace

S21S21 optimisedS11S11 optimisedS11 Required Gen2

Figure 6.8: Simulated s-parameters of the Sata Rx Channel 2 Port comparing preand post optimisation results

To simulate the signal integrity of the SATA traces, an eye diagram is simulated

according to the signal specications given by the SATA standard in [47]. For

the SATA 3 Gbit s−1, the signal period is setup with 330 ps, while the rise time

of 67 ps is applied. The amplitude of the signal at the transmitter is 400 mV. To

account for transmitter jitter the duty cycle jitter is set to 0.05 % unit interval

[47].

The resulting eye diagram is depicted in gure 6.9, which shows overshoot and

undershoot of 25 % after the level transients, which are within the specication.

The valid data region spans ±120 mV, which is also achieved. The resulting eye

width also complies with the requirements that the SATA 3 Gbit s−1 standard

species, as the maximum jitter does not exceed 50 ps. [47]

55

6 Simulation

Figure 6.9: Simulated eye diagram using SATA 3 Gbit s−1 standard signal setup

6.3 Camera Link base

To verify the signal integrity of the Camera Link interface during the simulation

phase, all Camera Link related LVDS channels are analysed. The documentation

is done representatively for the X1 channel of the Camera Link base receiver.

The maximum bandwidth of the Camera Link signals arises from the specied

maximum rise time of the LVDS data signal, which is 750 ps resulting in a band-

width of 467 MHz. The dierential traces of the X1 LVDS link implemented during

the rst iteration of the layout are shown in gure 6.10a. The traces comprise

the 100 Ω termination resistor in a 0603 package.

The s-parameter simulation for the initial link is shown in thin lines in gure 6.11.

The transmission losses average to 3.5 dB within the specied frequency range.

The reection losses show a minimal attenuation of −9.3 dB. The targeted limits

of 3 dB of admission losses and 10 dB of reection attenuation are not met.

(a) Initial layout of Camera Link channel

X1

(b) Improved layout of Camera Link chan-

nel X1

Figure 6.10: Comparison of Camera Link channel X1 pre and post optimisation

56

6 Simulation

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Frequency in GHz

-20

-18

-16

-14

-12

-10

-8

-6

-4

-2

0M

agni

tude

in d

BS-Parameter Signal X1

S21S21 optimisedS11S11 optimised

Figure 6.11: S-parameter simulation of LVDS channel X1 with 100 Ω termination

The proposed optimisations are depicted in gure 6.11. The 0603 package

termination is changed into a 0402 package, allowing for decreased unterminated

stub length. Furthermore the via transition from Sig2 to Sig1 is moved closer to

the Camera Link connector.

The resulting simulation results are shown in gure 6.11, as thick lines.

As gure 6.11 indicates, signicant improvements in both reection coecient

and admission coecient occur at frequencies above 1.2 GHz, however the

behaviour within the specied bandwidth up to 467 MHz is unchanged.

Even though the determined limits are not achieved after the optimisation,

the signal integrity simulation in form of an eye diagram simulation is carried out.

57

6 Simulation

The resulting eye diagram, simulated for a bit period of 1.68 ns with a rise time

of 0.75 ns and an amplitude of 290 mV is shown in gure 6.12, according to the

Camera Link receiver data sheet [11]. The jitter percentage of 0.089 % used to

setup the simulation is derived from the data sheet, taking a 1 m cable and the

given transmitter jitter into account.

Figure 6.12: Simulated eye diagram LVDS channel X1

The required eye width of 0.7 ns for the dierential input threshold voltage of

100 mV is achieved by the simulation carried out for the optimised layout of

channel X1. As the eye diagram shows, the signal integrity of the link fulls the

signal integrity requirements, the Camera Link interface passes the simulation

phase.

58

7 Verication

This chapter describes the the verication process of the completed PCB. The

tests are executed according to the test plan (Appendix A.1.5) generated during

the implementation phase.

The testing is divided into functional groups, beginning with the verication of

the power supply system. The next step is the testing of the FPGA circuitry.

Furthermore, the verication of the s-parameter simulation of the DDR3 interface

is conducted. Finally the correct function of the low speed interfaces is veried.

7.1 Power-Supply

To ensure that none of the components mounted on the PCB are damaged by

incorrect voltage levels, all net ties located at the outputs of the voltage converters

are disconnected.

The open circuit voltage outputs of all power rails are then measured, according

to the test plan and compared to the requirements regarding each rail, table 7.1.

Table 7.1: Voltage measurements of power rails for open circuit and 20 % FPGAusage

Power rail Requirement Open circuit 20% device usage

1V0 VCCINT 0.95 V − 1.05 V 1.007 V 1.006 V1V8 VCCAUX 1.71 V − 1.89 V 1.809 V 1.801 V3V3 VCCO 2.97 V − 3.45 V 3.345 V 3.342 V5V0 4.75 V − 5.25 V 5.024 V 5.005 V1V35 1.283 V − 1.45 V 1.345 V 1.340 V1V0 GTP 0.97 V − 1.03 V 1.009 V 1.005 V1V2 GTP 1.17 V − 1.23 V 1.208 V 1.201 V

59

7 Verication

With all power rail meeting the requirements of the specied voltage levels,

the start-up behaviour of the rails is analysed. The setup time for each rail

is compared to the specied start-up window according to the requirements, Ap-

pendix A.1.3. The documentation of the sequence verication is done using a

four channel oscilloscope, with the trigger set to the input power supply to ensure

that all measurements can be displayed in a single diagram. The resulting plot

is shown in gure 7.1. The main voltage rails are ramped coincidently, reaching

their specied voltage levels within the timing constraint. Also the linear voltage

regulators for the GTP-transceiver are enabled by the power-good output of the

5V0 rail and achieve the specied timing requirements.

0 2 4 6 8 10 12 14 16 18 20

Time in s 10-3

0

2

4

6

8

10

12

Vol

tage

in V

Supply1V05V03V31V351V81V2 GTP1V0 GTP5V0 PG

Figure 7.1: Veried power supply start-up sequence of the FPGA board

7.2 FPGA

The rst step in verifying the correct behaviour of the FPGA is the JTAG bound-

ary scan, using the Vivado Suite. As the Artix-7 device shows up in the connected

devices list with the correct ID, the next step is the programming of a bit-stream

le (Appendix A.1.8).

60

7 Verication

The initial test program divides the connected oscillator clock signal of 100 MHz

down to a 100 kHz signal, which is used to toggle the connected debugging LEDs.

This veries the JTAG interface of the FPGA as well as the connected oscillator.

The created constraint le used to verity the interfaces connected to the FPGA is

attached as verication project, Appendix A.1.8.

7.3 Camera Link

To verify the correct function of the Camera Link interface, the test pattern mode

of the Dalsa Spyder3 is used, as specied within the test plan (Appendix A.1.5).

To set the camera into test mode, two of the LED expansion header pins are

congured as links to the Camera Link serial interface, allowing for the external

connection of a USB-to-Serial converter. This enables the communication with

the camera via a terminal program on a computer, to manually review the

cameras status [56].

The test pattern created by the camera is shown in gure 7.2, containing a

number of 1024 12 bit pixel values, in which the rst half increments from 0 to

511 and the second half decreases from 4095 to 3584. A verication program

is written for the FPGA which compares the received frames to the expected

pattern, counting the number of detected dierences (Appendix A.1.9).

The verication is conducted over a duration of 30 min, leading to a total number

of 1.8 · 108 received and compared camera test frames. Throughout the test, no

errors are detected while comparing the camera data to the expected results.

61

7 Verication

1 512 1024

Pixel Count

0

512

2048

3584

4096P

ixel

Val

ue12 bit Camera test pattern

Figure 7.2: Generated test pattern image created by the Dalsa Spyder3 camera

7.4 DDR3

The verication of the physical layer of the DDR3 interface is done by measuring

the s-parameters of the signal traces similar to the simulated results. The experi-

mental setup is shown in gure 7.3a, with the unpopulated PCB connected to the

vector network analyser. The Ball Grid Array (BGA) pads of the FPGA and the

DDR3 chip are soldered to SMA based cables, with the cable shield soldered to

a ground pad in close proximity. Figure 7.3b shows the schematic setup of the

measurement, with ports 1 and 3 located at the DDR3 memory.

62

7 Verication

(a) Physical setup of the measurement

DQ5port 1 port 2

DQ7port 3 port 4

(b) Schematic setup of the s-parameter

measurement

Figure 7.3: DDR3 s-parameter measurement setup and schematic

The measured s-parameters are depicted in gure 7.4, with the parameters of

interest for the far end crosstalk being the S14 and S23 s-parameters. The mea-

surement of the multi port s-parameters is conducted according to [57]. The

frequencies analysed within the measurement range from 300 kHz to 3 GHz, de-

ned by the utilised measuring device. The lowest crosstalk suppression rates

−28 dB for a frequency of 1.05 MHz.

The simulation results with the lowest crosstalk parameter of −40 dB are not

precisely reproduced. Calculating the resulting crosstalk percentage according

to equation 7.1 yields 3.98 %. The required 5 % required as maximum crosstalk

between the channels DQ5 and DQ7 is thereby met. Taking the setup of the mea-

surement into account in regards to the soldered SMA cables, the result seems

reasonable.

FEXT = 10−27 dB

20 = 3.98 % (7.1)

The forward transmission coecients show a maximum admission of −10 dB

for the S32 parameter at 2.5 GHz. The simulated maximum admission however

rates −3 dB. A possible reason could be the SMA cables used. Therefore the

cables used for the measurement are soldered together and the transmission co-

ecients are measured directly and plotted in gure 7.4 as a dotted line showing

a maximum dampening of 5 dB.

63

7 Verication

10-3 10-2 10-1 100

Frequency in GHz

-70

-60

-50

-40

-30

-20

-10

0M

agni

tude

in d

BDQ5 DQ7 S-Parameter Measurement

S21S43S32S14Ref

Figure 7.4: Far end crosstalk measurement between data lines DQ5 and DQ7

As the DDR3 interface cannot be tested via software at the point of the comple-

tion of the thesis, the correct function of the interface cannot be veried, however

the conducted measurements verify the qualitative plausibility of the simulation.

7.5 Low-speed interfaces

The unit tests and integration tests of the low-speed interfaces are conducted

according to the test plan document generated during the system design phase.

The populated PCB used to verify the interfaces is shown in gure 7.5.

64

7 Verication

Figure 7.5: Resulting PCB used for the verication

The chronological order of system element verications executed is listed in the

following, with all results recorded in the test plan, Appendix A.1.5:

• USB Interface: Verify the conguration of the FT2232H chip and test the

bidirectional data transfer between the FPGA and a computer with an

example program, Appendix A.1.8.

65

7 Verication

• SSI interface: Verify the correct conversion of the dierential clock input

to a TTL output signal and measure the dierential output of the data

channel at the maximum specied frequency of 2 MHz.

• Photo sensors: External 24 V signals are applied to the input of the photo

sensor circuitry and the output voltage of the circuitry is measured and

compared to the specied output.

• Temperature sensor: The verication is conducted by reading a temperature

value via SPI from the mounted temperature sensor chip and comparing the

read value to the measurement of a suitable thermometer.

66

8 Conclusions

The aim of this project was the development of a hardware platform to evaluate

advanced spatial lter algorithms, which was achieved during the project. The

project included the requirements engineering of the complete system, the

elaboration of hardware specic requirements, the assessment of a suited system

architecture as well as the implementation and validation of a custom hardware

prototype.

Verifying theoretical calculations using simulations in an early stage of the

implementation phase, relying on a milestone-based project schedule as well as

the post layout simulation loop led to the veried custom electronics hardware

board usable for its main purpose.

Even though the majority of the test specied in verication were successful,

the correct function of the high speed interfaces was not veried, as the

complete verication was optionally agreed upon (Appendix A.1.1). The correct

function can only be estimated through the simulation results and s-parameter

measurements. The nal verication must be conducted in a future software

based project by frame error rate testing [19].

With the necessary functionality for the hardware prototype veried, the en-

hancement of spatial lter algorithms can be conducted. For a future hardware

project combining DSP, FPGA and peripherals into a single PCB, the selected

board stackup can be used. Furthermore the PDN analysis for the DSP can be

conducted analogue to the described analysis. Furthermore, if the attached im-

provement list, Appendix A.2, is taken into consideration, the design risk of the

combined hardware development can be minimised.

67

List of Figures

1.1 Spatial lter signal of a single particle [3] . . . . . . . . . . . . . . 2

2.1 Schematic circuit structure of LVDS physical layer . . . . . . . . . 4

2.2 Equivalent circuit of a real capacitor . . . . . . . . . . . . . . . . 5

2.3 Simulated Impedances of 0402 and 1206 Ceramic Capacitors . . . 6

2.4 Inductance estimation of spaced vias . . . . . . . . . . . . . . . . 7

2.5 Schematic transmission line characteristics for a conductor section

∆z, [14] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.6 Transmission Line Geometry [15, 16] . . . . . . . . . . . . . . . . 10

2.7 Transformation of 4-pole network with currents and voltages to

2-port wave network . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.8 Example timing diagram, showing jitter and skew . . . . . . . . . 13

2.9 Typical eye-diagram [17] . . . . . . . . . . . . . . . . . . . . . . . 14

3.1 Derived environment-model for the VADER-system . . . . . . . . 16

4.1 Proposed system architecture VADER . . . . . . . . . . . . . . . 17

4.2 Block diagram of information ow of the spatial lter velocimeter [3] 19

4.3 Camera Link cable conguration according to standard [30] . . . . 25

4.4 Chosen 66AK2Gx DSP development board from TI . . . . . . . . 26

4.5 Proposed system architecture of the FPGA board . . . . . . . . . 27

5.1 Implemented power-supply scheme . . . . . . . . . . . . . . . . . 30

5.2 Power supply start-up timing diagram . . . . . . . . . . . . . . . 31

5.3 Schematic of the LTC3636 dual buck converter . . . . . . . . . . . 32

5.4 Schematic of the FPGA conguration circuit . . . . . . . . . . . . 34

5.5 Schematic section decoupling capacitors FPGA VCCINT and VC-

CAUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.6 Schematic section of the DDR3 memory device . . . . . . . . . . . 36

I

List of Figures

5.7 Schematic section of the Camera Link base receiver circuit . . . . 37

5.8 Comparison of two dierent eight-layer stackups [48] . . . . . . . 40

5.9 Layer stackup exported from the Altium Designer project . . . . . 41

5.10 Implemented PWR-plane, showing net polygons as well as placed

decoupling capacitors . . . . . . . . . . . . . . . . . . . . . . . . 43

5.11 Simulated impedance of the 1V0 PDN . . . . . . . . . . . . . . . . 45

5.12 Implemented data traces (green) and address traces (purple) be-

tween DDR3 memory chip U1 and FPGA U2 . . . . . . . . . . . . 46

5.13 PCB section of the Camera Link base group . . . . . . . . . . . . 47

5.14 Resulting PCB highlighting signal traces on signal layers . . . . . . 48

6.1 Port description of the crosstalk measurement . . . . . . . . . . . 50

6.2 Image of tested DDR3 Data Lines DQ5 and DQ7 on Signal Layer 2 50

6.3 Simulated s-parameters of DQ5 to DQ7 data lines, with spacings

of 100 µm, 150 µm and 170 µm . . . . . . . . . . . . . . . . . . . 51

6.4 Denition of overshoot amplitude and area for DDR3L clock and

data pins [38] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

6.5 Simulated Eye Diagram DQ7, period: 625 ps, rise and fall time:

60 ps, amplitude: 1.35 V . . . . . . . . . . . . . . . . . . . . . . . 53

6.6 Analysed SATA traces, SATA_RX2 . . . . . . . . . . . . . . . . . 53

6.7 Optimisation of the FPGA fanout for the dierential SATA traces 54

6.8 Simulated s-parameters of the Sata Rx Channel 2 Port comparing

pre and post optimisation results . . . . . . . . . . . . . . . . . . 55

6.9 Simulated eye diagram using SATA 3 Gbit s−1 standard signal setup 56

6.10 Comparison of Camera Link channel X1 pre and post optimisation 56

6.11 S-parameter simulation of LVDS channel X1 with 100 Ω termination 57

6.12 Simulated eye diagram LVDS channel X1 . . . . . . . . . . . . . . 58

7.1 Veried power supply start-up sequence of the FPGA board . . . 60

7.2 Generated test pattern image created by the Dalsa Spyder3 camera 62

7.3 DDR3 s-parameter measurement setup and schematic . . . . . . . 63

7.4 Far end crosstalk measurement between data lines DQ5 and DQ7 64

7.5 Resulting PCB used for the verication . . . . . . . . . . . . . . . 65

II

List of Tables

4.1 CBA to elicit suiting FPGA series for the VADER project . . . . . . 20

4.2 CBA comparing the TMS320C6655 to the 66AK2G12 [23, 24] . . . 22

4.3 Data storage interface benchmark . . . . . . . . . . . . . . . . . . 23

4.4 Camera Interface Benchmark [30, 29] . . . . . . . . . . . . . . . . 24

5.1 Current estimation for power supplies, detailed in Appendix A.1.6 29

5.2 Physical layer specication of high speed interfaces [8, 43, 44, 45] 38

5.3 Trace dimensions for critical interfaces per layer . . . . . . . . . . 42

7.1 Voltage measurements of power rails for open circuit and 20 %

FPGA usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

III

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A Appendix

A.1 Data-CD

1 Documents\Projektauftrag_VADER_BRD.pdf

2 Documents\Lastenheft_SFV_V1.0_freigegeben.pdf

3 Documents\Anforderungen_Spannungsebenen.pdf

4 Documents\Meilensteinplan_VADER.pdf

5 Documents\Testplan.xls

6 Calculations\Powersupply\

7 Calculations\Implementation \

8 Verication\Hello_World\

9 Verication\Cameralink \

10 Simulation\PDN\

11 Datenblätter\

12 AltiumProject \

13 Masterthesis\Masterthesis_Dalton

14 Schematic \VADER_FPGA_Schematic.pdf

15 Documents \AnordnungFPGA_BRD.pdf

XI

A Appendix

A.2 Errata

1. 100 Ω series resistor in McASP traces must be increased to 330 Ω for the

rst prototype

2. Camera Link connector BOM order number must be changed to 517-10226-

6212PL

3. BOM order number of DS90LV047 has to be changed to correct footprint

part

4. Footprint of NUM60 digital-transistor must be updated

5. FTDI JTAG connection must have 0 Ω resistors in series

6. With SMD PCB assembly only, Micro-USB connector has no mechanical

attachment and must be soldered by hand

7. SPI Flash should be changed to an Artix-7 Vivado compatible manufacturer

device

8. GND test points should be added next to system elements circuits

A.3 Schematic

XII

A Appendix

11

22

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_LTC

3636

BU

CK

_LTC

3636

.Sch

Doc

PG_1

V0_

GTP

PG_1

V2_

GTP

PG_D

DR

3_1V

35PG

_1V

8

PG_5

V0

PG_3

V3

PG_1

V0

MA

STER

_RES

ET

Vol

tage

_Mon

itor

Vol

tage

_Mon

itor.S

chD

oc

JTA

G_T

DI

JTA

G_T

DO

JTA

G_T

CK

JTA

G_T

MS

MA

STER

_RES

ET

INP_

BIN

P_A

SSI_

CLK

SSI_

DTA

INC

_BM

ON

_IN

CIN

C_A

DIN

_SD

E_S

RO

UT_

SR

E_S

ENC

RX

CLK

_B

RX

CLK

_M

RX

OU

T_B

_[0.

.27]

RX

OU

T_M

_[0.

.27]

FTD

I_O

E

FTD

I_R

XF

FTD

I_TX

EFT

DI_

WR

FTD

I_R

DFT

DI_

SIW

UA

FTD

I_D

[0..7

]

LD[1

..4]

TEM

P_SC

TEM

P_C

STE

MP_

SO

TEM

P_SI

AN

Y_G

IP1

AN

Y_T

XA

NY

_OM

1A

NY

_RES

ETA

NY

_MI0

AN

Y_G

OP1

AN

Y_M

I1A

NY

_IR

QA

NY

_GO

P0A

NY

_RW

AN

Y_O

EA

NY

_GIP

0A

NY

_OM

0A

NY

_OM

2A

NY

_LED

1AA

NY

_RX

AN

Y_L

ED2B

AN

Y_M

D0

AN

Y_C

EA

NY

_LED

2AA

NY

_LED

1B

MC

ASP

0AX

R[0

..15]

MC

ASP

1AX

R[0

..9]

MC

ASP

0AH

CLK

XM

CA

SP0A

CLK

RM

CA

SP0A

MU

TEM

CA

SP0F

SR

MC

ASP

0FSX

MC

ASP

0AC

LKX

MC

ASP

0AH

CLK

R

MC

ASP

1AC

LKX

MC

ASP

1FSR

MC

ASP

1AC

LKR

MC

ASP

1FSX

MC

ASP

1AM

UTE

_RM

CA

SP1A

HC

LKR

SPI2

_CLK

SPI2

_SC

S0SP

I2_M

ISO

SPI2

_MO

SIR

ESET

STA

T

DIN

C[1

..4]

FPG

A_A

LLFP

GA

_ALL

.Sch

Doc

JTA

G_T

MS

JTA

G_T

DI

JTA

G_T

CK

JTA

G_T

DO

FTD

I_R

XF

FTD

I_TX

E

FTD

I_R

DFT

DI_

WR

FTD

I_SI

WU

AFT

DI_

D[0

..7]

FTD

I_O

E

USB

_IN

TER

FAC

EU

SB_I

NTE

RFA

CE.

SchD

oc

INP_

BIN

P_A

SEN

SOR

_IN

PUT

SEN

SOR

_IN

PUT.

SchD

oc

SSI_

CLK

SSI_

DTA

SSI

SSI.S

chD

oc

INC

_BM

ON

_IN

CIN

C_A

INC

REM

ENTA

LIN

CR

EMEN

TAL.

SchD

oc

TEM

P_SC

TEM

P_SI

TEM

P_C

STE

MP_

SO

LD[1

..4]

LED

_DEB

UG

LED

_DEB

UG

.Sch

Doc

Mec

hani

cal

Mec

hani

cal.S

chD

oc

RX

OU

T_M

_[0.

.27]

RX

OU

T_B

_[0.

.27]

LD[1

..4]

FTD

I_D

[0..7

]NL

FTDI

0D00

0070

NL

FTDI

0D00

0070

NL

FTDI

0D00

0070

NL

FTDI

0D00

0070

NL

FTDI

0D00

0070

NL

FTDI

0D00

0070

NL

FTDI

0D00

0070

NL

FTDI

0D00

0070

NLLD010040

NLLD010040

NLLD010040

NLLD010040

NLRXOUT0B00000270

NLRXOUT0B00000270

NLRXOUT0B00000270

NLRXOUT0B00000270

NLRXOUT0B00000270

NLRXOUT0B00000270

NLRXOUT0B00000270

NLRXOUT0B00000270

NLRXOUT0B00000270

NLRXOUT0B00000270

NLRXOUT0B00000270

NLRXOUT0B00000270

NLRXOUT0B00000270

NLRXOUT0B00000270

NLRXOUT0B00000270

NLRXOUT0B00000270

NLRXOUT0B00000270

NLRXOUT0B00000270

NLRXOUT0B00000270

NLRXOUT0B00000270

NLRXOUT0B00000270

NLRXOUT0B00000270

NLRXOUT0B00000270

NLRXOUT0B00000270

NLRXOUT0B00000270

NLRXOUT0B00000270

NLRXOUT0B00000270

NLRXOUT0B00000270

NLRX

OUT0

M000

0027

0 NL

RXOU

T0M0

0000

270

NLRX

OUT0

M000

0027

0 NL

RXOU

T0M0

0000

270

NLRX

OUT0

M000

0027

0 NL

RXOU

T0M0

0000

270

NLRX

OUT0

M000

0027

0 NL

RXOU

T0M0

0000

270

NLRX

OUT0

M000

0027

0 NL

RXOU

T0M0

0000

270

NLRX

OUT0

M000

0027

0 NL

RXOU

T0M0

0000

270

NLRX

OUT0

M000

0027

0 NL

RXOU

T0M0

0000

270

NLRX

OUT0

M000

0027

0 NL

RXOU

T0M0

0000

270

NLRX

OUT0

M000

0027

0 NL

RXOU

T0M0

0000

270

NLRX

OUT0

M000

0027

0 NL

RXOU

T0M0

0000

270

NLRX

OUT0

M000

0027

0 NL

RXOU

T0M0

0000

270

NLRX

OUT0

M000

0027

0 NL

RXOU

T0M0

0000

270

NLRX

OUT0

M000

0027

0 NL

RXOU

T0M0

0000

270

NLRX

OUT0

M000

0027

0 NL

RXOU

T0M0

0000

270

XIII

A Appendix

11

22

33

44

DD

CC

BB

AA

Tite

l:

Dat

um:

Seite

Entw

ickl

erkü

rzel

:Em

il-Fi

gge-

Straße

85,

442

27 D

ortm

und

BUC

K_TP

S821

40.S

chD

oc

03.0

9.20

18

2

SeD

a

BU

CK

_TP

S82

140.

Sch

Doc

Adre

sse:

Zeit:

13:4

6:48

von

23Ve

rsio

n:

Proj

ekt:

VAD

ER_F

RG

A.Pr

jPcb

v1.0

C22

10u

GN

D

GN

D

GN

DG

ND

R14

100k

GN

D

C23

22u

GN

D

R15

n.b.

1V8

12V

0

PG_1

V8

R13

124k

C25

10u

GN

D

GN

D

GN

DG

ND

R18

100k

R17

68k

GN

D

C26

22u

GN

D

R19

n.b.

1V35

PG_D

DR

3_1V

35

C28

10u

GN

D

GN

D

GN

DG

ND

GN

D

C29

22u

GN

D

R23

n.b.

5V0

PG_5

V0

C24

6n2

C27

27n

C30

15n

7.5

ms

ENVIN

GND

VO

UT

VO

UT

FB PGSS

/TR

PAD

IC2

TPS8

2140

ENVIN

GND

VO

UT

VO

UT

FB PGSS

/TR

PAD

IC3

TPS8

2140

ENVIN

GND

VO

UT

VO

UT

FB PGSS

/TR

PAD

IC4

TPS8

2140

Supp

ly 1

V8

Supp

ly 5

V0

Supp

ly D

DR

3 1V

35

1 2

J8 1036

69-1 G

ND

Inpu

t Pro

tect

ion

G

S

D

T6

FQD

17P0

6R

139

100k

D19

SM6T

36C

A

GN

DG

ND

12V

0

13.5

ms

3.1

ms

TP23

TP25

TP27

TP24

TP26

TP28

R4

100k

NT5

NET

TIE

NT7

NET

TIE

NT6

NET

TIE

NT4

NET

TIE

NT9

NET

TIE

NT8

NET

TIE

R5

19k1

12V

0

12V

0

PIC2201

PIC2202 CO

C22

PIC2301 PIC2302 COC2

3

PIC2401 PIC2402 CO

C24


PIC2601 PIC2602 CO

C26

PIC2701 PIC2702 CO

C27


PIC2901 PIC2902 CO

C29

PIC3001 PIC3002 CO

C30

PID1901 PID1902 CO

D19

PIIC201

PIIC202

PIIC203

PIIC204

PIIC205

PIIC206

PIIC207

PIIC208

PIIC209

COIC2

PIIC301

PIIC302

PIIC303

PIIC304

PIIC305

PIIC306

PIIC307

PIIC308

PIIC309

COIC

3

PIIC401

PIIC402

PIIC403

PIIC404

PIIC405

PIIC406

PIIC407

PIIC408

PIIC409

COIC

4

PIJ8

01

PIJ8

02

COJ8

PINT401

PINT402

CONT4

PINT501

PINT502

CONT5

PINT601

PINT602

CONT6

PINT701

PINT702

CONT7

PINT801

PINT802

CONT8

PINT901

PINT902

CONT9

PIR401 PIR402 COR

4

PIR501 PIR502 COR

5

PIR1301 PIR1302 CO

R13

PIR1401 PIR1402 CO

R14

PIR1501 PIR1502 CO

R15

PIR1701 PIR1702 COR1

7


8

PIR1901 PIR1902 CO

R19


3

PIR13901 PIR13902 COR139

PIT601

PIT602

PIT

603

COT6

PITP2300 COTP

23

PITP2400 COTP

24

PITP2500 COTP

25

PITP2600 COTP26

PITP2700 COTP27

PITP2800 COTP

28

PINT502

PINT702

PINT902

PINT401

PINT601

PINT801

PIT603

PIC2202

PIC2302

PIC2402

PIC2502 PIC2602

PIC2702

PIC2802 PIC2902

PIC3002

PID1901

PIIC203 PIIC209

PIIC303 PIIC309

PIIC403 PIIC409

PIJ8

02

PIR501

PIR1401

PIR1801

PIR13901

PIC2201

PIIC201

PIIC202

PINT402

PIC2301 PIIC204

PIIC205

PINT501

PIR1302

PIR1502

PITP2300

PIC2401 PIIC208

PIC2501

PIIC301

PIIC302

PINT602

PIC2601 PIIC304

PIIC305

PINT701

PIR1702

PIR1902

PITP2500

PIC2701 PIIC308

PIC2801

PIIC401

PIIC402

PINT802

PIC2901

PIIC404

PIIC405

PINT901

PIR402

PIR2302

PITP2700

PIC3001

PIIC408

PID1902 PI

J801

PIT

602

PIIC206

PIR1301 PIR1402 PITP24

00

PIIC207

PIR1501 POPG01V8

PIIC306


00

PIIC307

PIR1901 POPG0DDR301V35

PIIC406


00

PIIC407

PIR2301 POPG05V0

PIR13902 PIT601

POPG01V8

POPG05V0

POPG0DDR301V35

XIV

A Appendix

11

22

33

44

DD

CC

BB

AA

Tite

l:

Dat

um:

Seite

Entw

ickl

erkü

rzel

:Em

il-Fi

gge-

Straße

85,

442

27 D

ortm

und

BUC

K_LT

C36

36.S

chD

oc

03.0

9.20

18

3

SeD

a

BU

CK

_LTC

3636

.Sch

Doc

Adre

sse:

Zeit:

13:4

6:48

von

23Ve

rsio

n:

Proj

ekt:

VAD

ER_F

RG

A.Pr

jPcb

v1.0

ITH

11

RU

N1

2

MO

DE/

SYN

C3

RT

4

INTV

CC

5TM

ON

6

RU

N2

7

ITH

28

VFB

29

PGO

OD

210

TRA

CK

SS2

11

GND 12

SW2

13

BO

OST

214

VIN215 VIN216

SW2

17

GND 18

GND 19

SW1

20

VIN121 VIN122

BO

OST

123

SW1

24

GND 25

TRA

CK

SS1

26

PGO

OD

127

VFB

128

INTV

CC

29

GNDT 30

GNDT 31

GNDT 32

SW1T

33SW

2T34

IC1

LTC

3636

GN

D

C20

10n

C21

2n7

GN

DG

ND

R10

n.b.

R11

n.b.

R7

9k1

R6

62k

R8

13k7

R9

13k7

C8

100n

C9

100n

R2

10k5

R3

12k

C15

22p

C16

22p

GN

DG

ND

C17

100n

C14

100n

C12

100n

C19

100n

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

L2 1u

L1 1u5

R1

162k

GN

D

C6

220p

C7

220p

C4

10p

C5

10p

GN

DG

ND

GN

D

3V3

1V0

GN

DG

ND

12V

0

PG_3

V3

PG_1

V0

C1

47u

C2

47u

C13

47u

C18

47u

C10

100u

C11

100u

Supp

ly 3

V3

1V0

C3

4u7

4.3

ms

1.1

ms

TP13

TP20

TP22

TP21

NT1

NET

TIE

NT2

NET

TIE

NT3

NET

TIE

PIC101 PIC102 COC

1 PIC201 PIC202

COC2

PIC301

PIC302 COC

3

PIC401 PIC402 COC

4 PIC501

PIC502

COC5

PIC601 PIC602 CO

C6

PIC701 PIC702 COC

7 PIC801

PIC802

COC8

PIC901 PIC902 COC

9


PIC1101 PIC1102 CO

C11

PIC1201

PIC1202 CO

C12

PIC1301 PIC1302 CO

C13

PIC1401

PIC1402 CO

C14


PIC1601 PIC1602 CO

C16

PIC1701

PIC1702 CO

C17

PIC1801 PIC1802 CO

C18

PIC1901

PIC1902 CO

C19


0 PIC2101 PIC2102

COC2

1

PIIC101

PIIC102

PIIC103

PIIC104

PIIC105

PIIC106

PIIC107

PIIC108

PIIC109

PIIC1010

PIIC1011

PIIC1012

PIIC1013

PIIC1014

PIIC1015 PIIC1016

PIIC1017

PIIC1018 PIIC1019

PIIC1020

PIIC1021 PIIC1022

PIIC1023

PIIC1024

PIIC1025

PIIC1026

PIIC1027

PIIC1028

PIIC1029

PIIC1030 PIIC1031 PI

IC1032

PIIC1033

PIIC1034 CO

IC1

PIL1

01

PIL1

02

COL1

PI

L201

PI

L202

COL2

PINT101

PINT102

CONT1

PINT201

PINT202

CONT2

PINT301

PINT302

CONT3

PIR101 PIR102 COR

1

PIR201 PIR202 COR2

PIR301 PIR302 COR

3

PIR601 PIR602 COR6

PIR701 PIR702 CO

R7

PIR801 PIR802 COR8

PIR901 PIR902 COR

9


PIR1101 PIR1102 CO

R11

PITP1300 COTP

13

PITP2000 COTP

20

PITP2100 COTP

21

PITP2200 COTP

22

PIC1901

PINT302

PIC1201

PINT201

PINT101

PIC102 PIC202

PIC302

PIC402 PIC502

PIC602 PIC702

PIC1002 PIC1102

PIC1202

PIC1302 PIC140

2 PIC170

2 PIC1802

PIC1902

PIC2002 PIC2102

PIIC1012 PIIC1018

PIIC1019 PIIC1025 PIIC1030

PIIC1031 PIIC1032

PIR101

PIR801 PIR901

PIC101 PIC201

PIIC102

PIIC107

PIIC1015 PIIC1016 PIIC1021 PIIC1022 PINT102

PIC301

PIIC103

PIIC105

PIIC1029

PIC401 PIIC101

PIR202 PIC501

PIIC108

PIR302

PIC601 PIR201 PIC701 PIR301

PIC801

PIIC1023

PIC802

PIIC1020

PIIC1024

PIIC1033

PIL1

02

PIC901

PIIC1014

PIC902

PIIC1013

PIIC1017

PIIC1034

PIL2

01

PIC1001 PIC1301

PIC1401

PIC1502

PIL1

01

PINT202

PIR602

PIR1002

PITP1300

PIC1101 PIC1602

PIC1701

PIC1801

PIL2

02

PINT301

PIR702

PIR1102

PITP2000

PIC1501 PIIC1028


00

PIC1601 PIIC109


00

PIC2001 PIIC1026

PIC2101 PIIC1011

PIIC104

PIR102 PIIC106

PIIC1010

PIR1101 POPG01V0

PIIC1027

PIR1001 POPG03V3

POPG01V0

POPG03V3

XV

A Appendix

11

22

33

44

DD

CC

BB

AA

Tite

l:

Dat

um:

Seite

Entw

ickl

erkü

rzel

:Em

il-Fi

gge-

Straße

85,

442

27 D

ortm

und

LDO

_GTP

.Sch

Doc

03.0

9.20

18

4

SeD

a

LDO

_GTP

.Sch

Doc

Adre

sse:

Zeit:

13:4

6:48

von

23Ve

rsio

n:

Proj

ekt:

VAD

ER_F

RG

A.Pr

jPcb

v1.0

OU

T1

NC2

NC3

NC4

IN5

IN6

IN7

IN8

PG9

BIA

S10

EN11

GND 12NC13

NC14

SS15

FB16

NC17

OU

T18

OU

T19

OU

T20

GND 21

IC9

TPS7

4401

C49

1u5

C51

1u5

GN

D

GN

D

GN

D

GN

D

GN

DR

53n.

b.

C50

10u

GN

D

1V8

5V0

PG_1

V0_

GTP

R50

1k13

R51

4k53

OU

T1

NC2

NC3

NC4

IN5

IN6

IN7

IN8

PG9

BIA

S10

EN11

GND 12NC13

NC14

SS15

FB16

NC17

OU

T18

OU

T19

OU

T20

GND 21

IC10

TPS7

4401

C53

1u5

C55

1u5

GN

D

GN

D

GN

D

GN

D

GN

DR

58n.

b.

C54

10u

GN

D

1V8

5V0

PG_1

V2_

GTP

R56

2k49

R57

4k99

V(E

N)m

ax =

6V

LDO

_EN

R52

0R R54

0R

1V2_

GTP

1V0_

GTP

Trac

k 5V

0

2ms +

7ms

4ms +

7ms

C52

2n0

C56

3n9

TP1

TP3

TP2

10K

Pul

lup@

Vol

tage

mon

itor

GN

D

GN

D

1V8

1V8

EN_L

DO

_1V

0

EN_L

DO

_1V

2

EN_L

DO

_1V

2

EN_L

DO

_1V

0LD

O E

nabl

e

LDO

1V

0_G

TP

LDO

1V

2_G

TP

TP29

TP30

NT1

1

NET

TIE

NT1

0

NET

TIE

PIC4901 PIC4902 CO

C49


0

PIC5101

PIC5102 CO

C51

PIC5201 PIC5202 CO

C52

PIC5301

PIC5302 CO

C53


4

PIC5501

PIC5502 CO

C55

PIC5601 PIC5602 CO

C56

PIIC901


4 PIIC905

PIIC906

PIIC907

PIIC908

PIIC909

PIIC9010

PIIC9011


PIIC9015

PIIC9016

PIIC9017 PIIC9018

PIIC9019

PIIC9020

PIIC9021

COIC

9

PIIC1001


04 PIIC1005

PIIC1006

PIIC1007

PIIC1008

PIIC1009

PIIC10010

PIIC10011


PIIC10015

PIIC10016

PIIC10017 PIIC10018

PIIC10019

PIIC10020

PIIC10021

COIC10

PINT

1001

PI

NT10

02

CONT10

PINT

1101

PI

NT11

02

CONT11


0


1

PIR5201

PIR5202 COR52

PIR5301 PIR5302 CO

R53

PIR5401

PIR5402 COR54


6


7

PIR5801 PIR5802 CO

R58

PITP100 COTP

1

PITP200 COTP

2

PITP300 COTP

3

PITP2900 COTP

29

PITP3000 COTP

30

PINT

1002

PINT

1102

PIC4901

PIC5301

PIIC905

PIIC906

PIIC907

PIIC908

PIIC1005

PIIC1006

PIIC1007

PIIC1008

PIR5302 PIR5802

PIC5101

PIC5501

PIIC9010

PIIC10010

PIIC9011

PIR5201

NLEN0LDO01V0 PI

IC10011

PIR5401

NLEN0LDO01V2

PIC4902

PIC5002

PIC5102

PIC5202

PIC5302

PIC5402

PIC5502

PIC5602


4 PIIC9012 PIIC9013 PIIC9014 PIIC9021


04 PIIC10012 PIIC10013 PIIC10014 PIIC10021

PIR5101 PIR5701

PIC5001 PIIC901

PIIC9018

PIIC9019

PIIC9020

PINT

1001

PIR5002

PITP100

PIC5201 PIIC9015

PIC5401 PIIC1001

PIIC10018

PIIC10019

PIIC10020

PINT

1101

PIR5602

PITP300

PIC5601 PIIC10015

PIIC909

PIR5301 POPG01V00GTP

PIIC9016


00

PIIC9017

PIIC1009

PIR5801 POPG01V20GTP

PIIC10016


00

PIIC10017

PIR5202

PIR5402

PITP200 POLDO0EN

POLDO0EN

POPG01V00GTP

POPG01V20GTP

XVI

A Appendix

11

22

33

44

DD

CC

BB

AA

Tite

l:

Dat

um:

Seite

Entw

ickl

erkü

rzel

:Em

il-Fi

gge-

Straße

85,

442

27 D

ortm

und

Volta

ge_M

onito

r.Sch

Doc

03.0

9.20

18

5

SeD

a

Vol

tage

_Mon

itor.S

chD

oc

Adre

sse:

Zeit:

13:4

6:48

von

23Ve

rsio

n:

Proj

ekt:

VAD

ER_F

RG

A.Pr

jPcb

v1.0

UV

1

GND 2

SEN

SE3

SET

4

VDD5

OV

6

IC13

TPS3

702C

X10

DD

CT

C77

10n

GN

D

GN

D

C76

100n

3V3

GN

DR

7810

k

R79

0R

3V3

MA

STER

_RES

ET

5% A

ccur

acy

PG_1

V2_

GTP

PG_D

DR

3_1V

35

PG_1

V0_

GTP

PG_1

V8

PG_5

V0

PG_3

V3

PG_1

V0

R80

0RR

82

0RR

84

0RR

85

0RR

86

0RR

87

0RR

88

n.b.

R83

n.b.

GN

D

TP5

1V0

R34

0R

D16

LTST

-S27

0KR

KT

R35

300R

3V3

GN

D

TP4W

indo

w_1

V0

Win

dow

_1V

0

Win

dow

Wat

chdo

gPG

Mux

B

ECT5 B

C81

7

NT1

2

NET

TIE

NT1

3N

ET T

IE


6

PIC7701 PIC7702 COC

77

PID1601

PID1602 COD16

PIIC1301

PIIC1302

PIIC1303

PIIC1304

PIIC1305 PIIC1306

COIC13

PINT

1201

PI

NT12

02

CONT12

PINT1301 PINT1302 CONT13

PIR3401

PIR3402

COR3

4 PIR3501 PIR3502 CO

R35


8

PIR7901

PIR7902

COR79

PIR8001

PIR8002

COR8

0

PIR8201

PIR8202

COR82


PIR8401

PIR8402

COR8

4

PIR8501

PIR8502

COR85

PIR8601

PIR8602

COR8

6

PIR8701

PIR8702

COR87

PIR8801

PIR8802

COR8

8

PIT5

01

PIT502 PIT503

COT5

PITP400 COTP

4 PITP500 COTP

5 PI

NT12

01

PIC7601

PIIC1305

PIR3502

PIR7802 PIC7602

PIC7702

PIIC1302

PIR8301

PIT502

PIC7701 PIIC1303

PINT

1202

PINT1302

PID1601 PIR3501 PID1602 PIT503

PIIC1304

PINT1301 PIR8302

PIR3401

PIR7801 PIR7902

PIR8002

PIR8202

PIR8402

PIR8502

PIR8602

PIR8702

PIR8802

PIT5

01

PITP500 PIR3402 POMASTER0RESET

PIR8001

POPG03V3

PIR8201

POPG05V0

PIR8401

POPG01V8

PIR8501

POPG01V00GTP

PIR8601

POPG0DDR301V35

PIR8701

POPG01V20GTP

PIR8801

POPG01V0

PIIC1301

PIIC1306

PIR7901

PITP400 NL

Wind

ow01

V0

POMASTER0RESET

POPG01V0

POPG01V00GTP

POPG01V20GTP

POPG01V8

POPG03V3

POPG05V0

POPG0DDR301V35

XVII

A Appendix

11

22

33

44

DD

CC

BB

AA

Tite

l:

Dat

um:

Seite

Entw

ickl

erkü

rzel

:Em

il-Fi

gge-

Straße

85,

442

27 D

ortm

und

AnyB

us.S

chD

oc

03.0

9.20

18

6

SeD

a

Any

Bus

.Sch

Doc

Adre

sse:

Zeit:

13:4

6:48

von

23Ve

rsio

n:

Proj

ekt:

VAD

ER_F

RG

A.Pr

jPcb

v1.0

2

34

156

78

910

1112

1314

1516

1718

1920

212224

232526

J5 2x13

GN

D

GN

D

3V3

3V3

AN

Y_T

X

AN

Y_R

X

AN

Y_M

D0

AN

Y_L

ED1A

AN

Y_L

ED2A

AN

Y_L

ED2B

AN

Y_L

ED1B

AN

Y_T

X

AN

Y_M

I1

AN

Y_R

X

AN

Y_M

I0

AN

Y_O

M0

AN

Y_O

M1

AN

Y_O

M2

AN

Y_C

E

AN

Y_R

WA

NY

_IR

Q

AN

Y_O

EA

NY

_RES

ET

AN

Y_G

OP0

AN

Y_G

OP1

AN

Y_G

IP0

AN

Y_G

IP1

OM

[0..2

] Ope

ratio

nMod

e

MI[

0..1

] Mod

uleI

dent

ifica

tion

AN

Y_R

ESET

R69

4k7

AN

Y_R

ESET

C73

22u

C75

100n

C74

100n

AN

Y_M

I1A

NY

_MI0

GN

DA

NY

_MI0

AN

Y_M

I1

AN

Y_I

RQ

R73

4k7

AN

Y_I

RQ

3V3

AN

Y_T

X

AN

Y_R

X

GN

DG

ND

3V3

GN

D

GN

D

AN

Y_G

OP0

AN

Y_G

OP1

R74

4k7

R75

4k7

3V3

3V3

GO

P[0,

1] G

ener

al O

utpu

t Por

t

GP[

0,1]

Gen

eral

Inpu

t Por

t

AN

Y_G

OP0

AN

Y_G

OP1

R66

4k7

R67

4k7

3V3

3V3

AN

Y_C

EA

NY

_RW

AN

Y_O

E

AN

Y_C

EA

NY

_RW

AN

Y_O

E

AN

Y_G

IP0

AN

Y_G

IP1

R76

4k7

R77

4k7

GN

DG

ND

MD

0 M

odul

e D

etec

tion

AN

Y_G

IP0

AN

Y_G

IP1

AN

Y_L

ED1A

AN

Y_L

ED2A

AN

Y_L

ED2B

AN

Y_L

ED1B

AN

Y_O

M0

AN

Y_O

M1

AN

Y_O

M2

AN

Y_M

D0

R68

4k7

R70

4k7

R71

4k7

R72

4k7

3V3

GN

DG

ND

GN

D

AN

Y_M

D0

AN

Y_O

M0

AN

Y_O

M1

AN

Y_O

M2

AN

Y_L

ED1A

AN

Y_L

ED2A

AN

Y_L

ED1B

AN

Y_L

ED2B

Any

bus

Con

nect

orIn

terf

ace

R12

4k7

R16

4k7

R20

4k7

3V3

3V3

3V3

iA

nybu

si

Any

bus

PIC7301 PIC7302 CO

C73


4 PIC7501 PIC7502

COC75

PIJ5

01

PIJ5

02

PIJ5

03

PIJ5

04

PIJ5

05

PIJ5

06

PIJ5

07

PIJ5

08

PIJ5

09

PIJ5010

PIJ5011

PIJ5012

PIJ5013

PIJ5014

PIJ5015

PIJ5016

PIJ5017

PIJ5018

PIJ5019

PIJ5020

PIJ5021

PIJ5022

PIJ5023

PIJ5024

PIJ5025

PIJ5026 COJ

5


2

PIR1601 PIR1602 CO

R16


0

PIR6601 PIR6602 CO

R66

PIR6701 PIR6702 CO

R67

PIR6801 PIR6802 CO

R68

PIR6901 PIR6902 CO

R69


0

PIR7101 PIR7102 CO

R71


2

PIR7301 PIR7302 CO

R73

PIR7401 PIR7402 CO

R74


PIR7601 PIR7602 COR

76

PIR7701 PIR7702 CO

R77

PIC7301

PIC7401 PIC7501

PIJ5025

PIJ5026

PIR1202 PIR1602

PIR2002 PIR6602

PIR6702

PIR6802

PIR7302

PIR7402 PIR7502

PIJ5019

PIR1201 NLANY0CE

POANY0CE

PIJ5011

PIR7602

NLANY0GIP0

POANY0GIP0

PIJ5012

PIR7702

NLANY0GIP1

POANY0GIP1

PIJ5013

PIR7401 NL

ANY0

GOP0

POANY0GOP0

PIJ5014

PIR7501

NLAN

Y0GO

P1

POANY0GOP1

PIJ5017

PIR7301 NL

ANY0

IRQ

POANY0IRQ

PIJ5

08

NLAN

Y0LE

D1A

POANY0LED1A

PIJ5

07

NLAN

Y0LE

D1B

POANY0LED1B

PIJ5010

NLAN

Y0LE

D2A

POANY0LED2A

PIJ5

09

NLAN

Y0LE

D2B

POANY0LED2B

PIJ5

02

PIR6801 NLANY0MD0

POANY0MD0

PIJ5

04

NLAN

Y0MI

0 POANY0MI0

PIJ5

03

NLAN

Y0MI

1 POANY0MI1

PIJ5016

PIR2001

NLANY0OE

POANY0OE

PIJ5022

PIR7002

NLANY0OM0

POANY0OM0

PIJ5021

PIR7102

NLANY0OM1

POANY0OM1

PIJ5020

PIR7202

NLANY0OM2

POANY0OM2

PIJ5015

PIR6902 NL

ANY0

RESE

T POANY0RESET

PIJ5018

PIR1601 NL

ANY0

RW

POANY0RW

PIJ5

06

PIR6701

NLANY0RX

POANY0RX

PIJ5

05

PIR6601 NLANY0TX

POANY0TX

PIC7302

PIC7402 PIC7502

PIJ5

01

PIJ5023

PIJ5024

PIR6901

PIR7001 PIR7101

PIR7201

PIR7601 PIR7701

POANY0CE

POANY0GIP0

POANY0GIP1

POANY0GOP0

POANY0GOP1

POANY0IRQ

POANY0LED1A

POANY0LED1B

POANY0LED2A

POANY0LED2B

POANY0MD0

POANY0MI0

POANY0MI1

POANY0OE

POANY0OM0

POANY0OM1

POANY0OM2

POANY0RESET

POANY0RW

POANY0RX

POANY0TX

XVIII

A Appendix

11

22

33

44

DD

CC

BB

AA

Tite

l:

Dat

um:

Seite

Entw

ickl

erkü

rzel

:Em

il-Fi

gge-

Straße

85,

442

27 D

ortm

und

LED

_DEB

UG

.Sch

Doc

03.0

9.20

18

7

SeD

a

LED

_DE

BU

G.S

chD

oc

Adre

sse:

Zeit:

13:4

6:48

von

23Ve

rsio

n:

Proj

ekt:

VAD

ER_F

RG

A.Pr

jPcb

v1.0

D4

LTST

-S27

0KR

KT

R99

300R

D3

LTST

-S27

0KR

KT

R98

300R

D5

LTST

-S27

0KR

KT

R10

030

0R

D6

LTST

-S27

0KR

KT

R10

130

0R

GN

D

CS

1

GND 2

SI/O

3

SC4

VDD5

IC15

LM95

071

GN

D

3V3

GN

D

3V3 C

8710

0n

R10

4

100R

R10

5

100R

R10

3

100R

R10

210

k

3V3

TEM

P_C

S

TEM

P_SI

TEM

P_SC

1

2 3

T4 MU

N22

11

3V3

1

2 3

T1 MU

N22

11

GN

DG

ND

1

2 3

T2 MU

N22

11

3V3

3V3

1

2 3

T3 MU

N22

11

GN

D

3V3

LD1

LD2

LD3

LD4

R16

3

100R

R16

2

100R

R16

1

100R

R16

0

100R

LD1

LD2

LD3

LD4

3V3

GN

D

2 3 41 5 6

J7 1x6

TP7

TP8

TP6

R32

10k

TEM

P_SO

LD1

LD2

LD3

LD4

LD[1

..4]

LD[1

..4]

Tem

pera

ture

Sen

sor

Deb

ug H

eade

r

Deb

ug L

EDs

TP37

GN

D

PIC8701 PIC8702 CO

C87

PID301

PID302

COD3

PID40

1 PID402

COD4

PID50

1 PID502

COD5

PID6

01 PID602

COD6

PIIC1501

PIIC1502

PIIC1503

PIIC1504

PIIC1505 CO

IC15

PI

J701

PIJ7

02

PIJ7

03

PIJ7

04

PIJ7

05

PIJ7

06 COJ

7

PIR3201

PIR3202 COR32



9

PIR10001 PIR10002 CO

R100


R101


R102

PIR1

0301

PI

R103

02

COR1

03

PIR104

01 PIR

10402

COR1

04

PIR1

0501

PI

R105

02

COR1

05

PIR1

6001

PI

R160

02 COR1

60

PIR161

01 PIR

16102 CO

R161

PIR1

6201

PI

R162

02 COR1

62

PIR1

6301

PI

R163

02 COR1

63

PIT101

PIT102 PIT103

COT1

PIT201

PIT202 PIT203

COT2

PIT301

PIT302 PIT303

COT3

PIT401

PIT402 PIT403

COT4

PITP600 COTP6

PITP700 COTP

7 PITP800 COTP8

PITP

3700

COTP

37

PIC8701

PIIC1505 PI

J701

PIR9802 PIR9902

PIR10002 PIR10102

PIR10202

PIC8702

PIIC1502 PI

J706

PIT103 PIT203

PIT303 PIT403

PITP

3700





PIIC1501

PIR10201 PI

R103

02

PIIC1503

PIR104

02

PIIC1504

PIR1

0502

PIJ7

02

PIR1

6001

PIJ7

03

PIR161

01 PIJ7

04

PIR1

6201

PIJ7

05

PIR1

6301

PIR3201

PIR104

01 PITP700

POTEMP0SI PIR3202

POTEMP0SO

PIR1

0301

PITP600

POTEMP0CS

PIR1

0501

PITP800

POTEMP0SC

PIR1

6002

PIT401

NLLD010040

NLLD1

POLD010040

PIR161

02

PIT101

NLLD010040

NLLD2

POLD010040

PIR1

6202

PIT201

NLLD010040

NLLD3

POLD010040

PIR1

6302

PIT301

NLLD010040

NLLD4

POLD010040

POLD1

POLD2

POLD3

POLD4

POLD010040

POTEMP0CS

POTEMP0SC

POTEMP0SI

POTEMP0SO

XIX

A Appendix

11

22

33

44

DD

CC

BB

AA

Tite

l:

Dat

um:

Seite

Entw

ickl

erkü

rzel

:Em

il-Fi

gge-

Straße

85,

442

27 D

ortm

und

SEN

SOR

_IN

PUT.

SchD

oc

03.0

9.20

18

8

SeD

a

SE

NS

OR

_IN

PU

T.S

chD

oc

Adre

sse:

Zeit:

13:4

6:48

von

23Ve

rsio

n:

Proj

ekt:

VAD

ER_F

RG

A.Pr

jPcb

v1.0

1

23

D7

MM

BZ3

3VA

LT1G

GND 2

VCC5

IC16

AN

C7W

Z14

3V3

GN

D

C88

100n

3V3

GN

D

NC

1

A2

C3

NC

4G

ND

5V

o6

Ve

7V

cc8

IC17

HC

PL-0

600-

500E

INP_

GN

D

INP_

GN

D

D8

BA

V90

24V R

107

0R

R10

6n.

b.

INP_

_PN

P_A

R11

2

330R

A1

1Y

16

IC16

B

NC

7WZ1

4

R11

12k

2

3V3

C89

100n

GN

D

3V3

GN

D

INP_

A

INP_

NPN

_AR

110

0R

1

23

D9

MM

BZ3

3VA

LT1G

NC

1

A2

C3

NC

4G

ND

5V

o6

Ve

7V

cc8

IC19

HC

PL-0

600-

500E

INP_

GN

D

INP_

GN

D

D10

BA

V90

24V R

114

0R

R11

3n.

b.

INP_

_PN

P_B

R11

9

330R

A2

3Y

24

IC16

C

NC

7WZ1

4

R11

82k

2

3V3

C91

100n

GN

D

3V3

GN

D

INP_

B

INP_

NPN

_BR

117

0R

2 3 41 5 6 7 8

J10

1036

69-724

V

24VIN

P_N

PN_A

INP_

_PN

P_A

INP_

NPN

_B

INP_

_PN

P_B

INP_

GN

D

R10

84k

7

R11

64k

7R10

9

100R

R11

547

0R

INP_

GN

D

C23

310

0n

INP_

GN

D

R16

4

100R

R16

547

0RC

234

100n

INP_

GN

DIN

P_G

ND

TP10

TP9

TP18

TP17

Con

nect

or S

enso

rSe

nsor

Cha

nnel

A

Sens

ore

Cha

nnel

B

Inve

rter S

uppl

y

INP_

GN

D

TP33

TP34


8


9


1

PIC23301 PIC23302 CO

C233


C234

PID701 PID702

PID703

COD7

PID8

01

PID8

02

PID803

COD8

PID901 PID902

PID903

COD9

PID1001

PID1002

PID1003

COD10

PIIC1602 PIIC1605 CO

IC16

A

PIIC1601

PIIC1606

COIC

16B

PIIC1603

PIIC1604

COIC

16C

PIIC1701

PIIC1702

PIIC1703

PIIC1704

PIIC1705

PIIC1706

PIIC1707

PIIC1708

COIC17

PIIC1901

PIIC1902

PIIC1903

PIIC1904

PIIC1905

PIIC1906

PIIC1907

PIIC1908

COIC19

PIJ1001

PIJ1002

PIJ1003

PIJ1004

PIJ1005

PIJ1006

PIJ1007

PIJ1008

COJ10


R106


R107


R108

PIR1

0901

PIR10902

COR1

09

PIR1

1001

PI

R110

02 COR1

10


R111

PIR112

01 PIR

11202

COR1

12


R113


R114

PIR11501 PIR11502

COR1

15


R116

PIR1

1701

PI

R117

02 COR1

17


R118

PIR1

1901

PI

R119

02

COR1

19

PIR1

6401

PIR16402

COR1

64

PIR16501 PIR16502

COR1

65

PITP900 COTP

9

PITP1000 COTP

10

PITP1700 COTP

17

PITP1800 COTP

18

PITP3300 COTP

33

PITP3400 COTP

34

PIC8801

PIC8901 PIC9101

PIIC1605

PIIC1708

PIIC1908

PIR11102 PIR11802

PIJ1001

PIJ1005

PIR10702 PIR11402

PIC8802

PIC8902 PIC9102

PIIC1602

PIIC1705

PIIC1905

PID702 PIJ1003

PIR10602 NLIN

P00P

NP0A

PID902 PIJ1007

PIR11302 NLINP00PNP0B

PIC23302 PIC23402

PID703 PID803

PID903

PID1003

PIIC1703

PIIC1903

PIJ1004

PIJ1008

PIR11502 PIR16502

PID701

PIJ1002

PIR1

1002

NL

INP0

NPN0

A

PID901

PIJ1006

PIR1

1702

NL

INP0

NPN0

B

PIC23301 PI

D802

PIIC1702

PIR10902

PITP1700

PIC23401 PID1002

PIIC1902

PIR16402

PITP3300

PID8

01

PID1001

PIIC1601

PIR112

02 PIIC1603

PIR1

1902

PIIC1604

PITP1000 POINP0B

PIIC1606

PITP900 POINP0A

PIIC1701

PIIC1704

PIIC1706

PIR11101 PIR112

01 PITP1800

PIIC1707

PIIC1901

PIIC1904

PIIC1906

PIR11801 PIR1

1901

PITP34

00

PIIC1907

PIR10601 PIR10701 PIR10802 PIR10801

PIR1

0901

PI

R110

01

PIR11501

PIR11301 PIR11401 PIR11602 PIR11601

PIR1

1701

PI

R164

01

PIR16501

POINP0A

POINP0B

XX

A Appendix

11

22

33

44

DD

CC

BB

AA

Tite

l:

Dat

um:

Seite

Entw

ickl

erkü

rzel

:Em

il-Fi

gge-

Straße

85,

442

27 D

ortm

und

SSI.S

chD

oc

03.0

9.20

18

9

SeD

a

SS

I.Sch

Doc

Adre

sse:

Zeit:

13:4

6:48

von

23Ve

rsio

n:

Proj

ekt:

VAD

ER_F

RG

A.Pr

jPcb

v1.0

SSI_

DTA

+

SSI_

DTA

-

R12

491

RR

125

91R

R12

1

56R

R12

2

56R

R12

3

33R

R12

02k

2

NC

1

A2

C3

NC

4G

ND

5V

o6

Ve

7V

cc8

IC20

HC

PL-0

600-

500E

SSI_

CLK

+

SSI_

CLK

-

GN

D

3V3

C92

100n

C93

10n

C94

10n

GN

DG

ND

GN

D

3V3

GND 2

VCC5

IC21

AN

C7W

Z14

A1

1Y

16

IC21

B

NC

7WZ1

4

A2

3Y

24

IC21

C

NC

7WZ1

4

C95

100n

GN

D

3V3

C96

100n

GN

D

3V3

GN

D

GN

D

SSI_

CLK

SSI_

DTA

D11

BA

V90

R12

622

k

GN

D

3V3

C97

47p

C98

47p

GN

DG

ND

1

23

D12

MM

BZ3

3VA

LT1G

GN

D

SSI_

DTA

-

SSI_

DTA

+

2 3 41

J15

1036

69-3

DI

1

VCC2D

E3

Z4

GND 5

Y6

IC22

MA

X32

94A

UT+

T

TP11

TP12

SSI_

CLK

-

SSI_

CLK

+

TP19

SSI C

onne

ctor

SSI C

lock

Inpu

t

SSI D

ata

Out

put


2

PIC9301 PIC9302 CO

C93

PIC9401

PIC9402 CO

C94

PIC9501 PIC9502 COC

95

PIC9601 PIC9602 CO

C96

PIC9701 PIC9702 CO

C97


8

PID1101

PID1102

PID1103

COD11

PID1201 PID1202

PID1203

COD1

2

PIIC2001

PIIC2002

PIIC2003

PIIC2004

PIIC2005

PIIC2006

PIIC2007

PIIC2008

COIC20

PIIC2102 PIIC2105 CO

IC21

A

PIIC2101

PIIC2106

COIC

21B

PIIC2103

PIIC2104

COIC

21C

PIIC2201

PIIC2202

PIIC2203

PIIC2204

PIIC2205

PIIC2206 CO

IC22

PIJ1501

PIJ1502

PIJ1503

PIJ1504

COJ15

PIR12001 PIR12002 COR120

PIR1

2101

PI

R121

02

COR1

21

PIR1

2201

PI

R122

02

COR1

22

PIR1

2301

PI

R123

02

COR1

23


R124


R125

PIR12601 PIR12602 COR126

PITP1100 COTP

11

PITP1200 COTP12

PITP1900 COTP

19

PIC9201

PIC9501

PIC9601

PIIC2008

PIIC2105

PIIC2202

PIIC2203

PIR12002 PIC9202

PIC9302 PIC940

2 PIC9502

PIC9602

PIC9702 PIC9802

PID1203

PIIC2005

PIIC2102

PIIC2205 PIR12601

PIC9301 PIR12401 PIC940

1 PIR12501

PID1101

PID1102

PIIC2002

PIR1

2102

PID1103 PIIC2003

PIR1

2202

PIIC2001

PIIC2004

PIIC2006

PIIC2101

PIR12001 PITP1900

PIIC2007

PIIC2103

PIIC2106

PIIC2104

PIR1

2301

PITP1100

PIIC2201

PIR12602 PITP1200

POSSI0DTA

PIR1

2302

POSSI0CLK

PIJ1502

PIR1

2201

PIR12502

NLSSI0CLK0

PIJ1501

PIR1

2101

PIR12402

NLSSI0CLK0

PIC9801 PID1202

PIIC2204

PIJ1503

NLSS

I0DT

A0

PIC9701 PID1201

PIIC2206

PIJ1504

NLSSI0DTA0

POSSI0CLK

POSSI0DTA

XXI

A Appendix

11

22

33

44

DD

CC

BB

AA

Tite

l:

Dat

um:

Seite

Entw

ickl

erkü

rzel

:Em

il-Fi

gge-

Straße

85,

442

27 D

ortm

und

INC

REM

ENTA

L.Sc

hDoc

03.0

9.20

18

10

SeD

a

INC

RE

ME

NTA

L.S

chD

oc

Adre

sse:

Zeit:

13:4

6:48

von

23Ve

rsio

n:

Proj

ekt:

VAD

ER_F

RG

A.Pr

jPcb

v1.0

A IN

1

GND 2

A+

3

A-

4

VC

CI

5

B-

6B

+7

NC

8

B IN

9

MO

N10

C IN

11

GND 12

C+

13

C-

14

ENA

15

D-

16D

+17

NC

18

D IN

19

VC

DD

20IC

14

OL2

068

5V0

GN

D

INC

_A

INC

_B

MO

N_I

NC

1

23

D1

MM

BZ3

3VA

LT1G

1

23

D2

MM

BZ3

3VA

LT1G

C83

47p

C84

47p

C85

47p

C86

47p

GN

DG

ND

GN

DG

ND

GN

DG

ND

R96

22k

R97

22k

GN

D

GN

D

C82

100n

GN

DG

ND

INC

_A+

INC

_A-

INC

_B+

INC

_B-

2 3 41 5 6

J9 1036

69-5

GN

D

24V

_IN

C

24V

_IN

C

C81

10u

INC

_B+

INC

_B-

INC

_A-

INC

_A+

TP15

TP14

TP16

Incr

emen

tal

Incr

emen

tal C

onne

ctor

R21

22k

R22

22k

GN

DG

ND

1

2

3

J17

1x3Su

pply

5V

Supp

ly 2

4V

TP35

TP36

TP38

PIC8101 PIC8102 CO

C81


2

PIC8301 PIC8302 CO

C83

PIC8401 PIC8402 CO

C84


5 PIC860

1 PIC8602 CO

C86

PID101 PID102

PID103

COD1

PID201

PID202

PID203

COD2

PIIC1401

PIIC1402

PIIC1403

PIIC1404

PIIC1405

PIIC1406

PIIC1407

PIIC1408

PIIC1409

PIIC14010

PIIC14011

PIIC14012

PIIC14013

PIIC14014

PIIC14015

PIIC14016

PIIC14017

PIIC14018

PIIC14019

PIIC14020 CO

IC14

PIJ9

01

PIJ9

02

PIJ9

03

PIJ9

04

PIJ9

05

PIJ9

06 COJ9

PIJ1701 PIJ1702

PIJ1703

COJ17


1




PITP1400 COTP

14

PITP1500 COTP

15

PITP1600 COTP

16

PITP3500 COTP

35

PITP3600 COTP

36

PITP3800 COTP

38

PIJ1701

PIJ9

01

PIJ1703

PIC8102 PIC8202

PIC8302 PIC8402

PIC8502

PIC8602

PID103 PID203

PIIC1402 PIIC14012

PIJ9

06

PIR2101 PIR2201

PIR9601 PIR9701 PIC8301

PID101

PIIC1403

PIJ9

02

PITP1400

NLIN

C0A0

PIC8401

PID102

PIIC1404

PIJ9

03

PITP1600

NLIN

C0A0

PIC8501 PID202

PIIC1407

PIJ9

05

PITP3500

NLIN

C0B0

PIC8601

PID201

PIIC1406

PIJ9

04

PITP3600

NLIN

C0B0

PIC8101 PIC8201

PIIC14015

PIIC14020

PIJ1702

PIIC1401

PIR9602 PITP15

00 POINC0A

PIIC1405

PIIC1408

PIIC1409

PIR9702

PITP3800

POINC0B

PIIC14010

POMON0INC

PIIC14011

PIR2102

PIIC14013

PIIC14014

PIIC14016

PIIC14017

PIIC14018

PIIC14019

PIR2202

POINC0A

POINC0B

POMON0INC

XXII

A Appendix

11

22

33

44

DD

CC

BB

AA

Tite

l:

Dat

um:

Seite

Entw

ickl

erkü

rzel

:Em

il-Fi

gge-

Straße

85,

442

27 D

ortm

und

Cam

eraL

ink_

Base

.Sch

Doc

03.0

9.20

18

11

SeD

a

Cam

eraL

ink_

Bas

e.S

chD

oc

Adre

sse:

Zeit:

13:4

6:48

von

23Ve

rsio

n:

Proj

ekt:

VAD

ER_F

RG

A.Pr

jPcb

v1.0

GN

DR

290R

C37

n.b.

R30

0RC

38n.

b.

GN

DG

ND

GN

DG

ND

C36

100n

C35

100n

C34

100n

C33

100n

C32

100n

C31

100n

GN

DG

ND

GN

DG

ND

GN

DG

ND

3V3

GN

D

X0_

N

X0_

P

X1_

N

X1_

P

X2_

N

X2_

P

X3_

N

X3_

P

XC

LK_N

XC

LK_P

3V3

NC

_OU

T_N

EXP_

OU

T_P

SLV

_CLK

_OU

T_N

EXSY

NC

OU

T_P

SER

TFG

_PSE

RTC

_OU

T_N

X3_

PX

CLK

_PX

2_P

X1_

PX

0_P

X0_

NX

1_N

X2_

NX

CLK

_NX

3_N

NC

_OU

T_P

EXP_

OU

T_N

EXSY

NC

OU

T_N

SLV

_CLK

_OU

T_P

SER

TFG

_NSE

RTC

_OU

T_P

SER

TC_O

UT_

P

SER

TC_O

UT_

N

SER

TFG

_N

SER

TFG

_P

GN

D

3V3 C

3910

0n

GN

D

DIN

_S

DE_

SR

E_S

RO

UT_

S

3V3 C

4010

0n

GN

D

GN

D

EN1

DIN

12

DIN

23

VCC4 GND 5

DIN

36

DIN

47

EN*

8D

OU

T4-

9

DO

UT4

+10

DO

UT3

+11

DO

UT3

-12

DO

UT2

-13

DO

UT2

+14

DO

UT1

+15

DO

UT1

-16

IC6

DS9

0LV

047A

TM

GN

D

DE

1

DIN

2

NC 3

RO

UT

4

NC 5NC 6

GND 7

RE

8

RI-

9R

I+10

DO

-11

DO

+12

NC 13

VCC14

IC7

DS9

0LV

019

ENC

Cam

eraL

ink

Bas

e

RX

CLK

_B

RX

OU

T_B

_0R

XO

UT_

B_1

RX

OU

T_B

_2R

XO

UT_

B_3

RX

OU

T_B

_4R

XO

UT_

B_5

RX

OU

T_B

_6R

XO

UT_

B_7

RX

OU

T_B

_8R

XO

UT_

B_9

RX

OU

T_B

_10

RX

OU

T_B

_11

RX

OU

T_B

_12

RX

OU

T_B

_13

RX

OU

T_B

_14

RX

OU

T_B

_15

RX

OU

T_B

_16

RX

OU

T_B

_17

RX

OU

T_B

_18

RX

OU

T_B

_19

RX

OU

T_B

_20

RX

OU

T_B

_21

RX

OU

T_B

_22

RX

OU

T_B

_23

RX

OU

T_B

_24

RX

OU

T_B

_25

RX

OU

T_B

_26

RX

OU

T_B

_27

RX

OU

T_B

_[0.

.27]

RX

OU

T27

7R

XO

UT2

66

RX

OU

T25

5R

XO

UT2

43

RX

OU

T23

2R

XO

UT2

21

RX

OU

T21

55R

XO

UT2

054

RX

OU

T19

53R

XO

UT1

851

RX

OU

T17

50R

XO

UT1

649

RX

OU

T15

47R

XO

UT1

446

RX

OU

T13

45R

XO

UT1

243

RX

OU

T11

42R

XO

UT1

041

RX

OU

T939

RX

OU

T838

RX

OU

T737

RX

OU

T635

RX

OU

T534

RX

OU

T433

RX

OU

T332

RX

OU

T230

RX

OU

T129

RX

OU

T027

RX

CLK

_OU

T26

LVD

SGN

D21

LVD

SGN

D_3

14LV

DSG

ND

_28

PLLG

ND

24PL

LGN

D_2

22G

ND

28G

ND

_536

GN

D_4

52G

ND

_344

GN

D_2

4

PWR

DN

25

RX

CLK

IN+

18R

XC

LKIN

-17

RX

IN3+

20R

XIN

3-19

RX

IN2+

16R

XIN

2-15

RX

IN1+

12R

XIN

1-11

RX

IN0+

10R

XIN

0-9

VC

C48

VC

C_4

56V

CC

_340

VC

C_2

31PL

LVC

C23

LVD

SVC

C13

IC5

DS9

0CR

288

1 2

J6 1036

69-1

12V

0 GN

DF1 600m

A

iLV

DS_

Bas

eR

XC

LK_B

RX

OU

T_B

_[0.

.27]

Cam

eraL

ink

Rec

eive

r Bas

eC

amer

alin

k C

onne

ctor

s Bas

e

Con

figur

atio

n C

hann

el

3V3

Seria

l Cha

nnel

DIN

C[1

..4]

DIN

C1

DIN

C2

DIN

C3

DIN

C4

DIN

C[1

..4]

+C23

84U

7

GN

D

11

22

33

44

55

66

77

88

99

1010

1111

1212

1313

1414

1515

1616

1717

1818

1919

2020

2121

2222

2323

2424

2525

2626

SHIE

LD1

27

SHIE

LD2

28

J1

NC

_OU

T_P

NC

_OU

T_N

EXSY

NC

OU

T_N

EXSY

NC

OU

T_P

EXP_

OU

T_N

EXP_

OU

T_P

SLV

_CLK

_OU

T_P

SLV

_CLK

_OU

T_N

iLV

DS_

Con

figi

LVD

S_C

onfig

iR

XO

UT_

B

R24

100R

R25

100R

R26

100R

R27

100R

R28

100R

R33

100R

PIC3101 PIC3102 CO

C31

PIC3201 PIC3202 CO

C32


PIC3401 PIC3402 CO

C34

PIC3501 PIC3502 CO

C35

PIC3601 PIC3602 CO

C36

PIC3701 PIC3702 CO

C37

PIC3801

PIC3802 CO

C38

PIC3901 PIC3902 CO

C39

PIC4001 PIC4002 CO

C40

PIC23801 PIC23802

COC2

38

PIF1

01

PIF1

02

COF1

PIIC501

PIIC502

PIIC503

PIIC504

PIIC505

PIIC506

PIIC507

PIIC

508

PIIC

509

PIIC5010

PIIC5011

PIIC5012

PIIC5013

PIIC5014

PIIC5015

PIIC5016

PIIC5017

PIIC5018

PIIC5019

PIIC5020

PIIC5021

PIIC5022

PIIC5023

PIIC5024

PIIC5025

PIIC5026

PIIC5027

PIIC5028

PIIC5029

PIIC5030

PIIC5031

PIIC5032

PIIC5033

PIIC5034

PIIC5035

PIIC5036

PIIC5037

PIIC5038

PIIC5039

PIIC5040

PIIC5041

PIIC5042

PIIC5043

PIIC5044

PIIC5045

PIIC5046

PIIC5047

PIIC5048

PIIC5049

PIIC5050

PIIC5051

PIIC5052

PIIC5053

PIIC5054

PIIC5055

PIIC5056 COIC

5

PIIC601

PIIC602

PIIC603

PIIC604 PIIC605

PIIC606

PIIC607

PIIC608

PIIC609

PIIC6010

PIIC6011

PIIC6012

PIIC6013

PIIC6014

PIIC6015

PIIC6016

COIC

6

PIIC701

PIIC702

PIIC703

PIIC704

PIIC705 PIIC706

PIIC707

PIIC708

PIIC709

PIIC

7010

PIIC70

11

PIIC

7012

PIIC7013

PIIC7014 COI

C7

PIJ101

PIJ102

PIJ103

PIJ104

PIJ105

PIJ106

PIJ107

PIJ108

PIJ109

PIJ1010

PIJ1011

PIJ1012

PIJ1013

PIJ1014

PIJ1015

PIJ1016

PIJ1017

PIJ1018

PIJ1019

PIJ1020

PIJ1021

PIJ1022

PIJ1023

PIJ1024

PIJ1025

PIJ1026

PIJ1027

PIJ1028

COJ1

PIJ6

01

PIJ6

02 COJ6

PIR2401 PIR2402 COR

24


PIR2601 PIR2602 CO

R26


PIR2801 PIR2802 CO

R28


9


PIR3301 PIR3302 CO

R33

PIC3101 PIC3201

PIC3301 PIC3401

PIC3501

PIC3601

PIC3901

PIC4001

PIC23801

PIIC5013

PIIC5023

PIIC5025

PIIC5031

PIIC5040

PIIC5048

PIIC5056

PIIC604 PIIC7014

PIF1

01

PIIC6014

PIJ1016

NLEX

P0OU

T0N

PIIC6013

PIJ103

NLEX

P0OU

T0P

PIIC6010

PIJ1018

NLEX

SYNC

OUT0

N

PIIC609

PIJ105

NLEXSYNCOUT0P

PIC3102 PIC3202

PIC3302 PIC3402

PIC3502

PIC3602

PIC3702 PIC380

2

PIC3902

PIC4002

PIC23802

PIIC504

PIIC

508

PIIC5014

PIIC5021

PIIC5022

PIIC5024

PIIC5028

PIIC5036

PIIC5044

PIIC5052

PIIC605 PIIC608

PIIC707

PIJ101

PIJ1013

PIJ1014

PIJ1026

PIJ6

02

PIR2901 PIR3001

PIIC6015

PIJ102

NLNC0OUT0N

PIIC6016

PIJ1015

NLNC

0OUT

0P

PIC3701

PIJ1028 PIR2902

PIC3801

PIJ1027

PIR3002

PIF1

02

PIJ6

01

PIIC601

POENC

PIIC701 PODE0S

PIIC702 PODIN0S

PIIC703

PIIC704 POROUT0S

PIIC705 PIIC706

PIIC708 PORE0S

PIIC7013

PIIC5026

NLRXCLK0B

PORXCLK0B

PIIC70

11

PIJ107

NLSE

RTC0

OUT0

N PI

IC70

12

PIJ1020

NLSE

RTC0

OUT0

P

PIIC709

PIJ1019

PIR3301 NL

SERT

FG0N

PIIC

7010

PIJ106

PIR3302 NLSERTFG0P

PIIC6011

PIJ104

NLSL

V0CL

K0OU

T0N

PIIC6012

PIJ1017

NLSL

V0CL

K0OU

T0P

PIIC

509

PIJ1025

PIR2402 NL

X00N

PIIC5010

PIJ1012

PIR2401 NLX00P

PIIC5011

PIJ1024

PIR2502 NL

X10N

PIIC5012

PIJ1011

PIR2501 NLX10P

PIIC5015

PIJ1023

PIR2602 NL

X20N

PIIC5016

PIJ1010

PIR2601 NLX20P

PIIC5019

PIJ1021

PIR2702 NL

X30N

PIIC5020

PIJ108

PIR2701 NLX30P

PIIC5017

PIJ1022

PIR2802 NLXCLK0N

PIIC5018

PIJ109

PIR2801 NLXCLK0P

PIIC602

NLDINC010040

NLDINC1

PODINC010040

PIIC603

NLDINC010040

NLDINC2

PODINC010040

PIIC606

NLDINC010040

NLDINC3

PODINC010040

PIIC607

NLDINC010040

NLDINC4

PODINC010040

PIIC5027

NLRXOUT0B00000270

NLRX

OUT0

B00

PORXOUT0B00000270

PIIC5029

NLRXOUT0B00000270

NLRX

OUT0

B01

PORXOUT0B00000270

PIIC5030

NLRXOUT0B00000270

NLRX

OUT0

B02

PORXOUT0B00000270

PIIC5032

NLRXOUT0B00000270

NLRX

OUT0

B03

PORXOUT0B00000270

PIIC5033

NLRXOUT0B00000270

NLRX

OUT0

B04

PORXOUT0B00000270

PIIC5034

NLRXOUT0B00000270

NLRX

OUT0

B05

PORXOUT0B00000270

PIIC5035

NLRXOUT0B00000270

NLRX

OUT0

B06

PORXOUT0B00000270

PIIC5037

NLRXOUT0B00000270

NLRX

OUT0

B07

PORXOUT0B00000270

PIIC5038

NLRXOUT0B00000270

NLRX

OUT0

B08

PORXOUT0B00000270

PIIC5039

NLRXOUT0B00000270

NLRX

OUT0

B09

PORXOUT0B00000270

PIIC5041

NLRXOUT0B00000270

NLRXOUT0B010

PORXOUT0B00000270

PIIC5042

NLRXOUT0B00000270

NLRXOUT0B011

PORXOUT0B00000270

PIIC5043

NLRXOUT0B00000270

NLRXOUT0B012

PORXOUT0B00000270

PIIC5045

NLRXOUT0B00000270

NLRXOUT0B013

PORXOUT0B00000270

PIIC5046

NLRXOUT0B00000270

NLRXOUT0B014

PORXOUT0B00000270

PIIC5047

NLRXOUT0B00000270

NLRXOUT0B015

PORXOUT0B00000270

PIIC5049

NLRXOUT0B00000270

NLRXOUT0B016

PORXOUT0B00000270

PIIC5050

NLRXOUT0B00000270

NLRXOUT0B017

PORXOUT0B00000270

PIIC5051

NLRXOUT0B00000270

NLRXOUT0B018

PORXOUT0B00000270

PIIC5053

NLRXOUT0B00000270

NLRXOUT0B019

PORXOUT0B00000270

PIIC5054

NLRXOUT0B00000270

NLRXOUT0B020

PORXOUT0B00000270

PIIC5055

NLRXOUT0B00000270

NLRXOUT0B021

PORXOUT0B00000270

PIIC501

NLRXOUT0B00000270

NLRXOUT0B022

PORXOUT0B00000270

PIIC502

NLRXOUT0B00000270

NLRXOUT0B023

PORXOUT0B00000270

PIIC503

NLRXOUT0B00000270

NLRXOUT0B024

PORXOUT0B00000270

PIIC505

NLRXOUT0B00000270

NLRXOUT0B025

PORXOUT0B00000270

PIIC506

NLRXOUT0B00000270

NLRXOUT0B026

PORXOUT0B00000270

PIIC507

NLRXOUT0B00000270

NLRXOUT0B027

PORXOUT0B00000270

PODE0S

PODIN0S

PODINC1

PODINC2

PODINC3

PODINC4

PODINC010040

POENC

PORE0S

POROUT0S

PORXCLK0B

PORXOUT0B00

PORXOUT0B01

PORXOUT0B02

PORXOUT0B03

PORXOUT0B04

PORXOUT0B05

PORXOUT0B06

PORXOUT0B07

PORXOUT0B08

PORXOUT0B09

PORXOUT0B010

PORXOUT0B011

PORXOUT0B012

PORXOUT0B013

PORXOUT0B014

PORXOUT0B015

PORXOUT0B016

PORXOUT0B017

PORXOUT0B018

PORXOUT0B019

PORXOUT0B020

PORXOUT0B021

PORXOUT0B022

PORXOUT0B023

PORXOUT0B024

PORXOUT0B025

PORXOUT0B026

PORXOUT0B027

PORXOUT0B00000270

XXIII

A Appendix

11

22

33

44

DD

CC

BB

AA

Tite

l:

Dat

um:

Seite

Entw

ickl

erkü

rzel

:Em

il-Fi

gge-

Straße

85,

442

27 D

ortm

und

Cam

eraL

ink_

Med

ium

.Sch

Doc

03.0

9.20

18

12

SeD

a

Cam

eraL

ink_

Med

ium

.Sch

Doc

Adre

sse:

Zeit:

13:4

6:49

von

23Ve

rsio

n:

Proj

ekt:

VAD

ER_F

RG

A.Pr

jPcb

v1.0

R41

0RC

47n.

b.R

420R

C48

n.b.

GN

DG

ND

GN

DG

ND

GN

D

Cam

eraL

ink

Med

ium

Y0_

N

Y0_

PY

1_P

Y1_

NY

2_N

Y2_

P

YC

LK_N

YC

LK_P

Y3_

N

Y3_

P

TER

M_N

TER

M_P

Z0_N

Z1_N

Z2_N

Z0_P

Z1_P

Z2_P

ZCLK

_N

ZCLK

_P

Z3_N

Z3_P

GN

D

C46

100n

C45

100n

C44

100n

C43

100n

C42

100n

C41

100n

GN

DG

ND

GN

DG

ND

GN

DG

ND

3V3

3V3

RX

CLK

_M

YC

LK_N

YC

LK_P

Y0_

N

Y1_

N

Y2_

N

Y3_

N

Y0_

P

Y1_

P

Y2_

P

Y3_

P

TER

M_N

TER

M_P

Z0_N

Z1_N

Z2_N

ZCLK

_NZ3

_N

Z0_P

Z1_P

Z2_P

ZCLK

_PZ3

_P

RX

OU

T_M

_[0.

.27]

RX

OU

T_M

_0R

XO

UT_

M_1

RX

OU

T_M

_2R

XO

UT_

M_3

RX

OU

T_M

_4R

XO

UT_

M_5

RX

OU

T_M

_6R

XO

UT_

M_7

RX

OU

T_M

_8R

XO

UT_

M_9

RX

OU

T_M

_10

RX

OU

T_M

_11

RX

OU

T_M

_12

RX

OU

T_M

_13

RX

OU

T_M

_14

RX

OU

T_M

_15

RX

OU

T_M

_16

RX

OU

T_M

_17

RX

OU

T_M

_18

RX

OU

T_M

_19

RX

OU

T_M

_20

RX

OU

T_M

_21

RX

OU

T_M

_22

RX

OU

T_M

_23

RX

OU

T_M

_24

RX

OU

T_M

_25

RX

OU

T_M

_26

RX

OU

T_M

_27

RX

OU

T27

7R

XO

UT2

66

RX

OU

T25

5R

XO

UT2

43

RX

OU

T23

2R

XO

UT2

21

RX

OU

T21

55R

XO

UT2

054

RX

OU

T19

53R

XO

UT1

851

RX

OU

T17

50R

XO

UT1

649

RX

OU

T15

47R

XO

UT1

446

RX

OU

T13

45R

XO

UT1

243

RX

OU

T11

42R

XO

UT1

041

RX

OU

T939

RX

OU

T838

RX

OU

T737

RX

OU

T635

RX

OU

T534

RX

OU

T433

RX

OU

T332

RX

OU

T230

RX

OU

T129

RX

OU

T027

RX

CLK

_OU

T26

LVD

SGN

D21

LVD

SGN

D_3

14LV

DSG

ND

_28

PLLG

ND

24PL

LGN

D_2

22G

ND

28G

ND

_536

GN

D_4

52G

ND

_344

GN

D_2

4

PWR

DN

25

RX

CLK

IN+

18R

XC

LKIN

-17

RX

IN3+

20R

XIN

3-19

RX

IN2+

16R

XIN

2-15

RX

IN1+

12R

XIN

1-11

RX

IN0+

10R

XIN

0-9

VC

C48

VC

C_4

56V

CC

_340

VC

C_2

31PL

LVC

C23

LVD

SVC

C13

IC8

DS9

0CR

288

iLV

DS_

Med

ium

RX

OU

T_M

_[0.

.27]

RX

CLK

_M

Cam

eral

ink

Rec

eive

r Med

ium

Cam

eral

ink

Con

nect

or M

ediu

m

Term

unat

ion

unus

ed

+C23

94U

7

GN

D

11

22

33

44

55

66

77

88

99

1010

1111

1212

1313

1414

1515

1616

1717

1818

1919

2020

2121

2222

2323

2424

2525

2626

SHIE

LD1

27

SHIE

LD2

28

J3

iLV

DS_

Term

inat

ion

iR

XO

UT_

M

R43

100R

R46

100R

R47

100R

R44

100R

R45

100R

R48

100R

R40

100R

R39

100R

R38

100R

R37

100R

R36

100R



2 PIC4301 PIC4302

COC4

3 PIC4401 PIC4402

COC4

4 PIC450

1 PIC450

2 COC4

5 PIC4601 PIC4602

COC4

6


PIC4801 PIC4802 CO

C48

PIC23901

PIC23902

COC2

39

PIIC801

PIIC802

PIIC803

PIIC804

PIIC805

PIIC806

PIIC807

PIIC808

PIIC809

PIIC8010

PIIC8011

PIIC8012

PIIC8013

PIIC8014

PIIC8015

PIIC8016

PIIC8017

PIIC8018

PIIC8019

PIIC8020

PIIC8021

PIIC8022

PIIC8023

PIIC8024

PIIC8025

PIIC8026

PIIC8027

PIIC8028

PIIC8029

PIIC8030

PIIC8031

PIIC8032

PIIC8033

PIIC8034

PIIC8035

PIIC8036

PIIC8037

PIIC8038

PIIC8039

PIIC8040

PIIC8041

PIIC8042

PIIC8043

PIIC8044

PIIC8045

PIIC8046

PIIC8047

PIIC8048

PIIC8049

PIIC8050

PIIC8051

PIIC8052

PIIC8053

PIIC8054

PIIC8055

PIIC8056

COIC

8

PIJ301

PIJ302

PIJ303

PIJ304

PIJ305

PIJ306

PIJ307

PIJ308

PIJ309

PIJ3010

PIJ3011

PIJ3012

PIJ3013

PIJ3014

PIJ3015

PIJ3016

PIJ3017

PIJ3018

PIJ3019

PIJ3020

PIJ3021

PIJ3022

PIJ3023

PIJ3024

PIJ3025

PIJ3026

PIJ3027

PIJ3028

COJ3

PIR3601 PIR3602 CO

R36


7


8

PIR3901 PIR3902 CO

R39


0


1




4

PIR4501 PIR4502 CO

R45



7

PIR4801 PIR4802 CO

R48

PIC4101 PIC4201

PIC4301 PIC4401

PIC4501

PIC4601 PIC239

01

PIIC8013

PIIC8023

PIIC8025

PIIC8031

PIIC8040

PIIC8048

PIIC8056

PIC4102 PIC4202

PIC4302 PIC4402

PIC4502

PIC4602

PIC4702 PIC4802

PIC23902

PIIC804

PIIC808

PIIC8014

PIIC8021

PIIC8022

PIIC8024

PIIC8028

PIIC8036

PIIC8044

PIIC8052

PIJ301

PIJ3013

PIJ3014

PIJ3026 PIR4101

PIR4201

PIC4701

PIJ3028 PIR4102

PIC4801

PIJ3027

PIR4202

PIIC8026 NL

RXCL

K0M

PORXCLK0M

PIJ3020

PIR4302 NLTERM0N

PIJ307

PIR4301 NLTERM0P

PIIC809

PIJ3025

PIR3602 NL

Y00N

PIIC8010

PIJ3012

PIR3601 NLY00P

PIIC8011

PIJ3024

PIR3702 NL

Y10N

PIIC8012

PIJ3011

PIR3701 NLY10P

PIIC8015

PIJ3023

PIR3802 NL

Y20N

PIIC8016

PIJ3010

PIR3801 NLY20P

PIIC8019

PIJ3021

PIR3902 NL

Y30N

PIIC8020

PIJ308

PIR3901 NLY30P

PIIC8017

PIJ3022

PIR4002 NLYCLK0N

PIIC8018

PIJ309

PIR4001 NLYCLK0P

PIJ3019

PIR4402 NLZ00N

PIJ306

PIR4401 NL

Z00P

PIJ3018

PIR4502 NLZ10N

PIJ305

PIR4501 NLZ10P

PIJ3017

PIR4602 NLZ20N

PIJ304

PIR4601 NL

Z20P

PIJ3015

PIR4802 NLZ30N

PIJ302

PIR4801 NLZ30P

PIJ3016

PIR4702 NLZCLK0N

PIJ303

PIR4701 NLZCLK0P

PIIC8027

NLRX

OUT0

M000

0027

0 NL

RXOU

T0M0

0 PORXOUT0M00000270

PIIC8029

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M01

PORXOUT0M00000270

PIIC8030

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M02

PORXOUT0M00000270

PIIC8032

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M03

PORXOUT0M00000270

PIIC8033

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M04

PORXOUT0M00000270

PIIC8034

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M05

PORXOUT0M00000270

PIIC8035

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M06

PORXOUT0M00000270

PIIC8037

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M07

PORXOUT0M00000270

PIIC8038

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M08

PORXOUT0M00000270

PIIC8039

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M09

PORXOUT0M00000270

PIIC8041

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M010

PORXOUT0M00000270

PIIC8042

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M011

PORXOUT0M00000270

PIIC8043

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M012

PORXOUT0M00000270

PIIC8045

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M013

PORXOUT0M00000270

PIIC8046

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M014

PORXOUT0M00000270

PIIC8047

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M015

PORXOUT0M00000270

PIIC8049

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M016

PORXOUT0M00000270

PIIC8050

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M017

PORXOUT0M00000270

PIIC8051

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M018

PORXOUT0M00000270

PIIC8053

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M019

PORXOUT0M00000270

PIIC8054

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M020

PORXOUT0M00000270

PIIC8055

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M021

PORXOUT0M00000270

PIIC801

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M022

PORXOUT0M00000270

PIIC802

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M023

PORXOUT0M00000270

PIIC803

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M024

PORXOUT0M00000270

PIIC805

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M025

PORXOUT0M00000270

PIIC806

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M026

PORXOUT0M00000270

PIIC807

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M027

PORXOUT0M00000270

PORXCLK0M

PORXOUT0M00

PORXOUT0M01

PORXOUT0M02

PORXOUT0M03

PORXOUT0M04

PORXOUT0M05

PORXOUT0M06

PORXOUT0M07

PORXOUT0M08

PORXOUT0M09

PORXOUT0M010

PORXOUT0M011

PORXOUT0M012

PORXOUT0M013

PORXOUT0M014

PORXOUT0M015

PORXOUT0M016

PORXOUT0M017

PORXOUT0M018

PORXOUT0M019

PORXOUT0M020

PORXOUT0M021

PORXOUT0M022

PORXOUT0M023

PORXOUT0M024

PORXOUT0M025

PORXOUT0M026

PORXOUT0M027

PORXOUT0M00000270

XXIV

A Appendix

11

22

33

44

DD

CC

BB

AA

Tite

l:

Dat

um:

Seite

Entw

ickl

erkü

rzel

:Em

il-Fi

gge-

Straße

85,

442

27 D

ortm

und

CO

N_D

SP.S

chD

oc

03.0

9.20

18

13

SeD

a

CO

N_D

SP

.Sch

Doc

Adre

sse:

Zeit:

13:4

6:49

von

23Ve

rsio

n:

Proj

ekt:

VAD

ER_F

RG

A.Pr

jPcb

v1.0

23

41 5

67

89

1011

1213

1415

1617

1819

2021

22 2423 25

2627

2829

3031

3233

3435

3637

3839

4041

4243

4445

4647

4849

5051

5253

5455

5657

5859

6061

6263

6465

6667

6869

7071

7273

7475

7677

7879

8081

8283

8485

8687

8889

9091

9293

9495

9697

9899

100

J2 6695

3-02

5LF

GN

DG

ND

12V

0_D

SPD

EV

MC

ASP

0AX

R9

MC

ASP

0AC

LKX

MC

ASP

0AX

R6

MC

ASP

1AX

R5

MC

ASP

0AX

R12

MC

ASP

0AX

R1

MC

ASP

0AX

R13

MC

ASP

0AX

R14

MC

ASP

0AC

LKR

MC

ASP

0AX

R4

MC

ASP

0AX

R0

MC

ASP

1AX

R9

MC

ASP

1AX

R2

MC

ASP

0AX

R5

MC

ASP

1FSR

MC

ASP

1AX

R4

MC

ASP

1AX

R8

MC

ASP

1AC

LKR

MC

ASP

1AX

R0

MC

ASP

1AM

UTE

_R

SPI2

_SC

S0SP

I2_M

OSI

SPI2

_MIS

O

MC

ASP

1FSX

MC

ASP

0AM

UTE

MC

ASP

1AC

LKX

MC

ASP

1AX

R1

MC

ASP

1AX

R3

MC

ASP

1AH

CLK

R

MC

ASP

1AX

R6

MC

ASP

0AX

R7

MC

ASP

0AH

CLK

R

MC

ASP

1AX

R7

MC

ASP

0AX

R2

MC

ASP

0FSR

MC

ASP

0FSX

MC

ASP

0AH

CLK

XM

CA

SP0A

XR

15

MC

ASP

0AX

R3

MC

ASP

0AX

R10

_R

MC

ASP

0AX

R8

MC

ASP

1AX

R5

MC

ASP

1AX

R9

MC

ASP

1AX

R2

MC

ASP

1FSR

MC

ASP

1AX

R4

MC

ASP

1AX

R8

MC

ASP

1AC

LKR

MC

ASP

1AX

R0

MC

ASP

1AM

UTE

_R

MC

ASP

1FSX

MC

ASP

1AC

LKX

MC

ASP

1AX

R1

MC

ASP

1AX

R3

MC

ASP

1AH

CLK

R

MC

ASP

1AX

R6

MC

ASP

1AX

R7

MC

ASP

0AX

R9

MC

ASP

0AC

LKX

MC

ASP

0AX

R6

MC

ASP

0AX

R12

MC

ASP

0AX

R1

MC

ASP

0AX

R13

MC

ASP

0AX

R14

MC

ASP

0AC

LKR

MC

ASP

0AX

R4

MC

ASP

0AX

R0

MC

ASP

0AX

R5

MC

ASP

0AM

UTE

MC

ASP

0AX

R7

MC

ASP

0AH

CLK

R

MC

ASP

0AX

R2

MC

ASP

0FSR

MC

ASP

0FSX

MC

ASP

0AH

CLK

X

MC

ASP

0AX

R15

MC

ASP

0AX

R8

_R: R

esis

tor O

ptio

n on

DSP

Boa

rd, D

efau

lt n.

b.

MC

ASP

0AX

R10

MC

ASP

0AX

R[0

..15]

MC

ASP

1AX

R[0

..9]

MC

ASP

0AM

UTE

MC

ASP

0FSR

MC

ASP

0FSX

MC

ASP

0AC

LKR

MC

ASP

0AC

LKX

MC

ASP

0AH

CLK

RM

CA

SP0A

HC

LKX

MC

ASP

1AM

UTE

_R

MC

ASP

1FSR

MC

ASP

1FSX

MC

ASP

1AC

LKR

MC

ASP

1AC

LKX

MC

ASP

1AH

CLK

R

SPI2

_SC

S0SP

I2_M

OSI

RES

ETST

AT

SPI2

_CLK

SPI2

_MIS

O

RES

ETST

AT

SPI2

_CLK

SPI2

_MIS

OSP

I2_S

CS0

SPI2

_MO

SI

MC

ASP

0AX

R10

_RR

92

n.b.

12V

0_D

SPD

EV12

V0

MC

ASP

0AX

R[0

..15]

MC

ASP

1AX

R[0

..9]

R15

9

n.b.

DSP

Con

nect

orIn

terf

ace

iM

cASP

R31

100R

R49

100R

SPI2

_CLK

RES

ETST

AT

R95

100R

R16

710

0RR

169

100R

R17

110

0RR

173

100R

R17

510

0RR

177

100R

R17

910

0RR

181

100R

R18

310

0RR

185

100R

R18

710

0RR

189

100R

R19

110

0RR

193

100R

R19

510

0RR

197

100R

R19

910

0RR

201

100R

R20

310

0R

R55

100R

R94

100R

3V3_

DSP

DEV

R16

610

0RR

168

100R

R17

010

0RR

172

100R

R17

410

0RR

176

100R

R17

810

0R

R18

210

0RR

184

100R

R18

610

0RR

188

100R

R19

010

0RR

192

100R

R19

410

0RR

196

100R

R19

810

0RR

200

100R

R20

210

0R

R81

100R

PIJ2

01

PIJ2

02

PIJ2

03

PIJ2

04

PIJ2

05

PIJ2

06

PIJ2

07

PIJ2

08

PIJ2

09

PIJ2010

PIJ2011

PIJ2012

PIJ2013

PIJ2014

PIJ2015

PIJ2016

PIJ2017

PIJ2018

PIJ2019

PIJ2020

PIJ2021

PIJ2022

PIJ2023

PIJ2024

PIJ2025

PIJ2026

PIJ2027

PIJ2028

PIJ2029

PIJ2030

PIJ2031

PIJ2032

PIJ2033

PIJ2034

PIJ2035

PIJ2036

PIJ2037

PIJ2038

PIJ2039

PIJ2040

PIJ2041

PIJ2042

PIJ2043

PIJ2044

PIJ2045

PIJ2046

PIJ2047

PIJ2048

PIJ2049

PIJ2050

PIJ2051

PIJ2052

PIJ2053

PIJ2054

PIJ2055

PIJ2056

PIJ2057

PIJ2058

PIJ2059

PIJ2060

PIJ2061

PIJ2062

PIJ2063

PIJ2064

PIJ2065

PIJ2066

PIJ2067

PIJ2068

PIJ2069

PIJ2070

PIJ2071

PIJ2072

PIJ2073

PIJ2074

PIJ2075

PIJ2076

PIJ2077

PIJ2078

PIJ2079

PIJ2080

PIJ2081

PIJ2082

PIJ2083

PIJ2084

PIJ2085

PIJ2086

PIJ2087

PIJ2088

PIJ2089

PIJ2090

PIJ2091

PIJ2092

PIJ2093

PIJ2094

PIJ2095

PIJ2096

PIJ2097

PIJ2098

PIJ2099

PIJ201

00

COJ2

PIR3101

PIR3102

COR31

PIR4901

PIR4902

COR49

PIR5501

PIR5502

COR5

5 PIR8101

PIR8102

COR8

1

PIR9201

PIR9

202

COR9

2

PIR9401

PIR9402

COR94

PIR9501

PIR9502

COR9

5

PIR1

5901

PI

R159

02

COR1

59

PIR1

6601

PI

R166

02

COR1

66

PIR167

01 PIR

16702

COR1

67

PIR168

01 PIR

16802

COR1

68

PIR1

6901

PI

R169

02

COR1

69

PIR1

7001

PI

R170

02

COR1

70

PIR1

7101

PI

R171

02

COR171

PIR1

7201

PI

R172

02

COR1

72

PIR173

01 PIR

17302

COR173

PIR174

01 PIR

17402

COR1

74

PIR1

7501

PI

R175

02

COR1

75

PIR1

7601

PI

R176

02

COR1

76

PIR1

7701

PI

R177

02

COR1

77

PIR1

7801

PI

R178

02

COR178

PIR1

7901

PI

R179

02

COR1

79

PIR181

01 PIR

18102

COR181

PIR182

01 PIR

18202

COR1

82

PIR1

8301

PI

R183

02

COR1

83

PIR1

8401

PI

R184

02

COR1

84

PIR1

8501

PI

R185

02

COR185

PIR1

8601

PI

R186

02

COR1

86

PIR187

01 PIR

18702

COR1

87

PIR188

01 PIR

18802

COR1

88

PIR1

8901

PI

R189

02

COR1

89

PIR1

9001

PI

R190

02

COR1

90

PIR1

9101

PI

R191

02

COR191

PIR1

9201

PI

R192

02

COR1

92

PIR193

01 PIR

19302

COR193

PIR194

01 PIR

19402

COR1

94

PIR195

01 PIR

19502

COR1

95

PIR196

01 PIR

19602

COR1

96

PIR1

9701

PI

R197

02

COR1

97

PIR1

9801

PI

R198

02

COR198

PIR1

9901

PI

R199

02

COR1

99

PIR2

0001

PI

R200

02

COR2

00

PIR201

01 PIR

20102

COR201

PIR202

01 PIR

20202

COR2

02

PIR2

0301

PI

R203

02

COR2

03

PIJ2010

PIJ2012

PIR1

5902

PIJ2

02

PIJ2

04

PIJ2

06

PIR1

5901

PIJ2

01

PIJ2

03

PIJ2

05

PIJ2

07

PIJ2

08

PIJ2013

PIJ2014

PIJ2019

PIJ2020

PIJ2025

PIJ2026

PIJ2031

PIJ2032

PIJ2037

PIJ2038

PIJ2043

PIJ2044

PIJ2049

PIJ2050

PIJ2055

PIJ2056

PIJ2061

PIJ2062

PIJ2067

PIJ2068

PIJ2073

PIJ2074

PIJ2079

PIJ2080

PIJ2084

PIJ2085

PIJ2086

PIJ2091

PIJ2095

PIJ2096

PIJ2099

PIJ201

00

PIR187

01

NLMC

ASP0

ACLK

R POMCASP0ACLKR

PIR201

01

NLMC

ASP0

ACLK

X POMCASP0ACLKX

PIR1

8402

NLMCASP0AHCLKR

POMCASP0AHCLKR

PIR194

02

NLMCASP0AHCLKX

POMCASP0AHCLKX

PIR168

02

NLMC

ASP0

AMUT

E POMCASP0AMUTE

PIR9

202

PIR2

0002

NLMC

ASP0

AXR1

00R

PIR1

9002

NLMC

ASP0

FSR

POMCASP0FSR

PIR1

9202

NLMC

ASP0

FSX

POMCASP0FSX

PIR1

6901

NLMC

ASP1

ACLK

R POMCASP1ACLKR

PIR1

7002

NLMC

ASP1

ACLK

X POMCASP1ACLKX

PIR1

7602

NLMCASP1AHCLKR

POMCASP1AHCLKR

PIR9501

NLMCASP1AMUTE0R

POMCASP1AMUTE0R

PIR1

7501

NLMC

ASP1

FSR

POMCASP1FSR

PIR1

6602

NLMC

ASP1

FSX

POMCASP1FSX

PIJ2

09

PIR3102

PIJ2011

PIR4902

PIJ2015

PIR5502

PIJ2016 PIR8101

PIJ2017

PIR9402

PIJ2018

PIJ2021

PIJ2022

PIJ2023

PIJ2024

PIJ2027

PIR9502

PIJ2028

PIR1

6601

PIJ2029

PIR167

02 PIJ2030 PIR168

01

PIJ2033

PIR1

6902

PIJ2034

PIR1

7001

PIJ2035

PIR1

7102

PIJ2036 PIR1

7201

PIJ2039

PIR173

02 PIJ2040

PIR174

01

PIJ2041

PIR1

7502

PIJ2042 PIR1

7601

PIJ2045

PIR1

7702

PIJ2046

PIR1

7801

PIJ2047

PIR1

7902

PIJ2048

PIJ2051

PIR181

02 PIJ2052

PIR182

01

PIJ2053

PIR1

8302

PIJ2054 PIR1

8401

PIJ2057

PIR1

8502

PIJ2058

PIR1

8601

PIJ2059

PIR187

02 PIJ2060 PIR188

01

PIJ2063

PIR1

8902

PIJ2064

PIR1

9001

PIJ2065

PIR1

9102

PIJ2066 PIR1

9201

PIJ2069

PIR193

02 PIJ2070

PIR194

01

PIJ2071

PIR195

02 PIJ2072 PIR196

01

PIJ2075

PIR1

9702

PIJ2076

PIR1

9801

PIJ2077

PIR1

9902

PIJ2078 PIR2

0001

PIJ2081

PIR201

02 PIJ2082 PIR202

01

PIJ2083

PIR2

0302

PIJ2087

PIJ2088

PIJ2089

PIJ2090

PIJ2092

PIJ2093

PIJ2094

PIJ2097

PIJ2098

PIR4901

NLRE

SETS

TAT

PORESETSTAT

PIR3101

NLSP

I20C

LK

POSPI20CLK

PIR8102

NLSPI20MISO

POSPI20MISO

PIR5501

NLSPI20MOSI

POSPI20MOSI

PIR9401

NLSPI20SCS0

POSPI20SCS0

PIR1

8301

NLMC

ASP0

AXR0

0001

50

NLMC

ASP0

AXR0

POMCASP0AXR0000150

PIR193

01

NLMC

ASP0

AXR0

0001

50

NLMC

ASP0

AXR1

POMCASP0AXR0000150

PIR188

02

NLMC

ASP0

AXR0

0001

50

NLMC

ASP0

AXR2

POMCASP0AXR0000150

PIR1

9802

NLMC

ASP0

AXR0

0001

50

NLMC

ASP0

AXR3

POMCASP0AXR0000150

PIR1

8501

NLMC

ASP0

AXR0

0001

50

NLMC

ASP0

AXR4

POMCASP0AXR0000150

PIR1

7701

NLMC

ASP0

AXR0

0001

50

NLMC

ASP0

AXR5

POMCASP0AXR0000150

PIR1

9901

NLMC

ASP0

AXR0

0001

50

NLMC

ASP0

AXR6

POMCASP0AXR0000150

PIR182

02

NLMC

ASP0

AXR0

0001

50

NLMC

ASP0

AXR7

POMCASP0AXR0000150

PIR202

02

NLMC

ASP0

AXR0

0001

50

NLMC

ASP0

AXR8

POMCASP0AXR0000150

PIR2

0301

NLMC

ASP0

AXR0

0001

50

NLMC

ASP0

AXR9

POMCASP0AXR0000150

PIR9201

NLMC

ASP0

AXR0

0001

50

NLMC

ASP0

AXR1

0

POMCASP0AXR0000150

NLMC

ASP0

AXR0

0001

50 POMCASP0AXR0000150

PIR195

01

NLMC

ASP0

AXR0

0001

50

NLMC

ASP0

AXR1

2

POMCASP0AXR0000150

PIR1

8901

NLMC

ASP0

AXR0

0001

50

NLMC

ASP0

AXR1

3

POMCASP0AXR0000150

PIR1

9101

NLMC

ASP0

AXR0

0001

50

NLMC

ASP0

AXR1

4

POMCASP0AXR0000150

PIR196

02

NLMC

ASP0

AXR0

0001

50

NLMC

ASP0

AXR1

5

POMCASP0AXR0000150

PIR167

01

NLMC

ASP1

AXR0

0009

0

NLMC

ASP1

AXR0

POMCASP1AXR000090

PIR1

7202

NLMC

ASP1

AXR0

0009

0

NLMC

ASP1

AXR1

POMCASP1AXR000090

PIR1

7901

NLMC

ASP1

AXR0

0009

0

NLMC

ASP1

AXR2

POMCASP1AXR000090

PIR174

02 NL

MCAS

P1AX

R000

090

NLMC

ASP1

AXR3

POMCASP1AXR000090

PIR173

01 NL

MCAS

P1AX

R000

090

NLMC

ASP1

AXR4

POMCASP1AXR000090

PIR1

9701

NLMC

ASP1

AXR0

0009

0

NLMC

ASP1

AXR5

POMCASP1AXR000090

PIR1

7802

NLMC

ASP1

AXR0

0009

0

NLMC

ASP1

AXR6

POMCASP1AXR000090

PIR1

8602

NLMC

ASP1

AXR0

0009

0

NLMC

ASP1

AXR7

POMCASP1AXR000090

PIR1

7101

NLMC

ASP1

AXR0

0009

0

NLMC

ASP1

AXR8

POMCASP1AXR000090

PIR181

01

NLMC

ASP1

AXR0

0009

0

NLMC

ASP1

AXR9

POMCASP1AXR000090

POMCASP0ACLKR

POMCASP0ACLKX

POMCASP0AHCLKR

POMCASP0AHCLKX

POMCASP0AMUTE

POMCASP0AXR0

POMCASP0AXR1

POMCASP0AXR2

POMCASP0AXR3

POMCASP0AXR4

POMCASP0AXR5

POMCASP0AXR6

POMCASP0AXR7

POMCASP0AXR8

POMCASP0AXR9

POMCASP0AXR10

POMCASP0AXR11

POMCASP0AXR12

POMCASP0AXR13

POMCASP0AXR14

POMCASP0AXR15

POMCASP0AXR0000150

POMCASP0FSR

POMCASP0FSX

POMCASP1ACLKR

POMCASP1ACLKX

POMCASP1AHCLKR

POMCASP1AMUTE0R

POMCASP1AXR0

POMCASP1AXR1

POMCASP1AXR2

POMCASP1AXR3

POMCASP1AXR4

POMCASP1AXR5

POMCASP1AXR6

POMCASP1AXR7

POMCASP1AXR8

POMCASP1AXR9

POMCASP1AXR000090

POMCASP1FSR

POMCASP1FSX

PORESETSTAT

POSPI20CLK

POSPI20MISO

POSPI20MOSI

POSPI20SCS0

XXV

A Appendix

11

22

33

44

DD

CC

BB

AA

Tite

l:

Dat

um:

Seite

Entw

ickl

erkü

rzel

:Em

il-Fi

gge-

Straße

85,

442

27 D

ortm

und

USB

_IN

TER

FAC

E.Sc

hDoc

03.0

9.20

18

14

SeD

a

US

B_I

NTE

RFA

CE

.Sch

Doc

Adre

sse:

Zeit:

13:4

6:50

von

23Ve

rsio

n:

Proj

ekt:

VAD

ER_F

RG

A.Pr

jPcb

v1.0

FTD

I_R

XF

FTD

I_TX

EFT

DI_

RD

FTD

I_W

RFT

DI_

SIW

UA

FTD

I_O

E3V3

X1A

12.0

00 M

Hz

C70

27p

C71

27p

GN

DG

ND

3V3

GN

D

GN

D

VC

C1

D-

2

D+

3

ID4

GN

D5

J4 Mic

ro U

SB

5V0_

USB

GN

D

GN

DG

ND

GN

DG

ND

GN

DG

ND

1V8

GN

D

GN

DG

ND

3V3

GN

DG

ND

GN

DG

ND

USB

_D_N

USB

_D_P

R62

10k

R63

10k

R64

10k

R65

2k2

R61

10k

3V3

3V3

3V3

3V3

R59

0R

GN

D65

GN

D51

GN

D47

GN

D35

GN

D25

GN

D15

GN

D11

GN

D5

GN

D1

AG

ND

10

BC

BU

S759

BC

BU

S658

BC

BU

S557

BC

BU

S455

BC

BU

S354

BC

BU

S253

BC

BU

S152

BC

BU

S048

BD

BU

S746

BD

BU

S645

BD

BU

S544

BD

BU

S443

BD

BU

S341

BD

BU

S240

BD

BU

S139

BD

BU

S038

SUSP

END

#36

PWR

EN#

60

EEC

LK62

VR

EGO

UT

49V

REG

IN50

VPH

Y4

VPL

L9

VC

CIO

56V

CC

IO42

VC

CIO

31V

CC

IO20

VC

OR

E64

VC

OR

E37

VC

OR

E12

AC

BU

S734

AC

BU

S633

AC

BU

S532

AC

BU

S430

AC

BU

S329

AC

BU

S228

AC

BU

S127

AC

BU

S026

AD

BU

S724

AD

BU

S623

AD

BU

S522

AD

BU

S421

AD

BU

S319

AD

BU

S218

AD

BU

S117

AD

BU

S016

EEC

S63

EED

ATA

61

OSC

O3

OSC

I2

DP

8D

M7

TEST

13R

EF6

RES

ET#

14

IC11

FT22

32H

Q

FTD

I_D

0FT

DI_

D1

FTD

I_D

2FT

DI_

D3

FTD

I_D

4FT

DI_

D5

FTD

I_D

6FT

DI_

D7

FTD

I_D

[0..7

]

GN

D2

GN

D4

X1B

12.0

00 M

Hz

GN

D

iU

SB_D

JTA

G_T

DI

JTA

G_T

DO

JTA

G_T

CK

JTA

G_T

MS

C57

100n

C58

100n

C59

100n

C60

100n

C61

100n C

6510

0nC

6410

0nC

6310

0nC

6210

0n

C69

100n

C68

100n

C72

100n

FTD

I_D

[0..7

]

I/O1

1I/O

16

I/O2

3I/O

24

D17

A

8240

0102

GN

D2

VD

D5

D17

B

8240

0102

5V0_

USB

GN

DC

237

100n

GN

DR60

12k

GN

DG

ND

USB

_NU

SB_P

C66

4u7

C67

4u7

DO

1G

ND

2

DI

3

CLK

4

CS

5

VC

C6

IC12

93C

46B

-I/S

N

L4 33R

@ 1

00M

Hz

L3 33R

@ 1

00M

Hz

iFT

DI_

Inte

rfac

e

Asy

nchr

onou

s FI

FO M

ode


7 PIC5801 PIC5802

COC5

8 PIC590

1 PIC590

2 COC5

9 PIC6001 PIC6002

COC60

PIC6101

PIC6102 CO

C61

PIC6201 PIC6202 COC

62 PIC630

1 PIC630

2 COC6

3 PIC6401 PIC6402

COC64

PIC6501 PIC6502 CO

C65

PIC6601 PIC6602 CO

C66

PIC6701

PIC6702 CO

C67

PIC6801

PIC6802 CO

C68

PIC6901 PIC6902 CO

C69

PIC7001 PIC7002 CO

C70

PIC7101

PIC7102 CO

C71

PIC7201

PIC7202 CO

C72

PIC23701

PIC23702 CO

C237

PID1701

PID1703

PID1704

PID1706

COD1

7A

PID1702

PID1705

COD1

7B

PIIC1101

PIIC1102

PIIC1103

PIIC1104

PIIC1105

PIIC1106

PIIC1107

PIIC1108

PIIC1109

PIIC11010

PIIC11011

PIIC11012

PIIC11013

PIIC11014

PIIC11015

PIIC11016

PIIC11017

PIIC11018

PIIC11019

PIIC11020

PIIC11021

PIIC11022

PIIC11023

PIIC11024

PIIC11025

PIIC11026

PIIC11027

PIIC11028

PIIC11029

PIIC11030

PIIC11031

PIIC11032

PIIC11033

PIIC11034

PIIC11035

PIIC11036

PIIC11037

PIIC11038

PIIC11039

PIIC11040

PIIC11041

PIIC11042

PIIC11043

PIIC11044

PIIC11045

PIIC11046

PIIC11047

PIIC11048

PIIC11049

PIIC11050

PIIC11051

PIIC11052

PIIC11053

PIIC11054

PIIC11055

PIIC11056

PIIC11057

PIIC11058

PIIC11059

PIIC11060

PIIC11061

PIIC11062

PIIC11063

PIIC11064

PIIC11065

COIC

11

PIIC1201

PIIC1202

PIIC1203

PIIC1204

PIIC1205

PIIC1206 COIC12

PIJ401

PIJ402

PIJ403

PIJ404

PIJ405

COJ4

PIL3

01

PIL3

02

COL3

PIL4

01

PIL4

02

COL4


PIR6001 PIR6002

COR60


1


2

PIR6301 PIR6302 CO

R63

PIR6401 PIR6402 CO

R64

PIR6501

PIR6502

COR65

PIX101

PIX103

COX1

A

PIX1

02

PIX1

04

COX1

B

PIC5702 PIC5802

PIC5902

PIC6002 PIC610

2

PIIC11012

PIIC11037

PIIC11064

PIC6202 PIC630

2 PIC6402

PIC6502

PIC7202

PIIC11020

PIIC11031

PIIC11042

PIIC11050

PIIC11056

PIIC1206

PIL3

02

PIL4

02

PIR6102

PIR6202 PIR6302

PIR6402

PIC23702

PID1705

PIJ401

PIC5701 PIC5801

PIC5901

PIC6001 PIC610

1

PIC6201 PIC630

1 PIC6401

PIC6501

PIC6602 PIC6702

PIC6801

PIC6901

PIC7002 PIC7102

PIC7201

PIC23701

PID1702

PIIC1101

PIIC1105

PIIC11010

PIIC11011

PIIC11015

PIIC11025

PIIC11035

PIIC11047

PIIC11051

PIIC11065

PIIC1202

PIJ405

PIR5901 PIR6002

PIX1

02

PIX1

04

PIC6601 PIC6802

PIIC1109

PIL3

01

PIC6701

PIC6902 PIIC1104

PIL4

01

PIC7001 PIIC1102

PIX101

PIC7101

PIIC1103

PIX103

PIIC1106

PIR6001

PIIC11013

PIR5902

PIIC11014

PIR6101

PIIC11016

POJTAG0TCK

PIIC11017

POJTAG0TDI

PIIC11018

POJTAG0TDO

PIIC11019

POJTAG0TMS

PIIC11021

PIIC11022

PIIC11023

PIIC11024

PIIC11026

PIIC11027

PIIC11028

PIIC11029

PIIC11030

PIIC11032

PIIC11033

PIIC11034

PIIC11036

PIIC11048

POFTDI0RXF

PIIC11049

PIIC11052

POFTDI0TXE

PIIC11053

POFTDI0RD

PIIC11054

POFTDI0WR

PIIC11055

POFTDI0SIWUA

PIIC11057

PIIC11058

PIIC11059

POFTDI0OE

PIIC11060

PIIC11061

PIIC1203

PIR6502

PIIC11062

PIIC1204

PIR6401

PIIC11063

PIIC1205

PIR6301

PIIC1201

PIR6201

PIR6501

PIJ404

PID1706

PIIC1107

NLUSB0D0N

PID1704

PIIC1108

NLUS

B0D0

P PID1701

PIJ402

NLUS

B0N

PID1703

PIJ403

NLUSB0P

PIIC11038

NLFT

DI0D

0000

70

NLFTDI0D0

POFTDI0D000070

PIIC11039

NLFT

DI0D

0000

70

NLFTDI0D1

POFTDI0D000070

PIIC11040

NLFT

DI0D

0000

70

NLFTDI0D2

POFTDI0D000070

PIIC11041

NLFT

DI0D

0000

70

NLFTDI0D3

POFTDI0D000070

PIIC11043

NLFT

DI0D

0000

70

NLFTDI0D4

POFTDI0D000070

PIIC11044

NLFT

DI0D

0000

70

NLFTDI0D5

POFTDI0D000070

PIIC11045

NLFT

DI0D

0000

70

NLFTDI0D6

POFTDI0D000070

PIIC11046

NLFT

DI0D

0000

70

NLFTDI0D7

POFTDI0D000070

POFTDI0D0

POFTDI0D1

POFTDI0D2

POFTDI0D3

POFTDI0D4

POFTDI0D5

POFTDI0D6

POFTDI0D7

POFTDI0D000070

POFTDI0OE

POFTDI0RD

POFTDI0RXF

POFTDI0SIWUA

POFTDI0TXE

POFTDI0WR

POJTAG0TCK

POJTAG0TDI

POJTAG0TDO

POJTAG0TMS

XXVI

A Appendix

11

22

33

44

DD

CC

BB

AA

Tite

l:

Dat

um:

Seite

Entw

ickl

erkü

rzel

:Em

il-Fi

gge-

Straße

85,

442

27 D

ortm

und

FPG

A_AL

L.Sc

hDoc

03.0

9.20

18

15

SeD

a

FPG

A_A

LL.S

chD

oc

Adre

sse:

Zeit:

13:4

6:50

von

23Ve

rsio

n:

Proj

ekt:

VAD

ER_F

RG

A.Pr

jPcb

v1.0

JTA

G_T

DI

JTA

G_T

CK

JTA

G_T

MS

xSPI

_CS

xSPI

_D1

xSPI

_D2

xSPI

_D3

xSPI

_D0

JTA

G_T

DO

RES

ET

FPG

A_C

ON

FIG

FPG

A_C

ON

FIG

.Sch

Doc

xSPI

_D1

xSPI

_D2

xSPI

_D3

xSPI

_D0

xSPI

_CS

FTD

I_R

XF

FTD

I_TX

EFT

DI_

OE

FTD

I_W

RFT

DI_

RD

FTD

I_SI

WU

AFT

DI_

D[0

..7]

INC

_AIN

C_B

MO

N_I

NC

INP_

AIN

P_B

SSI_

CLK

SSI_

DTA

FPG

A_B

AN

KS0

FPG

A_B

AN

KS0

.Sch

Doc

FPG

A_P

OW

ERFP

GA

_PO

WER

.Sch

Doc

RX

OU

T_B

_[0.

.27]

RX

CLK

_B

DE_

SR

E_S

DIN

_S

RO

UT_

S

RX

OU

T_M

_[0.

.27]

RX

CLK

_M

LD[1

..4]

TEM

P_C

STE

MP_

SC

TEM

P_SI

TEM

P_SO

AN

Y_L

ED1B

AN

Y_L

ED2A

AN

Y_C

EA

NY

_MD

0A

NY

_OM

2A

NY

_OM

0A

NY

_LED

2BA

NY

_RX

AN

Y_L

ED1A

AN

Y_G

IP0

AN

Y_O

EA

NY

_RW

AN

Y_G

OP0

AN

Y_I

RQ

AN

Y_M

I1A

NY

_GO

P1A

NY

_MI0

AN

Y_R

ESET

AN

Y_G

IP1

AN

Y_O

M1

AN

Y_T

X

DIN

C[1

..4]

ENC

FPG

A_B

AN

KS1

FPG

A_B

AN

KS1

.Sch

Doc

FPG

A_G

TPFP

GA

_GTP

.Sch

Doc

DD

R3_

BA

[0..2

]

DD

R3_

CK

_N

DD

R3_

OD

TD

DR

3_W

ED

DR

3_C

AS

DD

R3_

RA

SD

DR

3_C

SD

DR

3_C

K_P

DD

R3_

CK

ED

DR

3_R

ESET

DD

R3_

DM

1D

DR

3_D

M0

DD

R3_

DQ

[0..1

5]D

DR

3_A

[0..1

3]

DD

R3_

DQ

S1_N

DD

R3_

DQ

S1_P

DD

R3_

DQ

S0_N

DD

R3_

DQ

S0_P

SPI2

_MO

SISP

I2_M

ISO

SPI2

_SC

S0SP

I2_C

LKR

ESET

STA

TM

CA

SP1A

MU

TE_R

MC

ASP

1FSX

MC

ASP

1AH

CLK

RM

CA

SP1A

CLK

RM

CA

SP1F

SRM

CA

SP1A

CLK

XM

CA

SP0A

HC

LKR

MC

ASP

0AC

LKX

MC

ASP

0FSX

MC

ASP

0FSR

MC

ASP

0AM

UTE

MC

ASP

0AC

LKR

MC

ASP

0AH

CLK

XM

CA

SP0A

XR

[0..1

5]M

CA

SP1A

XR

[0..9

]

FPG

A_B

AN

KS2

FPG

A_B

AN

KS2

.Sch

Doc

JTA

G_T

DI

JTA

G_T

DO

JTA

G_T

CK

JTA

G_T

MS

DD

R3_

A[0

..13]

DD

R3_

DQ

[0..1

5]

DD

R3_

OD

T

DD

R3_

CK

_N

DD

R3_

CK

ED

DR

3_C

K_P

DD

R3_

RES

ET

DD

R3_

CS

DD

R3_

RA

SD

DR

3_C

AS

DD

R3_

WE

DD

R3_

DQ

S0_P

DD

R3_

DQ

S0_N

DD

R3_

DQ

S1_P

DD

R3_

DQ

S1_N

DD

R3_

BA

[0..2

]

DD

R3_

DM

0D

DR

3_D

M1

DD

R3

DD

R3.

SchD

oc

DD

R3_

A[0

..13]

DIN

C[1

..4]

INP_

B

RE_

S

RX

CLK

_B

RO

UT_

S

RX

OU

T_B

_[0.

.27]

INC

_A

ENC

SSI_

CLK

INP_

A

RX

CLK

_M

DIN

_S

SSI_

DTA

INC

_B

RX

OU

T_M

_[0.

.27]

MO

N_I

NC

FTD

I_D

[0..7

]FT

DI_

SIW

UA

FTD

I_R

DFT

DI_

WR

FTD

I_O

EFT

DI_

TXE

FTD

I_R

XF

DE_

S

TEM

P_SO

TEM

P_SI

LD[1

..4]

TEM

P_C

STE

MP_

SC

AN

Y_T

XA

NY

_OM

1A

NY

_GIP

1A

NY

_RES

ETA

NY

_MI0

AN

Y_G

OP1

AN

Y_M

I1A

NY

_IR

QA

NY

_GO

P0A

NY

_RW

AN

Y_O

EA

NY

_GIP

0A

NY

_LED

1AA

NY

_RX

AN

Y_L

ED2B

AN

Y_O

M0

AN

Y_O

M2

AN

Y_M

D0

AN

Y_C

EA

NY

_LED

2AA

NY

_LED

1B

MC

ASP

1AX

R[0

..9]

MC

ASP

0AX

R[0

..15]

MC

ASP

0AH

CLK

XM

CA

SP0A

CLK

RM

CA

SP0A

MU

TEM

CA

SP0F

SRM

CA

SP0F

SXM

CA

SP0A

CLK

XM

CA

SP0A

HC

LKR

MC

ASP

1AC

LKX

MC

ASP

1FSR

MC

ASP

1AC

LKR

MC

ASP

1AH

CLK

R

SPI2

_CLK

SPI2

_SC

S0SP

I2_M

ISO

SPI2

_MO

SI

RES

ETST

AT

MC

ASP

1AM

UTE

_RM

CA

SP1F

SX

MC

ASP

A0A

MU

TE

MC

ASP

A0A

MU

TE

R18

0

n.b.

MA

STER

_RES

ETPIR1

8001

PI

R180

02

COR1

80

POANY0CE

POANY0GIP0

POANY0GIP1

POANY0GOP0

POANY0GOP1

POANY0IRQ

POANY0LED1A

POANY0LED1B

POANY0LED2A

POANY0LED2B

POANY0MD0

POANY0MI0

POANY0MI1

POANY0OE

POANY0OM0

POANY0OM1

POANY0OM2

POANY0RESET

POANY0RW

POANY0RX

POANY0TX

PODE0S

PODIN0S

POENC

POFTDI0OE

POFTDI0RD

POFTDI0RXF

POFTDI0SIWUA

POFTDI0TXE

POFTDI0WR

POINC0A

POINC0B

POINP0A

POINP0B

POJTAG0TCK

POJTAG0TDI

POJTAG0TDO

POJTAG0TMS

POMCASP0ACLKR

POMCASP0ACLKX

POMCASP0AHCLKR

POMCASP0AHCLKX

POMCASP0FSR

POMCASP0FSX

POMCASP1ACLKR

POMCASP1ACLKX

POMCASP1AHCLKR

POMCASP1AMUTE0R

POMCASP1FSR

POMCASP1FSX

PIR1

8002

NLMC

ASPA

0AMU

TE

POMCASP0AMUTE

POMON0INC

PIR1

8001

POMASTER0RESET

PORE0S

PORESETSTAT

POROUT0S

PORXCLK0B

PORXCLK0M

POSPI20CLK

POSPI20MISO

POSPI20MOSI

POSPI20SCS0

POSSI0CLK

POSSI0DTA

POTEMP0CS

POTEMP0SC

POTEMP0SI

POTEMP0SO

NLDDR30A0000130

NLDDR30A0000130

NLDDR30A0000130

NLDDR30A0000130

NLDDR30A0000130

NLDDR30A0000130

NLDDR30A0000130

NLDDR30A0000130

NLDDR30A0000130

NLDDR30A0000130

NLDDR30A0000130

NLDDR30A0000130

NLDDR30A0000130

NLDDR30A0000130

POANY0CE

POANY0GIP0

POANY0GIP1

POANY0GOP0

POANY0GOP1

POANY0IRQ

POANY0LED1A

POANY0LED1B

POANY0LED2A

POANY0LED2B

POANY0MD0

POANY0MI0

POANY0MI1

POANY0OE

POANY0OM0

POANY0OM1

POANY0OM2

POANY0RESET

POANY0RW

POANY0RX

POANY0TX

PODE0S

PODIN0S

PODINC1

PODINC2

PODINC3

PODINC4

PODINC010040

POENC

POFTDI0D0

POFTDI0D1

POFTDI0D2

POFTDI0D3

POFTDI0D4

POFTDI0D5

POFTDI0D6

POFTDI0D7

POFT

DI0D

0000

70

POFTDI0OE

POFTDI0RD

POFTDI0RXF

POFTDI0SIWUA

POFTDI0TXE

POFTDI0WR

POINC0A

POINC0B

POINP0A

POINP0B

POJTAG0TCK

POJTAG0TDI

POJTAG0TDO

POJTAG0TMS

POLD1

POLD2

POLD3

POLD4

POLD010040

POMASTER0RESET

POMCASP0ACLKR

POMCASP0ACLKX

POMCASP0AHCLKR

POMCASP0AHCLKX

POMCASP0AMUTE

POMCASP0AXR0

POMCASP0AXR1

POMCASP0AXR2

POMCASP0AXR3

POMCASP0AXR4

POMCASP0AXR5

POMCASP0AXR6

POMCASP0AXR7

POMCASP0AXR8

POMCASP0AXR9

POMCASP0AXR10

POMCASP0AXR11

POMCASP0AXR12

POMCASP0AXR13

POMCASP0AXR14

POMCASP0AXR15

POMCASP0AXR0000150

POMCASP0FSR

POMCASP0FSX

POMCASP1ACLKR

POMCASP1ACLKX

POMCASP1AHCLKR

POMCASP1AMUTE0R

POMCASP1AXR0

POMCASP1AXR1

POMCASP1AXR2

POMCASP1AXR3

POMCASP1AXR4

POMCASP1AXR5

POMCASP1AXR6

POMCASP1AXR7

POMCASP1AXR8

POMCASP1AXR9

POMCASP1AXR000090

POMCASP1FSR

POMCASP1FSX

POMON0INC

PORE0S

PORESETSTAT

POROUT0S

PORXCLK0B

PORXCLK0M

PORXOUT0B00

PORXOUT0B01

PORXOUT0B02

PORXOUT0B03

PORXOUT0B04

PORXOUT0B05

PORXOUT0B06

PORXOUT0B07

PORXOUT0B08

PORXOUT0B09

PORXOUT0B010

PORXOUT0B011

PORXOUT0B012

PORXOUT0B013

PORXOUT0B014

PORXOUT0B015

PORXOUT0B016

PORXOUT0B017

PORXOUT0B018

PORXOUT0B019

PORXOUT0B020

PORXOUT0B021

PORXOUT0B022

PORXOUT0B023

PORXOUT0B024

PORXOUT0B025

PORXOUT0B026

PORXOUT0B027

PORXOUT0B00000270

PORXOUT0M00

PORXOUT0M01

PORXOUT0M02

PORXOUT0M03

PORXOUT0M04

PORXOUT0M05

PORXOUT0M06

PORXOUT0M07

PORXOUT0M08

PORXOUT0M09

PORXOUT0M010

PORXOUT0M011

PORXOUT0M012

PORXOUT0M013

PORXOUT0M014

PORXOUT0M015

PORXOUT0M016

PORXOUT0M017

PORXOUT0M018

PORXOUT0M019

PORXOUT0M020

PORXOUT0M021

PORXOUT0M022

PORXOUT0M023

PORXOUT0M024

PORXOUT0M025

PORXOUT0M026

PORXOUT0M027

PORXOUT0M00000270

POSPI20CLK

POSPI20MISO

POSPI20MOSI

POSPI20SCS0

POSSI0CLK

POSSI0DTA

POTEMP0CS

POTEMP0SC

POTEMP0SI

POTEMP0SO

XXVII

A Appendix

11

22

33

44

DD

CC

BB

AA

Tite

l:

Dat

um:

Seite

Entw

ickl

erkü

rzel

:Em

il-Fi

gge-

Straße

85,

442

27 D

ortm

und

FPG

A_PO

WER

.Sch

Doc

03.0

9.20

18

16

SeD

a

FPG

A_P

OW

ER

.Sch

Doc

Adre

sse:

Zeit:

13:4

6:50

von

23Ve

rsio

n:

Proj

ekt:

VAD

ER_F

RG

A.Pr

jPcb

v1.0

GND D8

GND A2

GND A3

GND A5

GND A7

GND A9

GND A11

GND A12

GND A22

GNDAA2

GNDAA12

GNDAA22

GNDAB9

GNDAB19

GND B3

GND B12

GND B19

GND C3

GND C6

GND C10

GND C12

GND C16

GND D3

GND D4

GND D12

GND D13

GND E4

GND E5

GND E7

GND E9

GND E11

GND E20

GND F5

GND F11

GND F17

GND G5

GND G6

GND G7

GND G8

GND G9

GND G10

GND G12

GND G14

GND H1

GND H7

GND H9

GND H11

GND H21

GND J8

GNDJ10

GNDJ12

GNDJ18

GNDK5

GNDK7

GNDK11

GNDK15

GNDL2

GNDL8

GNDL22

GNDM7

GNDM11

GNDM19

GNDN6

GNDN8

GNDN16

GNDP3

GNDP7

GNDP9

GNDP11

GNDP13

GNDR8

GNDR10

GNDR12

GNDR20

GNDT7

GNDT9

GNDT11

GNDT17

GNDU4

GNDU14

GNDV1

GNDV11

GNDV21

GNDW8

GNDW18

GNDY5

GNDY15

GNDADC_0K9U

2K

XC

7A35

T-2F

GG

484I

VC

CO

_0T1

2

VC

CO

_13

AA

17

VC

CO

_13

AB

14

VC

CO

_13

V16

VC

CO

_13

W13

VC

CO

_13

Y10

VC

CO

_14

M14

VC

CO

_14

P18

VC

CO

_14

R15

VC

CO

_14

T22

VC

CO

_14

U19

VC

CO

_14

Y20

VC

CO

_15

G19

VC

CO

_15

H16

VC

CO

_15

J13

VC

CO

_15

K20

VC

CO

_15

L17

VC

CO

_15

N21

VC

CO

_16

A17

VC

CO

_16

B14

VC

CO

_16

C21

VC

CO

_16

D18

VC

CO

_16

E15

VC

CO

_16

F22

VC

CO

_34

AA

7

VC

CO

_34

AB

4

VC

CO

_34

R5

VC

CO

_34

T2

VC

CO

_34

V6

VC

CO

_34

W3

VC

CO

_35

C1

VC

CO

_35

F2

VC

CO

_35

H6

VC

CO

_35

J3

VC

CO

_35

M4

VC

CO

_35

N1

VC

CO

_0F1

2U

2I

XC

7A35

T-2F

GG

484I

VC

CIN

TH

8

VC

CIN

TH

10

VC

CIN

TJ7

VC

CIN

TJ9

VC

CIN

TK

8

VC

CIN

TL7

VC

CIN

TM

8

VC

CIN

TN

7

VC

CIN

TP8

VC

CIN

TP1

0

VC

CIN

TR

7

VC

CIN

TR

9

VC

CIN

TT8

VC

CIN

TT1

0

VC

CA

UX

H12

VC

CA

UX

K12

VC

CA

UX

M12

VC

CA

UX

P12

VC

CA

UX

R11

VC

CB

RA

MJ1

1

VC

CB

RA

ML1

1

VC

CB

RA

MN

11

VC

CA

DC

_0K

10

VC

CB

ATT

_0E1

2U

2J

XC

7A35

T-2F

GG

484I

1V0

1V8

1V0

1V35

GN

D

GN

D

1V8

C10

147

uC

102

4u7

C10

310

0n

C16

610

nC

165

470n

C16

44u

7

GN

DG

ND

1V8

XA

DC

1V8

XA

DC

1V8

C18

910

0nC

190

100n

C19

247

uC

191

470n

C16

810

0uC

169

4u7

C17

04u

7C

171

470n

C17

247

0nC

173

470n

C18

410

0nC

185

100n

C18

610

0nC

187

100n

C18

810

0n

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

D

C17

410

0nC

175

100n

C17

647

0nC

177

470n

C17

847

0nC

179

470n

C18

047

0nC

181

4u7

C18

24u

7C

183

47u

C13

410

0nC

135

100n

C13

610

0nC

137

470n

C13

847

0nC

139

470n

C14

047

0nC

141

4u7

C14

24u

7C

143

47u

C10

410

0nC

105

100n

C10

610

0nC

107

470n

C10

847

0nC

109

470n

C11

047

0nC

111

4u7

C11

24u

7C

113

47u

C15

410

0nC

155

100n

C15

610

0nC

157

470n

C15

847

0nC

159

470n

C16

047

0nC

161

4u7

C16

24u

7C

163

47u

C13

310

0nC

132

100n

C13

110

0nC

130

470n

C12

947

0nC

128

470n

C12

747

0nC

126

4u7

C12

54u

7C

124

47u

C15

310

0nC

152

100n

C15

110

0nC

150

470n

C14

947

0nC

148

470n

C14

747

0nC

146

4u7

C14

54u

7C

144

47u

C12

310

0nC

122

100n

C12

110

0nC

120

470n

C11

947

0nC

118

470n

C11

747

0nC

116

4u7

C11

54u

7C

114

47u

GN

DG

ND

GN

D

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

3V3

3V3

3V3

3V3

C16

710

0n

IO B

ank

Supp

ly

Cor

e Su

pply

XA

DC

Filt

er

GN

D S

uppl

yL5 600R

@ 1

00M

Hz

3V3

3V3

GN

D

GN

D

PIC10101 PIC10102 COC101 PIC10201 PIC10202

COC1

02 PIC10301 PIC10302

COC1

03


C104

PIC10501 PIC10502 COC105 PIC1060

1 PIC10602 CO

C106


C107


C108


C109

PIC11001 PIC11002 COC110 PIC1110

1 PIC11102 CO

C111


C112


C113

PIC11401 PIC11402 COC114 PIC11501

PIC11502

COC1

15 PIC11601 PIC11602

COC1

16 PIC11701

PIC11702

COC1

17 PIC11801 PIC11802

COC1

18 PIC11901 PIC11902

COC119 PIC12001

PIC12002

COC1

20 PIC12101 PIC12102

COC1

21 PIC12201

PIC12202

COC1

22 PIC12301 PIC12302

COC1

23

PIC12401 PIC12402 COC124 PIC1250

1 PIC1250

2 COC1

25 PIC12601 PIC12602

COC1

26 PIC1270

1 PIC1270

2 COC1

27 PIC12801 PIC12802

COC1

28 PIC12901 PIC12902

COC129 PIC1300

1 PIC1300

2 COC1

30 PIC13101 PIC13102

COC1

31 PIC1320

1 PIC1320

2 COC1

32 PIC13301 PIC13302

COC1

33


C134

PIC13501 PIC13502 COC135 PIC1360

1 PIC1360

2 COC1

36 PIC13701 PIC13702

COC1

37 PIC1380

1 PIC1380

2 COC1

38 PIC13901 PIC13902

COC1

39 PIC14001 PIC14002

COC140 PIC1410

1 PIC1410

2 COC1

41 PIC14201 PIC14202

COC1

42 PIC1430

1 PIC1430

2 COC1

43

PIC14401 PIC14402 COC144 PIC1450

1 PIC1450

2 COC1

45 PIC14601 PIC14602

COC1

46 PIC1470

1 PIC1470

2 COC1

47 PIC14801 PIC14802

COC1

48 PIC14901 PIC14902

COC149 PIC1500

1 PIC1500

2 COC1

50 PIC15101 PIC15102

COC1

51 PIC1520

1 PIC1520

2 COC1

52 PIC15301 PIC15302

COC1

53


C154

PIC15501 PIC15502 COC155 PIC1560

1 PIC1560

2 COC1

56 PIC15701 PIC15702

COC1

57 PIC1580

1 PIC1580

2 COC1

58 PIC15901 PIC15902

COC1

59 PIC16001 PIC16002

COC160 PIC1610

1 PIC1610

2 COC1

61 PIC16201 PIC16202

COC1

62 PIC1630

1 PIC1630

2 COC1

63


C164

PIC1650

1 PIC16502 CO

C165


C166


C167


C168

PIC16901 PIC16902 COC169 PIC17001

PIC17002

COC1

70 PIC17101 PIC17102

COC1

71 PIC17201

PIC17202

COC1

72 PIC17301 PIC17302

COC1

73

PIC17401 PIC17402 COC174 PIC17501

PIC17502

COC1

75 PIC17601 PIC17602

COC1

76 PIC17701

PIC17702

COC1

77 PIC17801 PIC17802

COC1

78 PIC17901 PIC17902

COC179 PIC18001

PIC18002

COC1

80 PIC18101 PIC18102

COC1

81 PIC18201

PIC18202

COC1

82 PIC18301 PIC18302

COC1

83

PIC18401 PIC18402 COC184 PIC1850

1 PIC18502 CO

C185


C186


C187


C188


C189


C190

PIC19101 PIC19102 COC191 PIC1920

1 PIC19202 CO

C192

PIL5

01

PIL5

02

COL5

PIU20A17

PIU20AA7

PIU20AA17

PIU20AB4

PIU20AB14

PIU20B14

PIU20C1

PIU20C21

PIU20D18

PIU20E15

PIU20F2

PIU20F12

PIU20F22

PIU20G19

PIU20H6

PIU20H16

PIU20J3

PIU20J13

PIU20K20

PIU20L17

PIU20M4

PIU20M14

PIU20N1

PIU20N21

PIU20P18

PIU20R5

PIU20R15

PIU20T2

PIU20T12

PIU20T22

PIU20U19

PIU20V6

PIU20V16

PIU20W3

PIU20W13

PIU20Y10

PIU20Y20 COU2

I

PIU20E12

PIU20H8

PIU20H10

PIU20H12

PIU20J7

PIU20J9

PIU20J11

PIU20K8

PIU20K10

PIU20K12

PIU20L7

PIU20L11

PIU20M8

PIU20M12

PIU20N7

PIU20N11

PIU20P8

PIU20P10

PIU20P12

PIU20R7

PIU20R9

PIU20R11

PIU20T8

PIU20T10 COU2

J

PIU20A2 PIU20A3 PIU20A5 PIU20A7


PIU20AA2 PIU20AA12 PIU20AA22 PIU20AB9

PIU20AB19

PIU20B3 PIU20B12 PIU20B19 PIU20C3

PIU20C6 PIU20C10 PIU20C12 PIU20C16

PIU20D3 PIU20D4 PIU20D8 PIU20D12

PIU20D13 PIU20E4 PIU20E5 PIU20E7

PIU20E9 PIU20E11 PIU20E20 PIU20F5

PIU20F11 PIU20F17 PIU20G5 PIU20G6

PIU20G7 PIU20G8 PIU20G9 PIU20G10

PIU20G12 PIU20G14 PIU20H1 PIU20H7

PIU20H9 PIU20H11 PIU20H21 PIU20J8

PIU20J10 PIU20J12 PIU20J18 PIU20K5

PIU20K7 PIU20K9

PIU20K11 PIU20K15 PIU20L2 PIU20L8

PIU20L22 PIU20M7 PIU20M11 PIU20M19

PIU20N6 PIU20N8 PIU20N16 PIU20P3

PIU20P7 PIU20P9 PIU20P11 PIU20P13

PIU20R8 PIU20R10 PIU20R12 PIU20R20

PIU20T7 PIU20T9 PIU20T11 PIU20T17

PIU20U4 PIU20U14 PIU20V1 PIU20V11

PIU20V21 PIU20W8 PIU20W18 PIU20Y5

PIU20Y15

COU2

K

PIC16801 PIC16901

PIC17001

PIC17101 PIC17201

PIC17301

PIC18401 PIC1850

1 PIC18601

PIC18701

PIC18801

PIC18901 PIC19001

PIC19101 PIC1920

1

PIU20H8

PIU20H10

PIU20J7

PIU20J9

PIU20J11

PIU20K8

PIU20L7

PIU20L11

PIU20M8

PIU20N7

PIU20N11

PIU20P8

PIU20P10

PIU20R7

PIU20R9

PIU20T8

PIU20T10

PIC16401

PIC17401 PIC17501

PIC17601

PIC17701

PIC17801 PIC17901

PIC18001

PIC18101 PIC18201

PIC18301

PIL5

01

PIU20E12

PIU20H12

PIU20K12

PIU20M12

PIU20P12

PIU20R11

PIC15401 PIC15501

PIC15601

PIC15701 PIC1580

1 PIC15901

PIC16001 PIC1610

1 PIC16201

PIC16301

PIU20C1

PIU20F2

PIU20H6

PIU20J3

PIU20M4

PIU20N1

PIC10101 PIC10201

PIC10301

PIC10401 PIC10501

PIC10601

PIC10701 PIC1080

1 PIC10901

PIC11001 PIC1110

1 PIC11201

PIC11301

PIC11402 PIC11502

PIC11602

PIC11702

PIC11802 PIC11902

PIC12002

PIC12102 PIC12202

PIC12302

PIC12402 PIC1250

2 PIC12602

PIC12702

PIC12802 PIC12902

PIC13002

PIC13102 PIC1320

2 PIC13302

PIC13401 PIC13501

PIC13601

PIC13701 PIC1380

1 PIC13901

PIC14001 PIC1410

1 PIC14201

PIC14301

PIC14402 PIC1450

2 PIC14602

PIC14702

PIC14802 PIC14902

PIC15002

PIC15102 PIC1520

2 PIC15302

PIU20A17

PIU20AA7

PIU20AA17

PIU20AB4

PIU20AB14

PIU20B14

PIU20C21

PIU20D18

PIU20E15

PIU20F12

PIU20F22

PIU20G19

PIU20H16

PIU20J13

PIU20K20

PIU20L17

PIU20M14

PIU20N21

PIU20P18

PIU20R5

PIU20R15

PIU20T2

PIU20T12

PIU20T22

PIU20U19

PIU20V6

PIU20V16

PIU20W3

PIU20W13

PIU20Y10

PIU20Y20

PIC10102 PIC10202

PIC10302

PIC10402 PIC10502

PIC10602

PIC10702 PIC10802

PIC10902

PIC11002 PIC11102

PIC11202

PIC11302

PIC11401 PIC11501

PIC11601

PIC11701

PIC11801 PIC11901

PIC12001

PIC12101 PIC12201

PIC12301

PIC12401 PIC1250

1 PIC12601

PIC12701

PIC12801 PIC12901

PIC13001

PIC13101 PIC1320

1 PIC13301

PIC13402 PIC13502

PIC13602

PIC13702 PIC1380

2 PIC13902

PIC14002 PIC1410

2 PIC14202

PIC14302

PIC14401 PIC1450

1 PIC14601

PIC14701

PIC14801 PIC14901

PIC15001

PIC15101 PIC1520

1 PIC15301

PIC15402 PIC15502

PIC15602

PIC15702 PIC1580

2 PIC15902

PIC16002 PIC1610

2 PIC16202

PIC16302

PIC16402

PIC16502

PIC16602 PIC16702

PIC16802

PIC16902 PIC17002

PIC17102

PIC17202

PIC17302

PIC17402 PIC17502

PIC17602

PIC17702

PIC17802 PIC17902

PIC18002

PIC18102 PIC18202

PIC18302

PIC18402 PIC18502

PIC18602

PIC18702

PIC18802

PIC18902 PIC19002

PIC19102 PIC19202




PIU20AB19

PIU20B3 PIU20B12 PIU20B19 PIU20C3

PIU20C6 PIU20C10 PIU20C12 PIU20C16

PIU20D3 PIU20D4 PIU20D8 PIU20D12

PIU20D13 PIU20E4 PIU20E5 PIU20E7

PIU20E9 PIU20E11 PIU20E20 PIU20F5

PIU20F11 PIU20F17 PIU20G5 PIU20G6

PIU20G7 PIU20G8 PIU20G9 PIU20G10

PIU20G12 PIU20G14 PIU20H1 PIU20H7

PIU20H9 PIU20H11 PIU20H21 PIU20J8

PIU20J10 PIU20J12 PIU20J18 PIU20K5

PIU20K7 PIU20K9

PIU20K11 PIU20K15 PIU20L2 PIU20L8

PIU20L22 PIU20M7 PIU20M11 PIU20M19

PIU20N6 PIU20N8 PIU20N16 PIU20P3

PIU20P7 PIU20P9 PIU20P11 PIU20P13

PIU20R8 PIU20R10 PIU20R12 PIU20R20

PIU20T7 PIU20T9 PIU20T11 PIU20T17

PIU20U4 PIU20U14 PIU20V1 PIU20V11

PIU20V21 PIU20W8 PIU20W18 PIU20Y5

PIU20Y15

PIC16501

PIC16601 PIC1670

1 PI

L502

PIU20K10

XXVIII

A Appendix

11

22

33

44

DD

CC

BB

AA

Tite

l:

Dat

um:

Seite

Entw

ickl

erkü

rzel

:Em

il-Fi

gge-

Straße

85,

442

27 D

ortm

und

FPG

A_G

TP.S

chD

oc

03.0

9.20

18

17

SeD

a

FPG

A_G

TP.S

chD

oc

Adre

sse:

Zeit:

13:4

6:50

von

23Ve

rsio

n:

Proj

ekt:

VAD

ER_F

RG

A.Pr

jPcb

v1.0

MG

TRR

EF_2

16F8

MG

TREF

CLK

0N_2

16E6

MG

TREF

CLK

0P_2

16F6

MG

TPR

XP1

_216

D11

MG

TPR

XP2

_216

B10

MG

TPR

XP3

_216

D9

MG

TPR

XP0

_216

B8

MG

TPTX

P3_2

16D

7

MG

TPTX

P2_2

16B

6

MG

TREF

CLK

1P_2

16F1

0

MG

TREF

CLK

1N_2

16E1

0

MG

TPR

XN

1_21

6C

11

MG

TPR

XN

2_21

6A

10

MG

TPR

XN

3_21

6C

9

MG

TPR

XN

0_21

6A

8

MG

TPTX

N3_

216

C7

MG

TPTX

N2_

216

A6

MG

TPTX

P1_2

16D

5

MG

TPTX

N1_

216

C5

MG

TPTX

P0_2

16B

4

MG

TPTX

N0_

216

A4

U2G

XC

7A35

T-2F

GG

484I

MG

TAV

CC

D6

MG

TAV

CC

D10

MG

TAV

CC

F7

MG

TAV

CC

F9

MG

TAV

CC

E8

MG

TAV

TTB

5

MG

TAV

TTB

7

MG

TAV

TTB

9

MG

TAV

TTB

11

MG

TAV

TTC

4

MG

TAV

TTC

8

U2H

XC

7A35

T-2F

GG

484I

VC

C3V

3

C20

910

nC

208

100n

C21

110

u

R14

7

10R

C21

010

n

VD

DA

_SA

TAC

LK

VD

DA

1

GN

D2

XTA

L_O

UT

3

XTA

L_IN

4

FREQ

_SEL

5

nQ6

Q7

VD

D8

IC25

IC84

4071

VD

DA

_SA

TAC

LKV

DD

A_S

ATA

CLK

R14

9n.

b.

SATA

CLK

_P

SATA

CLK

_NR

148

1M0

X2

25.0

00 M

Hz

C21

422

pC

213

22p

n.B

. = 7

5 M

Hz

0R =

150

MH

z

C19

410

0nC

195

100n

C19

610

0nC

197

100n

1V2_

GTP

1V0_

GTP

GN

DG

ND

GN

DG

ND

GN

DG

ND

C19

34u

7C

198

4u7

SATA

CLK

_PSA

TAC

LK_N

1V2_

GTP

R14

6

100R

Unu

sed

Floa

t

GN

DA

ccor

ding

toU

G48

2

C20

7

100n

C21

2

100nGN

DA

+A

-G

ND

B-

B+

GN

DSH

IELD

SHIE

LD

J13

GN

DA

+A

-G

ND

B-

B+

GN

DSH

IELD

SHIE

LD

J14

SATA

_RX

2_P

SATA

_RX

2_N

SATA

_TX

2_N

SATA

_TX

2_P

R15

6n.

b.R

157

n.b.

R15

4n.

b.R

155

n.b.

GN

DG

ND

GN

D

GN

DG

ND

GN

D

SATA

_RX

1_P

SATA

_RX

1_N

SATA

_RX

2_P

SATA

_RX

2_N

SATA

_TX

1_P

SATA

_TX

1_N

SATA

_TX

2_N

SATA

_TX

2_P

C20

4

100n

C20

3

100n

C19

910

0nC

200

100n

C20

110

0nC

202

100n

SATA

_RX

1_P

SATA

_RX

1_N

SATA

_TX

1_P

SATA

_TX

1_N

C20

6

100n

C20

5

100n

3V3

5V0

GN

D

2 3 41 5 6

J16

1x6

C23

610

0u

C23

510

0u

GN

D

GN

D

Sata

Clo

ckSS

D-P

ower

supp

ly

GTP

-Por

tSa

ta C

onne

ctor

s

L7 600R

@ 1

00M

Hz

L8 600R

@ 1

00M

Hz

L9 600R

@ 1

00M

Hz

iSA

TA

ISA

TA_R

X1_

PIS

ATA

_RX

1_N

ISA

TA_T

X1_

PIS

ATA

_TX

1_N

ISA

TA_R

X2_

PIS

ATA

_RX

2_N

ISA

TA_T

X2_

NIS

ATA

_TX

2_P

SCLK

_P

SCLK

_N

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

PIC19301 PIC19302 COC193

PIC19401

PIC19402 CO

C194


C195

PIC19601 PIC19602

COC1

96 PIC1970

1 PIC1970

2 COC1

97 PIC19801 PIC19802

COC1

98

PIC199

01 PIC

19902

COC1

99

PIC200

01 PIC

20002

COC200

PIC201

01 PI

C201

02

COC2

01

PIC202

01 PIC

20202

COC202

PIC203

01 PIC

20302

COC203

PIC2

0401

PIC20

402

COC2

04

PIC205

01 PIC

20502

COC2

05

PIC206

01 PIC

20602

COC206

PIC207

01 PIC

20702 CO

C207

PIC2080

1 PIC20802 CO

C208


C209

PIC21001 PIC21002

COC2

10 PIC21101 PIC21102

COC2

11

PIC212

01 PIC

21202 CO

C212


C213

PIC21401 PIC21402 COC214


C235

PIC23601 PIC23602 COC236

PIIC2501

PIIC2502

PIIC2503

PIIC2504

PIIC2505

PIIC2506

PIIC2507

PIIC2508

COIC25

PIJ1301

PIJ1302

PIJ1303

PIJ1304

PIJ1305

PIJ1306

PIJ1307

PIJ1308

PIJ1309

COJ13

PIJ1401

PIJ1402

PIJ1403

PIJ1404

PIJ1405

PIJ1406

PIJ1407

PIJ1408

PIJ1409

COJ14

PIJ1601

PIJ1602

PIJ1603

PIJ1604

PIJ1605

PIJ1606 COJ

16

PIL7

01

PIL7

02

COL7

PIL8

01

PIL8

02

COL8

PIL9

01

PIL9

02

COL9

PIR1

4601

PI

R146

02 COR1

46

PIR1

4701

PIR14702

COR1

47

PIR14801 PIR14802 COR148


R149


R154


R155


R156


R157

PIU20A4

PIU20A6

PIU20A8

PIU20A10

PIU20B4

PIU20B6

PIU20B8

PIU20B10

PIU20C5

PIU20C7

PIU20C9

PIU20C11

PIU20D5

PIU20D7

PIU20D9

PIU20D11

PIU20E6

PIU20E10

PIU20F6

PIU20F8

PIU20F10

COU2

G

PIU20B5

PIU20B7

PIU20B9

PIU20B11

PIU20C4

PIU20C8

PIU20D6

PIU20D10

PIU20E8

PIU20F7

PIU20F9

COU2

H

PIX201

PIX202 CO

X2

PIL8

02

PIL7

01

PIR1

4602

PIC23501 PIJ1601

PIJ1602

PIC23601 PIJ1603

PIJ1604 PIC19301

PIC19401

PIC19501 PIC19601

PIC19701

PIC19801

PIC20802

PIC20902 PIC21002

PIC21102

PIC21302 PIC21402

PIC23502

PIC23602 PIIC2502

PIJ1301

PIJ1304

PIJ1307

PIJ1401

PIJ1404

PIJ1407

PIJ1605

PIJ1606

PIR14901

PIR15401 PIR15501

PIR15601 PIR15701

PIU20A10

PIU20B10

PIU20C9

PIU20D9

PIC202

01 PIJ1306

NLISATA0RX10N

PIC201

01 PIJ1305

NLIS

ATA0

RX10

P

PIC206

02 PIJ1406

NLISATA0RX20N

PIC205

02 PIJ1405

NLIS

ATA0

RX20

P

PIC200

01 PIJ1303

NLISATA0TX10N

PIC199

01 PIJ1302

NLIS

ATA0

TX10

P

PIC204

02 PIJ1403

NLISATA0TX20N

PIC203

02 PIJ1402

NLIS

ATA0

TX20

P

PIC19302 PIC1940

2 PIC19502

PIL7

02

PIU20B5

PIU20B7

PIU20B9

PIU20B11

PIU20C4

PIU20C8

PIC19602 PIC1970

2 PIC19802

PIL8

01

PIU20D6

PIU20D10

PIU20E8

PIU20F7

PIU20F9

PIC20801

PIC20901 PI

L902

PI

R147

01

PIC21301

PIIC2503

PIR14802 PIX202

PIC21401

PIIC2504

PIR14801 PIX201

PIIC2505 PIR14902

PIJ1308

PIR15502 PIJ1309 PIR15402

PIJ1408

PIR15702 PIJ1409 PIR15602

PIR1

4601

PIU20F8

PIU20A6

PIU20B6

PIU20C7

PIU20D7

PIU20E10

PIU20F10

PIC202

02

PIU20A8

NLSATA0RX10N

PIC2

0102

PIU20B8

NLSATA0RX10P

PIC206

01

PIU20C11

NLSATA0RX20N

PIC205

01

PIU20D11

NLSATA0RX20P

PIC200

02

PIU20A4

NLSATA0TX10N

PIC199

02

PIU20B4

NLSATA0TX10P PI

C204

01

PIU20C5

NLSATA0TX20N

PIC203

01 PIU20D5

NLSATA0TX20P

PIC212

01

PIU20E6

NLSA

TACL

K0N

PIC207

01

PIU20F6

NLSA

TACL

K0P

PIC212

02 PIIC2506 NLSCLK0N

PIC207

02

PIIC2507 NLSCLK0P

PIL9

01

PIC21001 PIC21101

PIIC2501

PIIC2508

PIR14702

XXIX

A Appendix

11

22

33

44

DD

CC

BB

AA

Tite

l:

Dat

um:

Seite

Entw

ickl

erkü

rzel

:Em

il-Fi

gge-

Straße

85,

442

27 D

ortm

und

FPG

A_C

ON

FIG

.Sch

Doc

03.0

9.20

18

18

SeD

a

FPG

A_C

ON

FIG

.Sch

Doc

Adre

sse:

Zeit:

13:4

6:50

von

23Ve

rsio

n:

Proj

ekt:

VAD

ER_F

RG

A.Pr

jPcb

v1.0

DO

NE_

0G

11

DX

P_0

N10

VR

EFP_

0M

10

VN

_0M

9

TCK

_0V

12

DX

N_0

N9

VR

EFN

_0L9

VP_

0L1

0

CC

LK_0

L12

M0_

0U

11

M1_

0U

10

INIT

_B_0

U12

TDI_

0R

13

TDO

_0U

13

M2_

0U

9

CFG

BV

S_0

U8

PRO

GR

AM

_B_0

N12

TMS_

0T1

3

U2F

XC

7A35

T-2F

GG

484I

3V3 C

100

100n

GN

D

GN

D

R13

2

100R

R13

6

100R

R13

5

100R

R13

4

100R

R13

3

100R

R13

14k

7R

130

4k7

R12

92k

4

3V3

3V3

3V3

JTA

G_T

DI

JTA

G_T

DO

JTA

G_T

CK

JTA

G_T

MS

R14

52k

2

3V3

3V3

MO

DE0

MO

DE1

MO

DE2

GN

D

MO

DE2

3V

3 JT

AG

MO

DE2

0V

SPI

1 2

J11

1x2

GN

D

JTAG

x4 SPI

GN

D

MO

DE0

MO

DE1

MO

DE2

R14

31k

0

R13

810

0R D13

LTST

-S27

0KG

KT

3V3

GN

D

R14

14k

7

PRO

GR

AM

_B

PRO

GR

AM

_B

3V3

R14

04k

7IN

IT_B

3V3

INIT

_B

R14

24k

7

3V3

CFG

BV

S

CFG

BV

S

JTA

G_T

DI

JTA

G_T

DO

JTA

G_T

CK

JTA

G_T

MS

R14

41k

0

xSPI

_CS

xSPI

_D1

xSPI

_D2

xSPI

_D3

xSPI

_D0

12 4

3 56

J12

2x3

I/O1

1I/O

16

I/O2

3I/O

24

D15

A

8240

0102

3V3

GN

D

JTA

G_T

DI

JTA

G_T

DO

I/O1

1I/O

16

I/O2

3I/O

24

D14

A

8240

0102

JTA

G_T

CK

JTA

G_T

MS

R15

1

100R

R15

3

100R

R15

0

100R

R15

2

100R

GN

D2

VD

D5

D14

B

8240

0102

GN

D2

VD

D5

D15

B

8240

0102

3V3

3V3

GN

DG

ND

RES

ET

Con

figur

atio

n

CC

LK_0

CC

LK_0

JTA

G C

onne

ctor

SPI F

lash

Boo

t Mod

e

R13

733

0RC

S#1

SO /

IO1

2

WP#

/ IO

23

GND 4

SI /

IO0

5

SCK

6

IO3/

RES

ET#

7

VDD8

PAD 9

IC23

IS25

LP12

8

GN

D

PIC10001 PIC10002 COC100

PID1301

PID1302

COD13

PID1401

PID1403

PID1

404

PID1406 COD1

4A

PID1402

PID1405

COD1

4B

PID1501

PID1503

PID1

504

PID1506 COD1

5A

PID1502

PID1505

COD1

5B

PIIC2301

PIIC2302

PIIC2303

PIIC2304

PIIC2305

PIIC2306

PIIC2307

PIIC2308

PIIC2309

COIC23

PIJ1101

PIJ1102

COJ11

PIJ1201

PIJ1202

PIJ1203

PIJ1204

PIJ1205

PIJ1206

COJ12


R129


30 PIR13101 PIR13102

COR1

31

PIR1

3201

PI

R132

02

COR1

32

PIR1

3301

PI

R133

02

COR1

33

PIR134

01 PIR

13402

COR1

34

PIR1

3501

PI

R135

02

COR1

35

PIR1

3601

PI

R136

02

COR1

36


R137


R138


R140


R141


R142


R143


R144


R145

PIR1

5001

PI

R150

02

COR150

PIR1

5101

PI

R151

02

COR1

51

PIR152

01 PIR

15202

COR1

52

PIR153

01 PIR15302

COR1

53

PIU20G11

PIU20L9

PIU20L10

PIU20L12

PIU20M9

PIU20M10

PIU20N9

PIU20N10

PIU20N12

PIU20R13

PIU20T13

PIU20U8

PIU20U9

PIU20U10

PIU20U11

PIU20U12

PIU20U13

PIU20V12

COU2F

PIC10001

PID1405

PID1505

PIIC2308

PIJ1205

PIR12902 PIR13002

PIR13102

PIR13702

PIR14002 PIR14102

PIR14202

PIR14302 PIR14402

PIIC2306

PIU20L12

NLCCLK00

PIR14201

PIU20U8

NLCFGBVS

PIC10002

PID1302

PID1402

PID1502

PIIC2304 PIIC2309

PIJ1102

PIJ1206

PIR14501

PIU20L9

PIU20L10

PIU20M9

PIU20M10

PIU20N9

PIU20N10

PIR14001

PIU20U12

NLINIT0B

PORESET

PIR1

5001

PIU20V12 NLJT

AG0T

CK POJTAG0TCK

PIR1

5102

PIU20R13

NLJTAG0TDI

POJTAG0TDI

PIR15302

PIU20U13

NLJT

AG0T

DO

POJTAG0TDO

PIR152

01

PIU20T13 NLJT

AG0T

MS POJTAG0TMS

PIR14401

PIU20U11

NLMO

DE0

PIR14502

PIU20U10

NLMO

DE1

PIJ1101 PIR14301

PIU20U9

NLMO

DE2

PID1301 PIR13801

PID1401

PIJ1201

PID1403

PIJ1203

PID1

404

PIR152

02

PID1406

PIR1

5002

PID1501

PIR1

5101

PID1503

PIR153

01 PI

D150

4 PIJ1204

PID1506

PIJ1202

PIIC2301

PIR1

3202

PIIC2302

PIR1

3302

PIIC2303

PIR134

02

PIIC2305

PIR1

3502

PIIC2307

PIR1

3602

PIR12901

PIR1

3201

POxSPI0CS

PIR13001

PIR134

01 POxSPI0D2

PIR13101

PIR1

3601

POxSPI0D3

PIR1

3301

POxSPI0D1

PIR1

3501

POxSPI0D0

PIR13701 PIR13802 PIU20G11

PIR14101

PIU20N12

NLPROGRAM0B

POJTAG0TCK

POJTAG0TDI

POJTAG0TDO

POJTAG0TMS

PORESET

POXSPI0CS

POXSPI0D0

POXSPI0D1

POXSPI0D2

POXSPI0D3

XXX

A Appendix

11

22

33

44

DD

CC

BB

AA

Tite

l:

Dat

um:

Seite

Entw

ickl

erkü

rzel

:Em

il-Fi

gge-

Straße

85,

442

27 D

ortm

und

FPG

A_BA

NKS

0.Sc

hDoc

03.0

9.20

18

19

SeD

a

FPG

A_B

AN

KS

0.S

chD

oc

Adre

sse:

Zeit:

13:4

6:50

von

23Ve

rsio

n:

Proj

ekt:

VAD

ER_F

RG

A.Pr

jPcb

v1.0

xSPI

_CS

xSPI

_D1

xSPI

_D2

xSPI

_D3

xSPI

_D0

GN

DR12

71k

0

3V3 R

128

n.b.

IO_L

11P_

T1_S

RC

C_1

4U

20

IO_L

1P_T

0_D

00_M

OSI

_14

P22

IO_L

1N_T

0_D

01_D

IN_1

4R

22

IO_L

2P_T

0_D

02_1

4P2

1

IO_L

2N_T

0_D

03_1

4R

21

IO_L

3P_T

0_D

QS_

PUD

C_B

_14

U22

IO_L

3N_T

0_D

QS_

EMC

CLK

_14

V22

IO_L

4P_T

0_D

04_1

4T2

1

IO_L

4N_T

0_D

05_1

4U

21

IO_L

10P_

T1_D

14_1

4A

B21

IO_L

5N_T

0_D

07_1

4R

19

IO_L

6P_T

0_FC

S_B

_14

T19

IO_L

6N_T

0_D

08_V

REF

_14

T20

IO_L

7P_T

1_D

09_1

4W

21

IO_L

7N_T

1_D

10_1

4W

22

IO_L

8P_T

1_D

11_1

4A

A20

IO_L

8N_T

1_D

12_1

4A

A21

IO_L

9P_T

1_D

QS_

14Y

21

IO_L

10N

_T1_

D15

_14

AB

22

IO_L

5P_T

0_D

06_1

4P1

9

IO_0

_14

P20

IO_L

11N

_T1_

SRC

C_1

4V

20

IO_L

12P_

T1_M

RC

C_1

4W

19

IO_L

9N_T

1_D

QS_

D13

_14

Y22

IO_L

12N

_T1_

MR

CC

_14

W20

IO_L

13P_

T2_M

RC

C_1

4Y

18

IO_L

13N

_T2_

MR

CC

_14

Y19

IO_L

14P_

T2_S

RC

C_1

4V

18

IO_L

14N

_T2_

SRC

C_1

4V

19

IO_L

15P_

T2_D

QS_

RD

WR

_B_1

4A

A19

IO_L

15N

_T2_

DQ

S_D

OU

T_C

SO_B

_14

AB

20

IO_L

16P_

T2_C

SI_B

_14

V17

IO_L

16N

_T2_

A15

_D31

_14

W17

IO_L

17P_

T2_A

14_D

30_1

4A

A18

IO_L

17N

_T2_

A13

_D29

_14

AB

18

IO_L

18P_

T2_A

12_D

28_1

4U

17

IO_L

19P_

T3_A

10_D

26_1

4P1

4

IO_L

23P_

T3_A

03_D

19_1

4N

13

IO_L

23N

_T3_

A02

_D18

_14

N14

IO_L

19N

_T3_

A09

_D25

_VR

EF_1

4R

14

IO_2

5_14

N15

IO_L

22P_

T3_A

05_D

21_1

4P1

5

IO_L

21P_

T3_D

QS_

14N

17

IO_L

21N

_T3_

DQ

S_A

06_D

22_1

4P1

7

IO_L

20P_

T3_A

08_D

24_1

4R

18

IO_L

24P_

T3_A

01_D

17_1

4P1

6

IO_L

20N

_T3_

A07

_D23

_14

T18

IO_L

24N

_T3_

A00

_D16

_14

R17

IO_L

18N

_T2_

A11

_D27

_14

U18

IO_L

22N

_T3_

A04

_D20

_14

R16

BANK 14

U2A

XC

7A35

T-2F

GG

484I

FTD

I_TX

EFT

DI_

RX

FFT

DI_

D[0

..7]

FTD

I_SI

WU

AFT

DI_

RD

FTD

I_W

RFT

DI_

OE

FTD

I_D

0FT

DI_

D1

FTD

I_D

2FT

DI_

D3

FTD

I_D

4FT

DI_

D5

FTD

I_D

6FT

DI_

D7

FTD

I_D

[0..7

]

xSPI

_D0

xSPI

_D1

xSPI

_D2

xSPI

_D3

xSPI

_CS

PUD

C

FTD

I_O

EFT

DI_

WR

FTD

I_R

DFT

DI_

SIW

UA

FTD

I_R

XF

FTD

I_TX

E

INC

_AIN

C_B

MO

N_I

NC

INP_

AIN

P_B

SSI_

CLK

SSI_

DTA

SSI_

DTA

SSI_

CLK

INP_

AIN

P_B

MO

N_I

NC

INC

_BIN

C_A

Ban

k 14

NCT14

NCT15

NCT16

NCU15

NCU16

NCV10

NCV13

NCV14

NCV15

NCW10

NCW11

NCW12

NCW14

NCW15

NCW16

NCY11

NCY12

NCY13

NC Y14

NC Y16

NC Y17

NC AA9

NC AA10

NC AA11

NC AA13

NC AA14

NC AA15

NC AA16

NC AB10

NC AB11

NC AB12

NC AB13

NC AB15

NC AB16

NC AB17

U2L

XC

7A35

T-2F

GG

484I

NC


R127

PIR12801 PIR12802 COR128

PIU20AA18

PIU20AA19

PIU20AA20

PIU20AA21

PIU20AB18

PIU20AB20

PIU20AB21

PIU20AB22

PIU20N13

PIU20N14

PIU20N15

PIU20N17

PIU20P14

PIU20P15

PIU20P16

PIU20P17

PIU20P19

PIU20P20

PIU20P21

PIU20P22

PIU20R14

PIU20R16

PIU20R17

PIU20R18

PIU20R19

PIU20R21

PIU20R22

PIU20T18

PIU20T19

PIU20T20

PIU20T21

PIU20U17

PIU20U18

PIU20U20

PIU20U21

PIU20U22

PIU20V17

PIU20V18

PIU20V19

PIU20V20

PIU20V22

PIU20W17

PIU20W19

PIU20W20

PIU20W21

PIU20W22

PIU20Y18

PIU20Y19

PIU20Y21

PIU20Y22

COU2

A

PIU20AA9 PIU20AA10 PIU20AA11 PIU20AA13


PIU20AB11 PIU20AB12 PIU20AB13 PIU20AB15

PIU20AB16 PIU20AB17

PIU20T14 PIU20T15 PIU20T16 PIU20U15

PIU20U16 PIU20V10 PIU20V13 PIU20V14

PIU20V15 PIU20W10 PIU20W11 PIU20W12

PIU20W14 PIU20W15 PIU20W16 PIU20Y11

PIU20Y12 PIU20Y13

PIU20Y14 PIU20Y16 PIU20Y17

COU2

L

PIR12702

PIU20P14

NLFTDI0OE

POFTDI0OE

PIU20N14

NLFTDI0RD

POFTDI0RD

PIU20N15

NLFTDI0RXF

POFTDI0RXF

PIU20R14

NLFTDI0SIWUA

POFT

DI0S

IWUA

PIU20P15

NLFTDI0TXE

POFTDI0TXE

PIU20N13

NLFT

DI0W

R POFTDI0WR

PIR12801

PIU20Y22

NLINC0A

POINC0A

PIU20W19

NLIN

C0B

POINC0B

PIU20P20

NLIN

P0A

POINP0A

PIU20P19

NLIN

P0B

POINP0B

PIU20V20

NLMON0INC

POMON0INC

PIU20AA9 PIU20AA10 PIU20AA11 PIU20AA13

PIU20AA14 PIU20AA15 PIU20AA16

PIU20AA18

PIU20AA19

PIU20AA20

PIU20AA21

PIU20AB10 PIU20AB11 PIU20AB12 PIU20AB13

PIU20AB15 PIU20AB16 PIU20AB17

PIU20AB18

PIU20AB20

PIU20AB21

PIU20R19

PIU20T14 PIU20T15 PIU20T16

PIU20T20

PIU20T21

PIU20U15 PIU20U16

PIU20U17

PIU20U20

PIU20U21

PIU20V10 PIU20V13 PIU20V14 PIU20V15

PIU20V17

PIU20V18

PIU20V19

PIU20V22

PIU20W10 PIU20W11 PIU20W12 PIU20W14

PIU20W15 PIU20W16

PIU20W17

PIU20W20

PIU20W21

PIU20W22



PIU20Y18

PIU20Y19

PIR12701 PIR12802 PIU20U22

NLPU

DC

PIU20AB22

NLSS

I0CL

K POSSI0CLK

PIU20Y21

NLSSI0DTA

POSSI0DTA

PIU20T19

NLxS

PI0C

S POxSPI0CS

PIU20P22

NLxS

PI0D

0 POxSPI0D0

PIU20R22

NLxS

PI0D

1 POxSPI0D1

PIU20P21

NLxS

PI0D

2 POxSPI0D2

PIU20R21

NLxS

PI0D

3 POxSPI0D3

PIU20N17

NLFT

DI0D

0000

70

NLFTDI0D0

POFT

DI0D

0000

70

PIU20P17

NLFT

DI0D

0000

70

NLFTDI0D1

POFT

DI0D

0000

70

PIU20R18

NLFT

DI0D

0000

70

NLFTDI0D2

POFT

DI0D

0000

70

PIU20P16

NLFT

DI0D

0000

70

NLFTDI0D3

POFT

DI0D

0000

70

PIU20T18

NLFT

DI0D

0000

70

NLFTDI0D4

POFT

DI0D

0000

70

PIU20R17

NLFT

DI0D

0000

70

NLFTDI0D5

POFT

DI0D

0000

70

PIU20U18

NLFT

DI0D

0000

70

NLFTDI0D6

POFT

DI0D

0000

70

PIU20R16

NLFT

DI0D

0000

70

NLFTDI0D7

POFT

DI0D

0000

70

POFTDI0D0

POFTDI0D1

POFTDI0D2

POFTDI0D3

POFTDI0D4

POFTDI0D5

POFTDI0D6

POFTDI0D7

POFT

DI0D

0000

70

POFTDI0OE

POFTDI0RD

POFTDI0RXF

POFT

DI0S

IWUA

POFTDI0TXE

POFTDI0WR

POINC0A

POINC0B

POINP0A

POINP0B

POMON0INC

POSSI0CLK

POSSI0DTA

POXSPI0CS

POXSPI0D0

POXSPI0D1

POXSPI0D2

POXSPI0D3

XXXI

A Appendix

11

22

33

44

DD

CC

BB

AA

Tite

l:

Dat

um:

Seite

Entw

ickl

erkü

rzel

:Em

il-Fi

gge-

Straße

85,

442

27 D

ortm

und

DD

R3.

SchD

oc

03.0

9.20

18

20

SeD

a

DD

R3.

Sch

Doc

Adre

sse:

Zeit:

13:4

6:50

von

23Ve

rsio

n:

Proj

ekt:

VAD

ER_F

RG

A.Pr

jPcb

v1.0

R90

1k0

R89

1k0

C79

1u2

GN

DG

ND

GN

D

1V35

1V35

1V35

1V35

GN

D

DD

R3_

CK

ED

DR

3_C

K_N

DD

R3_

CK

_P

iPa

ram

eter

Set

C80

100n

C78

100n

DD

R3_

A[0

..13]

DD

R3_

A0

DD

R3_

A1

DD

R3_

A2

DD

R3_

A3

DD

R3_

A4

DD

R3_

A5

DD

R3_

A6

DD

R3_

A7

DD

R3_

A8

DD

R3_

A9

DD

R3_

A10

DD

R3_

A11

DD

R3_

A12

DD

R3_

A13

DD

R3_

DQ

0D

DR

3_D

Q1

DD

R3_

DQ

2D

DR

3_D

Q3

DD

R3_

DQ

4D

DR

3_D

Q5

DD

R3_

DQ

6D

DR

3_D

Q7

DD

R3_

DQ

[0..1

5]i

DD

R3_

Dat

ai

DD

R3_

Add

ress

DD

R3_

DQ

S1_P

DD

R3_

BA

[0..2

]

DD

R3_

BA

0D

DR

3_B

A1

DD

R3_

BA

2

DD

R3_

WE

DD

R3_

CK

E

DQ

13A

2

DQ

15A

3

DQ

12A

7

UD

QS#

B7

DQ

14B

8

DQ

11C

2

DQ

9C

3

UD

QS

C7

DQ

10C

8

UD

MD

3

DQ

8D

7

DQ

0E3

LDM

E7

DQ

2F2

LDQ

SF3

DQ

1F7

DQ

3F8

DQ

6G

2

LDQ

S#G

3

DQ

4H

3

DQ

7H

7

DQ

5H

8

RA

S#J3

CK

J7

OD

TK

1

CA

S#K

3

CK

#K

7

CK

EK

9

CS#

L2

WE#

L3

A10

/AP

L7

ZQL8

BA

0M

2

BA

2M

3

A3

N2

A0

N3

A12

/BC

#N

7

BA

1N

8

A5

P2

A2

P3A

1P7

A4

P8

A7

R2

A9

R3

A11

R7

A6

R8

RES

ET#

T2

A13

T3

A8

T8

U1A

MT4

1K12

8M16

JT-1

25 IT

DD

R3_

OD

TD

DR

3_O

DT

R93

1k0

GN

D

R15

810

k

GN

D

DD

R3_

RES

ETD

DR

3_R

ESET

DD

R3_

CS

DD

R3_

RA

SD

DR

3_C

AS

DD

R3_

WE

DD

R3_

CS

DD

R3_

RA

SD

DR

3_C

AS

DD

R3_

DQ

S0_P

DD

R3_

DQ

S0_N

DD

R3_

DQ

S0_P

DD

R3_

DQ

S0_N

DD

R3_

DQ

S1_P

DD

R3_

DQ

S1_N

DD

R3_

DQ

S1_N

DD

R3_

DQ

8D

DR

3_D

Q9

DD

R3_

DQ

10D

DR

3_D

Q11

DD

R3_

DQ

12D

DR

3_D

Q13

DD

R3_

DQ

14D

DR

3_D

Q15

DD

R3_

DM

0D

DR

3_D

M1

DD

R3_

DM

0D

DR

3_D

M1

VD

DQ

A1

VD

DQ

A8

VSS

A9

VSS

QB

1

VD

DB

2

VSS

B3

VSS

QB

9

VD

DQ

C1

VD

DQ

C9

VSS

QD

1

VD

DQ

D2

VSS

QD

8

VD

DD

9

VSS

E1

VSS

QE2

VSS

QE8

VD

DQ

E9V

DD

QF1

VSS

QF9

VSS

QG

1

VD

DG

7

VSS

G8

VSS

QG

9V

DD

QH

2

VD

DQ

H9

VSS

J2

VSS

J8

VD

DK

2

VD

DK

8V

SSM

1

VSS

M9

VD

DN

1

VD

DN

9V

SSP1

VSS

P9

VD

DR

1

VD

DR

9V

SST1

VSS

T9

VR

EFD

QH

1V

REF

CA

M8

U1B

MT4

1K12

8M16

JT-1

25 IT

NC

J1N

CJ9

NC

L1

NC

L9

NC

M7

NC

T7

U1C

MT4

1K12

8M16

JT-1

25 IT

C90

100n

DD

R3_

CK

_ND

DR

3_C

K_P

C21

510

0nC

216

100n

C21

710

0nC

218

100n

C21

910

0nC

220

100n

C22

110

0n

C22

210

0nC

223

100n

C22

410

0nC

225

100n

C22

610

0nC

227

100n

C22

810

0nC

229

100n

C23

047

0nC

231

470n

C23

24u

7

GN

DG

ND

GN

D

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

1V35

1V35

1V35

DD

R3_

A[0

..13]

DD

R3_

BA

[0..2

]

DD

R3_

DQ

[0..1

5]

Cap

acito

r Ban

king

DD

R3

Mem

ory

DD

R3

Pow

ersu

pply

R91

82R

TP31

TP32

PIC7801 PIC7802 CO

C78

PIC7901 PIC7902 CO

C79

PIC8001 PIC8002 CO

C80


PIC21501

PIC21502 CO

C215


C216

PIC21701

PIC21702 CO

C217


C218

PIC21901 PIC21902 COC219 PIC2200

1 PIC2200

2 COC2

20 PIC22101 PIC22102

COC2

21

PIC22201 PIC22202 COC222 PIC2230

1 PIC2230

2 COC2

23 PIC22401 PIC22402

COC2

24 PIC2250

1 PIC2250

2 COC2

25 PIC22601 PIC22602

COC2

26 PIC22701 PIC22702

COC227 PIC2280

1 PIC2280

2 COC2

28 PIC22901 PIC22902

COC2

29

PIC23001 PIC23002 COC230


C231

PIC2320

1 PIC23202 CO

C232

PIR8901 PIR8902 CO

R89

PIR9001 PIR9002 CO

R90



3


R158

PITP3100 COTP

31

PITP3200 COTP

32

PIU10A2

PIU10A3

PIU10A7

PIU10B7

PIU10B8

PIU10C2

PIU10C3

PIU10C7

PIU10C8

PIU10D3

PIU10D7

PIU10E3

PIU10E7

PIU10F2

PIU10F3

PIU10F7

PIU10F8

PIU10G2

PIU10G3

PIU10H3

PIU10H7

PIU10H8

PIU10J3

PIU10J7

PIU10K1

PIU10K3

PIU10K7

PIU10K9

PIU10L2

PIU10L3

PIU10L7

PIU10L8

PIU10M2

PIU10M3

PIU10N2

PIU10N3

PIU10N7

PIU10N8

PIU10P2

PIU10P3

PIU10P7

PIU10P8

PIU10R2

PIU10R3

PIU10R7

PIU10R8

PIU10T2

PIU10T3

PIU10T8 COU1A

PIU10A1

PIU10A8

PIU10A9

PIU10B1

PIU10B2

PIU10B3

PIU10B9

PIU10C1

PIU10C9

PIU10D1

PIU10D2

PIU10D8

PIU10D9

PIU10E1

PIU10E2

PIU10E8

PIU10E9

PIU10F1

PIU10F9

PIU10G1

PIU10G7

PIU10G8

PIU10G9

PIU10H1

PIU10H2

PIU10H9

PIU10J2

PIU10J8

PIU10K2

PIU10K8

PIU10M1

PIU10M8

PIU10M9

PIU10N1

PIU10N9

PIU10P1

PIU10P9

PIU10R1

PIU10R9

PIU10T1

PIU10T9

COU1B

PIU10J1

PIU10J9

PIU10L1

PIU10L9

PIU10M7

PIU10T7

COU1C

PIC7801

PIC9001 PIC2150

1 PIC21601

PIC21701

PIC21801 PIC21901

PIC22001

PIC22101

PIC22201 PIC2230

1 PIC22401

PIC22501

PIC22601 PIC22701

PIC22801

PIC22901

PIC23001 PIC2310

1 PIC2320

1

PIR8902

PIU10A1

PIU10A8

PIU10B2

PIU10C1

PIU10C9

PIU10D2

PIU10D9

PIU10E9

PIU10F1

PIU10G7

PIU10H2

PIU10H9

PIU10K2

PIU10K8

PIU10N1

PIU10N9

PIU10R1

PIU10R9

PIU10K3

NLDD

R30C

AS

PODDR30CAS

PIR9101 PIU10K7

NLDD

R30C

K0N

PODDR30CK0N

PIR9102

PIU10J7

NLDD

R30C

K0P

PODDR30CK0P

PIU10K9

NLDD

R30C

KE

PODDR30CKE

PIU10L2

NLDD

R30C

S PODDR30CS

PIU10E7

NLDDR30DM0

PODDR30DM0

PIU10D3

NLDDR30DM1

PODDR30DM1

PIU10G3

NLDD

R30D

QS00

N PODDR30DQS00N

PIU10F3

NLDDR30DQS00P

PODDR30DQS00P

PIU10B7

NLDD

R30D

QS10

N PODDR30DQS10N

PIU10C7

NLDDR30DQS10P

PODDR30DQS10P

PIU10K1

NLDD

R30O

DT

PODDR30ODT

PIU10J3

NLDD

R30R

AS

PODDR30RAS

PIR15802

PIU10T2

NLDDR30RESET

PODDR30RESET

PIU10L3

NLDDR30WE

PODDR30WE

PIC7902 PIC8002

PIC9002 PIC2150

2 PIC21602

PIC21702

PIC21802 PIC21902

PIC22002

PIC22102

PIC22202 PIC2230

2 PIC22402

PIC22502

PIC22602 PIC22702

PIC22802

PIC22902

PIC23002 PIC23102

PIC23202

PIR9001

PIR9301 PIR15801

PIU10A9

PIU10B1

PIU10B3

PIU10B9

PIU10D1

PIU10D8

PIU10E1

PIU10E2

PIU10E8

PIU10F9

PIU10G1

PIU10G8

PIU10G9

PIU10J2

PIU10J8

PIU10M1

PIU10M9

PIU10P1

PIU10P9

PIU10T1

PIU10T9

PIC7802

PIC7901 PIC8001


00

PIU10H1

PIU10M8

PIR9302 PITP32

00 PIU10L8

PIU10J1

PIU10J9

PIU10L1

PIU10L9

PIU10M7

PIU10T7

PIU10N3

NLDDR30A0000130

NLDD

R30A

0

PODDR30A0000130

PIU10P7

NLDDR30A0000130

NLDD

R30A

1

PODDR30A0000130

PIU10P3

NLDDR30A0000130

NLDD

R30A

2

PODDR30A0000130

PIU10N2

NLDDR30A0000130

NLDD

R30A

3

PODDR30A0000130

PIU10P8

NLDDR30A0000130

NLDD

R30A

4

PODDR30A0000130

PIU10P2

NLDDR30A0000130

NLDD

R30A

5

PODDR30A0000130

PIU10R8

NLDDR30A0000130

NLDD

R30A

6

PODDR30A0000130

PIU10R2

NLDDR30A0000130

NLDD

R30A

7

PODDR30A0000130

PIU10T8

NLDDR30A0000130

NLDD

R30A

8

PODDR30A0000130

PIU10R3

NLDDR30A0000130

NLDD

R30A

9

PODDR30A0000130

PIU10L7

NLDDR30A0000130

NLDDR30A10

PODDR30A0000130

PIU10R7

NLDDR30A0000130

NLDDR30A11

PODDR30A0000130

PIU10N7

NLDDR30A0000130

NLDDR30A12

PODDR30A0000130

PIU10T3

NLDDR30A0000130

NLDDR30A13

PODDR30A0000130

PIU10M2

NLDD

R30B

A000

020

NLDD

R30B

A0

PODDR30BA000020

PIU10N8

NLDD

R30B

A000

020

NLDD

R30B

A1

PODDR30BA000020

PIU10M3

NLDD

R30B

A000

020

NLDD

R30B

A2

PODDR30BA000020

PIU10E3

NLDD

R30D

Q000

0150

NLDD

R30D

Q0

PODDR30DQ0000150

PIU10F7

NLDD

R30D

Q000

0150

NLDD

R30D

Q1

PODDR30DQ0000150

PIU10F2

NLDD

R30D

Q000

0150

NLDD

R30D

Q2

PODDR30DQ0000150

PIU10F8

NLDD

R30D

Q000

0150

NLDD

R30D

Q3

PODDR30DQ0000150

PIU10H3

NLDD

R30D

Q000

0150

NLDD

R30D

Q4

PODDR30DQ0000150

PIU10H8

NLDD

R30D

Q000

0150

NLDD

R30D

Q5

PODDR30DQ0000150

PIU10G2

NLDD

R30D

Q000

0150

NLDD

R30D

Q6

PODDR30DQ0000150

PIU10H7

NLDD

R30D

Q000

0150

NLDD

R30D

Q7

PODDR30DQ0000150

PIU10D7

NLDD

R30D

Q000

0150

NLDD

R30D

Q8

PODDR30DQ0000150

PIU10C3

NLDD

R30D

Q000

0150

NLDD

R30D

Q9

PODDR30DQ0000150

PIU10C8

NLDD

R30D

Q000

0150

NLDD

R30D

Q10

PODDR30DQ0000150

PIU10C2

NLDD

R30D

Q000

0150

NLDD

R30D

Q11

PODDR30DQ0000150

PIU10A7

NLDD

R30D

Q000

0150

NLDD

R30D

Q12

PODDR30DQ0000150

PIU10A2

NLDD

R30D

Q000

0150

NLDD

R30D

Q13

PODDR30DQ0000150

PIU10B8

NLDD

R30D

Q000

0150

NLDD

R30D

Q14

PODDR30DQ0000150

PIU10A3

NLDD

R30D

Q000

0150

NLDD

R30D

Q15

PODDR30DQ0000150

PODDR30A0

PODDR30A1

PODDR30A2

PODDR30A3

PODDR30A4

PODDR30A5

PODDR30A6

PODDR30A7

PODDR30A8

PODDR30A9

PODDR30A10

PODDR30A11

PODDR30A12

PODDR30A13

PODDR30A0000130

PODDR30BA0

PODDR30BA1

PODDR30BA2

PODDR30BA000020

PODDR30CAS

PODDR30CK0N

PODDR30CK0P

PODDR30CKE

PODDR30CS

PODDR30DM0

PODDR30DM1

PODDR30DQ0

PODDR30DQ1

PODDR30DQ2

PODDR30DQ3

PODDR30DQ4

PODDR30DQ5

PODDR30DQ6

PODDR30DQ7

PODDR30DQ8

PODDR30DQ9

PODDR30DQ10

PODDR30DQ11

PODDR30DQ12

PODDR30DQ13

PODDR30DQ14

PODDR30DQ15

PODDR30DQ0000150

PODDR30DQS00N

PODDR30DQS00P

PODDR30DQS10N

PODDR30DQS10P

PODDR30ODT

PODDR30RAS

PODDR30RESET

PODDR30WE

XXXII

A Appendix

11

22

33

44

DD

CC

BB

AA

Tite

l:

Dat

um:

Seite

Entw

ickl

erkü

rzel

:Em

il-Fi

gge-

Straße

85,

442

27 D

ortm

und

FPG

A_BA

NKS

2.Sc

hDoc

03.0

9.20

18

21

SeD

a

FPG

A_B

AN

KS

2.S

chD

oc

Adre

sse:

Zeit:

13:4

6:51

von

23Ve

rsio

n:

Proj

ekt:

VAD

ER_F

RG

A.Pr

jPcb

v1.0

IO_0

_35

F4

IO_L

5N_T

0_A

D13

N_3

5F1

IO_L

4P_T

0_35

E2

IO_L

6P_T

0_35

F3

IO_L

4N_T

0_35

D2

IO_L

3P_T

0_D

QS_

AD

5P_3

5E1

IO_L

3N_T

0_D

QS_

AD

5N_3

5D

1

IO_L

1N_T

0_A

D4N

_35

A1

IO_L

5P_T

0_A

D13

P_35

G1

IO_L

1P_T

0_A

D4P

_35

B1

IO_L

2N_T

0_A

D12

N_3

5B

2

IO_L

2P_T

0_A

D12

P_35

C2

IO_L

6N_T

0_V

REF

_35

E3

IO_L

8N_T

1_A

D14

N_3

5G

2

IO_L

7P_T

1_A

D6P

_35

K1

IO_L

8P_T

1_A

D14

P_35

H2

IO_L

7N_T

1_A

D6N

_35

J1

IO_L

9P_T

1_D

QS_

AD

7P_3

5K

2

IO_L

9N_T

1_D

QS_

AD

7N_3

5J2

IO_L

10P_

T1_A

D15

P_35

J5

IO_L

11P_

T1_S

RC

C_3

5H

3

IO_L

12P_

T1_M

RC

C_3

5H

4

IO_L

10N

_T1_

AD

15N

_35

H5

IO_L

11N

_T1_

SRC

C_3

5G

3

IO_L

12N

_T1_

MR

CC

_35

G4

IO_L

13N

_T2_

MR

CC

_35

J4

IO_L

18P_

T2_3

5L5

IO_L

16N

_T2_

35M

2

IO_L

14N

_T2_

SRC

C_3

5K

3

IO_L

17P_

T2_3

5K

6

IO_L

14P_

T2_S

RC

C_3

5L3

IO_L

13P_

T2_M

RC

C_3

5K

4

IO_L

15N

_T2_

DQ

S_35

L1

IO_L

17N

_T2_

35J6

IO_L

18N

_T2_

35L4

IO_L

15P_

T2_D

QS_

35M

1

IO_L

16P_

T2_3

5M

3

IO_L

23N

_T3_

35M

5

IO_L

23P_

T3_3

5M

6

IO_L

24P_

T3_3

5P6

IO_L

22N

_T3_

35N

2

IO_L

21P_

T3_D

QS_

35P5

IO_L

21N

_T3_

DQ

S_35

P4

IO_L

24N

_T3_

35N

5

IO_L

20N

_T3_

35P1

IO_L

19P_

T3_3

5N

4

IO_L

22P_

T3_3

5P2

IO_L

20P_

T3_3

5R

1

IO_L

19N

_T3_

VR

EF_3

5N

3

IO_2

5_35

L6BANK 35

U2E

XC

7A35

T-2F

GG

484I

DD

R3_

BA

[0..2

]

DD

R3_

CK

_N

DD

R3_

DQ

S1_N

DD

R3_

DQ

S1_P

DD

R3_

DQ

S0_N

DD

R3_

DQ

S0_P

DD

R3_

OD

TD

DR

3_W

ED

DR

3_C

AS

DD

R3_

RA

SD

DR

3_C

KE

DD

R3_

RES

ETD

DR

3_C

SD

DR

3_C

K_P

DD

R3_

DQ

0D

DR

3_D

Q1

DD

R3_

DQ

2D

DR

3_D

Q3

DD

R3_

DQ

4D

DR

3_D

Q5

DD

R3_

DQ

6D

DR

3_D

Q7

DD

R3_

BA

0D

DR

3_B

A1

DD

R3_

BA

2

DD

R3_

DQ

S1_P

DD

R3_

DQ

S1_N

DD

R3_

RES

ETD

DR

3_C

S

DD

R3_

RA

SD

DR

3_C

AS

DD

R3_

WE

DD

R3_

CK

_PD

DR

3_C

K_N

DD

R3_

CK

E

DD

R3_

OD

T

DD

R3_

RES

ET

DD

R3_

DQ

[0..1

5]

DD

R3_

DM

1D

DR

3_D

M0

DD

R3_

DM

0D

DR

3_D

M1

DD

R3_

DQ

8D

DR

3_D

Q9

DD

R3_

DQ

10D

DR

3_D

Q11

DD

R3_

DQ

12D

DR

3_D

Q13

DD

R3_

DQ

14D

DR

3_D

Q15

DD

R3_

DQ

S0_P

DD

R3_

DQ

S0_N

DD

R3_

CK

ED

DR

3_W

ED

DR

3_B

A1

DD

R3_

RA

SD

DR

3_B

A2

DD

R3_

A0

DD

R3_

CA

SD

DR

3_A

2D

DR

3_B

A0

DD

R3_

A3

DD

R3_

A1

DD

R3_

A4

DD

R3_

A10

DD

R3_

OD

TD

DR

3_A

9D

DR

3_A

6D

DR

3_C

K_P

DD

R3_

CK

_ND

DR

3_A

7D

DR

3_A

11D

DR

3_A

5D

DR

3_A

12D

DR

3_A

8D

DR

3_A

13D

DR

3_C

S

DD

R3_

A0

DD

R3_

A1

DD

R3_

A2

DD

R3_

A3

DD

R3_

A4

DD

R3_

A5

DD

R3_

A6

DD

R3_

A7

DD

R3_

A8

DD

R3_

A9

DD

R3_

A10

DD

R3_

A11

DD

R3_

A12

DD

R3_

A13

DD

R3_

A[0

..13]

DD

R3_

A[0

..13]

DD

R3_

BA

[0..2

]

DD

R3_

DQ

[0..1

5]

IO_L

18N

_T2_

34A

A6

IO_L

10P_

T1_3

4A

A5

IO_L

10N

_T1_

34A

B5

IO_L

22N

_T3_

34A

B8

IO_L

20P_

T3_3

4A

B7

IO_L

11P_

T1_S

RC

C_3

4Y

4

IO_L

8P_T

1_34

AB

3

IO_L

19P_

T3_3

4V

7

IO_L

21N

_T3_

DQ

S_34

V8

IO_L

22P_

T3_3

4A

A8

IO_L

1N_T

0_34

U1

IO_L

6P_T

0_34

U3

IO_L

2N_T

0_34

V2

IO_L

4P_T

0_34

W2

IO_L

21P_

T3_D

QS_

34V

9

IO_L

9N_T

1_D

QS_

34A

A3

IO_L

1P_T

0_34

T1

IO_L

9P_T

1_D

QS_

34Y

3

IO_L

24P_

T3_3

4W

9

IO_L

23N

_T3_

34Y

7

IO_L

18P_

T2_3

4Y

6

IO_L

4N_T

0_34

Y2

IO_L

11N

_T1_

SRC

C_3

4A

A4

IO_L

12P_

T1_M

RC

C_3

4V

4

IO_L

12N

_T1_

MR

CC

_34

W4

IO_L

13P_

T2_M

RC

C_3

4R

4

IO_L

13N

_T2_

MR

CC

_34

T4

IO_L

14P_

T2_S

RC

C_3

4T5

IO_L

17N

_T2_

34T6

IO_L

15N

_T2_

DQ

S_34

W5

IO_L

2P_T

0_34

U2

IO_L

23P_

T3_3

4Y

8

IO_L

7N_T

1_34

AB

1

IO_2

5_34

U7

IO_L

15P_

T2_D

QS_

34W

6

IO_L

20N

_T3_

34A

B6

IO_L

3N_T

0_D

QS_

34R

2

IO_L

7P_T

1_34

AA

1

IO_L

14N

_T2_

SRC

C_3

4U

5

IO_L

8N_T

1_34

AB

2

IO_L

19N

_T3_

VR

EF_3

4W

7

IO_0

_34

T3

IO_L

16P_

T2_3

4U

6

IO_L

17P_

T2_3

4R

6

IO_L

3P_T

0_D

QS_

34R

3

IO_L

24N

_T3_

34Y

9

IO_L

6N_T

0_V

REF

_34

V3

IO_L

5P_T

0_34

W1

IO_L

5N_T

0_34

Y1

IO_L

16N

_T2_

34V

5

BANK 34

U2D

XC

7A35

T-2F

GG

484I

MC

ASP

0AH

CLK

R

MC

ASP

1FSR

MC

ASP

1AC

LKR

MC

ASP

1AH

CLK

R

SPI2

_CLK

SPI2

_SC

S0SP

I2_M

ISO

SPI2

_MO

SI

RES

ETST

AT

MC

ASP

1AM

UTE

_RM

CA

SP1F

SX

SPI2

_SC

S0SP

I2_M

ISO

SPI2

_MO

SI

SPI2

_CLK

RES

ETST

AT

MC

ASP

1AM

UTE

_R

MC

ASP

1FSR

MC

ASP

1FSX

MC

ASP

1AH

CLK

RM

CA

SP1A

CLK

R

MC

ASP

0AH

CLK

R

Inte

rfac

e

Ban

k 35

Ban

k 34

C99

100n

Stan

dby

1

GN

D2

Out

put

3

VC

C4

IC18

100.

000

MH

zG

ND

GN

D

3V3

CLK

_100

MH

z

100

MH

z C

lock

CLK

_100

MH

z

MC

ASP

0AC

LKX

MC

ASP

0AH

CLK

X

MC

ASP

0AM

UTE

MC

ASP

0FSR

MC

ASP

0FSX

MC

ASP

0FSX

MC

ASP

0FSR

MC

ASP

0AM

UTE

MC

ASP

0AH

CLK

X

MC

ASP

0AX

R[0

..15]

MC

ASP

0AX

R9

MC

ASP

0AX

R6

MC

ASP

0AX

R12

MC

ASP

0AX

R13

MC

ASP

0AX

R14

MC

ASP

0AX

R4

MC

ASP

0AX

R5

MC

ASP

0AX

R7

MC

ASP

0AX

R15

MC

ASP

0AX

R8

MC

ASP

0AX

R10

MC

ASP

0AX

R[0

..15]

MC

ASP

0AC

LKR

MC

ASP

0AC

LKX

MC

ASP

0AC

LKR

MC

ASP

1AC

LKX

MC

ASP

1AC

LKX

MC

ASP

0AC

LKX

MC

ASP

0AC

LKR

MC

ASP

1AC

LKX

GN

D

J18 SS

MC

X 5

0R

DD

R3_

DM

0D

DR

3_D

Q5

DD

R3_

DQ

2D

DR

3_D

Q1

DD

R3_

DQ

S0_P

DD

R3_

DQ

S0_N

DD

R3_

DQ

4D

DR

3_D

Q7

DD

R3_

DQ

0D

DR

3_D

Q6

DD

R3_

DQ

3

DD

R3_

DM

1D

DR

3_D

Q12

DD

R3_

DQ

10D

DR

3_D

Q14

DD

R3_

DQ

S1_P

DD

R3_

DQ

S1_N

DD

R3_

DQ

11D

DR

3_D

Q8

DD

R3_

DQ

15D

DR

3_D

Q13

DD

R3_

DQ

9

MC

ASP

0AX

R3

MC

ASP

1AX

R[0

..9]

MC

ASP

1AX

R[0

..9]

MC

ASP

1AX

R0

MC

ASP

1AX

R1

MC

ASP

1AX

R2

MC

ASP

1AX

R9

MC

ASP

1AX

R8

MC

ASP

1AX

R6

MC

ASP

1AX

R7

MC

ASP

1AX

R5

MC

ASP

1AX

R4

MC

ASP

1AX

R3

MC

ASP

0AX

R1

MC

ASP

0AX

R0

MC

ASP

0AX

R2

PIC9901 PIC9902 CO

C99

PIIC1801

PIIC1802

PIIC1803

PIIC1804 COIC

18

PIJ1

801

PIJ1802

COJ18

PIU20AA1

PIU20AA3

PIU20AA4

PIU20AA5

PIU20AA6

PIU20AA8

PIU20AB1

PIU20AB2

PIU20AB3

PIU20AB5

PIU20AB6

PIU20AB7

PIU20AB8

PIU20R2

PIU20R3

PIU20R4

PIU20R6

PIU20T1

PIU20T3

PIU20T4

PIU20T5

PIU20T6

PIU20U1

PIU20U2

PIU20U3

PIU20U5

PIU20U6

PIU20U7

PIU20V2

PIU20V3

PIU20V4

PIU20V5

PIU20V7

PIU20V8

PIU20V9

PIU20W1

PIU20W2

PIU20W4

PIU20W5

PIU20W6

PIU20W7

PIU20W9

PIU20Y1

PIU20Y2

PIU20Y3

PIU20Y4

PIU20Y6

PIU20Y7

PIU20Y8

PIU20Y9

COU2D

PIU20A1

PIU20B1

PIU20B2

PIU20C2

PIU20D1

PIU20D2

PIU20E1

PIU20E2

PIU20E3

PIU20F1

PIU20F3

PIU20F4

PIU20G1

PIU20G2

PIU20G3

PIU20G4

PIU20H2

PIU20H3

PIU20H4

PIU20H5

PIU20J1

PIU20J2

PIU20J4

PIU20J5

PIU20J6

PIU20K1

PIU20K2

PIU20K3

PIU20K4

PIU20K6

PIU20L1

PIU20L3

PIU20L4

PIU20L5

PIU20L6

PIU20M1

PIU20M2

PIU20M3

PIU20M5

PIU20M6

PIU20N2

PIU20N3

PIU20N4

PIU20N5

PIU20P1

PIU20P2

PIU20P4

PIU20P5

PIU20P6

PIU20R1

COU2E

PIC9901 PIIC1801

PIIC1804

PIIC1803

PIJ1

801

PIU20R4

NLCLK0100MHz

PIU20K4

NLDD

R30C

AS

PODDR30CAS

PIU20P4

NLDD

R30C

K0N

PODDR30CK0N

PIU20P5

NLDD

R30C

K0P

PODDR30CK0P

PIU20J4

NLDDR30CKE

PODDR30CKE

PIU20L6

NLDD

R30C

S PODDR30CS

PIU20G2

NLDDR30DM0

PODDR30DM0

PIU20F1

NLDDR30DM1

PODDR30DM1

PIU20J2

NLDD

R30D

QS00

N PODDR30DQS00N

PIU20K2

NLDD

R30D

QS00

P PODDR30DQS00P

PIU20D1

NLDD

R30D

QS10

N PODDR30DQS10N

PIU20E1

NLDD

R30D

QS10

P PODDR30DQS10P

PIU20M6

NLDDR30ODT

PODDR30ODT

PIU20K3

NLDD

R30R

AS

PODDR30RAS

PIU20F4

NLDDR30RESET

PODDR30RESET

PIU20L5

NLDD

R30W

E PODDR30WE

PIC9902 PIIC1802

PIJ1802

PIU20Y2

NLMC

ASP0

ACLK

R POMCASP0ACLKR

PIU20V4

NLMC

ASP0

ACLK

X POMCASP0ACLKX

PIU20U3

NLMCASP0AHCLKR

POMCASP0AHCLKR

PIU20T1

NLMCASP0AHCLKX

POMCASP0AHCLKX

PIU20V9

NLMC

ASP0

AMUT

E POMCASP0AMUTE

PIU20W2

NLMC

ASP0

FSR

POMCASP0FSR

PIU20V2

NLMC

ASP0

FSX

POMCASP0FSX

PIU20V8

NLMC

ASP1

ACLK

R POMCASP1ACLKR

PIU20T5

NLMC

ASP1

ACLK

X POMCASP1ACLKX

PIU20V7

NLMCASP1AHCLKR

POMCASP1AHCLKR

PIU20Y4

NLMCASP1AMUTE0R

POMCASP1AMUTE0R

PIU20AA8

NLMC

ASP1

FSR

POMCASP1FSR

PIU20AB3

NLMC

ASP1

FSX

POMCASP1FSX

PIU20AA4

PIU20AB6

PIU20E3

PIU20G4

PIU20T4

PIU20W4

PIU20Y1

PIU20Y3

PIU20AB7

NLRE

SETS

TAT

PORESETSTAT

PIU20AB8

NLSP

I20C

LK

POSPI20CLK

PIU20AA5

NLSPI20MISO

POSPI20MISO

PIU20AA6

NLSPI20MOSI

POSPI20MOSI

PIU20AB5

NLSPI20SCS0

POSPI20SCS0

PIU20L3

NLDDR30A0000130

NLDD

R30A

0

PODDR30A0000130

PIU20M1

NLDDR30A0000130

NLDD

R30A

1

PODDR30A0000130

PIU20L1

NLDDR30A0000130

NLDD

R30A

2

PODDR30A0000130

PIU20L4

NLDDR30A0000130

NLDD

R30A

3

PODDR30A0000130

PIU20M3

NLDDR30A0000130

NLDD

R30A

4

PODDR30A0000130

PIU20N4

NLDDR30A0000130

NLDD

R30A

5

PODDR30A0000130

PIU20N2

NLDDR30A0000130

NLDD

R30A

6

PODDR30A0000130

PIU20N5

NLDDR30A0000130

NLDD

R30A

7

PODDR30A0000130

PIU20R1

NLDDR30A0000130

NLDD

R30A

8

PODDR30A0000130

PIU20P6

NLDDR30A0000130

NLDD

R30A

9

PODDR30A0000130

PIU20M5

NLDDR30A0000130

NLDDR30A10

PODDR30A0000130

PIU20P1

NLDDR30A0000130

NLDDR30A11

PODDR30A0000130

PIU20P2

NLDDR30A0000130

NLDDR30A12

PODDR30A0000130

PIU20N3

NLDDR30A0000130

NLDDR30A13

PODDR30A0000130

PIU20J6

NLDD

R30B

A000

020

NLDD

R30B

A0

PODDR30BA000020

PIU20M2

NLDD

R30B

A000

020

NLDD

R30B

A1

PODDR30BA000020

PIU20K6

NLDD

R30B

A000

020

NLDD

R30B

A2

PODDR30BA000020

PIU20H4

NLDD

R30D

Q000

0150

NLDD

R30D

Q0

PODDR30DQ0000150

PIU20J1

NLDD

R30D

Q000

0150

NLDD

R30D

Q1

PODDR30DQ0000150

PIU20H2

NLDD

R30D

Q000

0150

NLDD

R30D

Q2

PODDR30DQ0000150

PIU20G3

NLDD

R30D

Q000

0150

NLDD

R30D

Q3

PODDR30DQ0000150

PIU20J5

NLDD

R30D

Q000

0150

NLDD

R30D

Q4

PODDR30DQ0000150

PIU20K1

NLDD

R30D

Q000

0150

NLDD

R30D

Q5

PODDR30DQ0000150

PIU20H5

NLDD

R30D

Q000

0150

NLDD

R30D

Q6

PODDR30DQ0000150

PIU20H3

NLDD

R30D

Q000

0150

NLDD

R30D

Q7

PODDR30DQ0000150

PIU20G1

NLDD

R30D

Q000

0150

NLDD

R30D

Q8

PODDR30DQ0000150

PIU20C2

NLDD

R30D

Q000

0150

NLDD

R30D

Q9

PODDR30DQ0000150

PIU20F3

NLDD

R30D

Q000

0150

NLDD

R30D

Q10

PODDR30DQ0000150

PIU20A1

NLDD

R30D

Q000

0150

NLDD

R30D

Q11

PODDR30DQ0000150

PIU20E2

NLDD

R30D

Q000

0150

NLDD

R30D

Q12

PODDR30DQ0000150

PIU20B2

NLDD

R30D

Q000

0150

NLDD

R30D

Q13

PODDR30DQ0000150

PIU20D2

NLDD

R30D

Q000

0150

NLDD

R30D

Q14

PODDR30DQ0000150

PIU20B1

NLDD

R30D

Q000

0150

NLDD

R30D

Q15

PODDR30DQ0000150

PIU20AA3

NLMC

ASP0

AXR0

0001

50

NLMC

ASP0

AXR0

POMCASP0AXR0000150

PIU20R2

NLMC

ASP0

AXR0

0001

50

NLMC

ASP0

AXR1

POMCASP0AXR0000150

PIU20AA1

NLMC

ASP0

AXR0

0001

50

NLMC

ASP0

AXR2

POMCASP0AXR0000150

PIU20U5

NLMC

ASP0

AXR0

0001

50

NLMC

ASP0

AXR3

POMCASP0AXR0000150

PIU20AB2

NLMC

ASP0

AXR0

0001

50

NLMC

ASP0

AXR4

POMCASP0AXR0000150

PIU20W7

NLMC

ASP0

AXR0

0001

50

NLMC

ASP0

AXR5

POMCASP0AXR0000150

PIU20T3

NLMC

ASP0

AXR0

0001

50

NLMC

ASP0

AXR6

POMCASP0AXR0000150

PIU20U6

NLMC

ASP0

AXR0

0001

50

NLMC

ASP0

AXR7

POMCASP0AXR0000150

PIU20R6

NLMC

ASP0

AXR0

0001

50

NLMC

ASP0

AXR8

POMCASP0AXR0000150

PIU20R3

NLMC

ASP0

AXR0

0001

50

NLMC

ASP0

AXR9

POMCASP0AXR0000150

PIU20Y9

NLMC

ASP0

AXR0

0001

50

NLMC

ASP0

AXR1

0

POMCASP0AXR0000150 NL

MCAS

P0AX

R000

0150

POMCASP0AXR0000150

PIU20V3

NLMC

ASP0

AXR0

0001

50

NLMC

ASP0

AXR1

2

POMCASP0AXR0000150

PIU20W1

NLMC

ASP0

AXR0

0001

50

NLMC

ASP0

AXR1

3

POMCASP0AXR0000150

PIU20U1

NLMC

ASP0

AXR0

0001

50

NLMC

ASP0

AXR1

4

POMCASP0AXR0000150

PIU20V5

NLMC

ASP0

AXR0

0001

50

NLMC

ASP0

AXR1

5

POMCASP0AXR0000150

PIU20W9

NLMC

ASP1

AXR0

0009

0 NL

MCAS

P1AX

R0

POMCASP1AXR000090

PIU20Y7

NLMC

ASP1

AXR0

0009

0 NL

MCAS

P1AX

R1

POMCASP1AXR000090

PIU20Y6

NLMC

ASP1

AXR0

0009

0

NLMC

ASP1

AXR2

POMCASP1AXR000090

PIU20T6

NLMC

ASP1

AXR0

0009

0

NLMC

ASP1

AXR3

POMCASP1AXR000090

PIU20W5

NLMC

ASP1

AXR0

0009

0

NLMC

ASP1

AXR4

POMCASP1AXR000090

PIU20U2

NLMC

ASP1

AXR0

0009

0

NLMC

ASP1

AXR5

POMCASP1AXR000090

PIU20Y8

NLMC

ASP1

AXR0

0009

0

NLMC

ASP1

AXR6

POMCASP1AXR000090

PIU20AB1

NLMC

ASP1

AXR0

0009

0

NLMC

ASP1

AXR7

POMCASP1AXR000090

PIU20U7

NLMC

ASP1

AXR0

0009

0

NLMC

ASP1

AXR8

POMCASP1AXR000090

PIU20W6

NLMC

ASP1

AXR0

0009

0

NLMC

ASP1

AXR9

POMCASP1AXR000090

PODDR30A0

PODDR30A1

PODDR30A2

PODDR30A3

PODDR30A4

PODDR30A5

PODDR30A6

PODDR30A7

PODDR30A8

PODDR30A9

PODDR30A10

PODDR30A11

PODDR30A12

PODDR30A13

PODDR30A0000130

PODDR30BA0

PODDR30BA1

PODDR30BA2

PODDR30BA000020

PODDR30CAS

PODDR30CK0N

PODDR30CK0P

PODDR30CKE

PODDR30CS

PODDR30DM0

PODDR30DM1

PODDR30DQ0

PODDR30DQ1

PODDR30DQ2

PODDR30DQ3

PODDR30DQ4

PODDR30DQ5

PODDR30DQ6

PODDR30DQ7

PODDR30DQ8

PODDR30DQ9

PODDR30DQ10

PODDR30DQ11

PODDR30DQ12

PODDR30DQ13

PODDR30DQ14

PODDR30DQ15

PODDR30DQ0000150

PODDR30DQS00N

PODDR30DQS00P

PODDR30DQS10N

PODDR30DQS10P

PODDR30ODT

PODDR30RAS

PODDR30RESET

PODDR30WE

POMCASP0ACLKR

POMCASP0ACLKX

POMCASP0AHCLKR

POMCASP0AHCLKX

POMCASP0AMUTE

POMCASP0AXR0

POMCASP0AXR1

POMCASP0AXR2

POMCASP0AXR3

POMCASP0AXR4

POMCASP0AXR5

POMCASP0AXR6

POMCASP0AXR7

POMCASP0AXR8

POMCASP0AXR9

POMCASP0AXR10

POMCASP0AXR11

POMCASP0AXR12

POMCASP0AXR13

POMCASP0AXR14

POMCASP0AXR15

POMCASP0AXR0000150

POMCASP0FSR

POMCASP0FSX

POMCASP1ACLKR

POMCASP1ACLKX

POMCASP1AHCLKR

POMCASP1AMUTE0R

POMCASP1AXR0

POMCASP1AXR1

POMCASP1AXR2

POMCASP1AXR3

POMCASP1AXR4

POMCASP1AXR5

POMCASP1AXR6

POMCASP1AXR7

POMCASP1AXR8

POMCASP1AXR9

POMCASP1AXR000090

POMCASP1FSR

POMCASP1FSX

PORESETSTAT

POSPI20CLK

POSPI20MISO

POSPI20MOSI

POSPI20SCS0

XXXIII

A Appendix

11

22

33

44

DD

CC

BB

AA

Tite

l:

Dat

um:

Seite

Entw

ickl

erkü

rzel

:Em

il-Fi

gge-

Straße

85,

442

27 D

ortm

und

FPG

A_BA

NKS

1.Sc

hDoc

03.0

9.20

18

22

SeD

a

FPG

A_B

AN

KS

1.S

chD

oc

Adre

sse:

Zeit:

13:4

6:51

von

23Ve

rsio

n:

Proj

ekt:

VAD

ER_F

RG

A.Pr

jPcb

v1.0

IO_0

_16

F15

IO_L

1N_T

0_16

F14

IO_L

3P_T

0_D

QS_

16C

14

IO_L

3N_T

0_D

QS_

16C

15

IO_L

24N

_T3_

16G

22

IO_L

2P_T

0_16

F16

IO_L

12N

_T1_

MR

CC

_16

C17

IO_L

5N_T

0_16

D16

IO_L

5P_T

0_16

E16

IO_2

5_16

F21

IO_L

13P_

T2_M

RC

C_1

6C

18

IO_L

2N_T

0_16

E17

IO_L

6N_T

0_V

REF

_16

D15

IO_L

9P_T

1_D

QS_

16A

15

IO_L

7N_T

1_16

B16

IO_L

9N_T

1_D

QS_

16A

16

IO_L

11P_

T1_S

RC

C_1

6B

17

IO_L

19N

_T3_

VR

EF_1

6C

20

IO_L

17P_

T2_1

6A

18

IO_L

17N

_T2_

16A

19

IO_L

11N

_T1_

SRC

C_1

6B

18

IO_L

16N

_T2_

16A

20

IO_L

16P_

T2_1

6B

20

IO_L

12P_

T1_M

RC

C_1

6D

17

IO_L

21N

_T3_

DQ

S_16

A21

IO_L

20N

_T3_

16B

22

IO_L

21P_

T3_D

QS_

16B

21

IO_L

20P_

T3_1

6C

22

IO_L

23N

_T3_

16D

21

IO_L

22N

_T3_

16D

22

IO_L

23P_

T3_1

6E2

1

IO_L

22P_

T3_1

6E2

2

IO_L

18N

_T2_

16F2

0

IO_L

18P_

T2_1

6F1

9

IO_L

15P_

T2_D

QS_

16F1

8

IO_L

14P_

T2_S

RC

C_1

6E1

9

IO_L

14N

_T2_

SRC

C_1

6D

19

IO_L

19P_

T3_1

6D

20

IO_L

15N

_T2_

DQ

S_16

E18

IO_L

4P_T

0_16

E13

IO_L

1P_T

0_16

F13

IO_L

4N_T

0_16

E14

IO_L

10P_

T1_1

6A

13

IO_L

10N

_T1_

16A

14

IO_L

8P_T

1_16

C13

IO_L

8N_T

1_16

B13

IO_L

6P_T

0_16

D14

IO_L

13N

_T2_

MR

CC

_16

C19

IO_L

24P_

T3_1

6G

21

IO_L

7P_T

1_16

B15

BANK 16

U2C

XC

7A35

T-2F

GG

484I

RX

OU

T_B

_13

RX

OU

T_B

_14

RX

OU

T_B

_15

RX

OU

T_B

_16

RX

OU

T_B

_17

RX

OU

T_B

_18

RX

OU

T_B

_19

RX

OU

T_B

_20

RX

OU

T_B

_21

RX

OU

T_B

_22

RX

OU

T_B

_23

RX

OU

T_B

_24

RX

OU

T_B

_25

RX

OU

T_B

_26

RX

OU

T_B

_27

RX

OU

T_B

_[0.

.27]

RX

OU

T_B

_[0.

.27]

IO_L

4P_T

0_15

G17

IO_L

8N_T

1_A

D10

N_1

5G

20

IO_L

4N_T

0_15

G18

IO_L

8P_T

1_A

D10

P_15

H20

IO_L

12N

_T1_

MR

CC

_15

H19

IO_L

11P_

T1_S

RC

C_1

5J2

0

IO_L

12P_

T1_M

RC

C_1

5J1

9

IO_L

13P_

T2_M

RC

C_1

5K

18

IO_L

14N

_T2_

SRC

C_1

5L2

0

IO_L

14P_

T2_S

RC

C_1

5L1

9

IO_L

7N_T

1_A

D2N

_15

H22

IO_L

11N

_T1_

SRC

C_1

5J2

1

IO_L

7P_T

1_A

D2P

_15

J22

IO_L

9P_T

1_D

QS_

AD

3P_1

5K

21

IO_L

9N_T

1_D

QS_

AD

3N_1

5K

22

IO_L

10N

_T1_

AD

11N

_15

L21

IO_L

18N

_T2_

A23

_15

M20

IO_L

15N

_T2_

DQ

S_A

DV

_B_1

5M

22

IO_L

10P_

T1_A

D11

P_15

M21

IO_L

15P_

T2_D

QS_

15N

22

IO_L

3P_T

0_D

QS_

AD

1P_1

5J1

4

IO_L

6P_T

0_15

H17

IO_L

5N_T

0_A

D9N

_15

H15

IO_L

2N_T

0_A

D8N

_15

G16

IO_L

2P_T

0_A

D8P

_15

G15

IO_L

3N_T

0_D

QS_

AD

1N_1

5H

14

IO_L

1P_T

0_A

D0P

_15

H13

IO_L

1N_T

0_A

D0N

_15

G13

IO_L

13N

_T2_

MR

CC

_15

K19

IO_L

19N

_T3_

A21

_VR

EF_1

5K

14

IO_L

5P_T

0_A

D9P

_15

J15

IO_L

17P_

T2_A

26_1

5N

18

IO_L

16N

_T2_

A27

_15

L18

IO_L

24P_

T3_R

S1_1

5M

15

IO_L

20P_

T3_A

20_1

5M

13

IO_L

21N

_T3_

DQ

S_A

18_1

5J1

7

IO_L

6N_T

0_V

REF

_15

H18

IO_0

_15

J16

IO_L

23N

_T3_

FWE_

B_1

5K

16

IO_2

5_15

M17

IO_L

22P_

T3_A

17_1

5L1

4

IO_L

16P_

T2_A

28_1

5M

18

IO_L

21P_

T3_D

QS_

15K

17

IO_L

17N

_T2_

A25

_15

N19

IO_L

23P_

T3_F

OE_

B_1

5L1

6

IO_L

24N

_T3_

RS0

_15

M16

IO_L

22N

_T3_

A16

_15

L15

IO_L

19P_

T3_A

22_1

5K

13

IO_L

20N

_T3_

A19

_15

L13

IO_L

18P_

T2_A

24_1

5N

20

BANK 15

U2B

XC

7A35

T-2F

GG

484I

RX

OU

T_M

_[0.

.27]

RX

CLK

_M

RX

OU

T_M

_0R

XO

UT_

M_1

RX

OU

T_M

_2R

XO

UT_

M_3

RX

OU

T_M

_4R

XO

UT_

M_5

RX

OU

T_M

_6R

XO

UT_

M_7

RX

OU

T_M

_8R

XO

UT_

M_9

RX

OU

T_M

_10

RX

OU

T_M

_11

RX

OU

T_M

_12

RX

OU

T_M

_13

RX

OU

T_M

_14

RX

OU

T_M

_15

RX

OU

T_M

_16

RX

OU

T_M

_17

RX

OU

T_M

_18

RX

OU

T_M

_19

RX

OU

T_M

_20

RX

OU

T_M

_21

RX

OU

T_M

_22

RX

OU

T_M

_23

RX

OU

T_M

_24

RX

OU

T_M

_25

RX

OU

T_M

_26

RX

OU

T_M

_27

RX

OU

T_M

_[0.

.27]

RX

OU

T_B

_0R

XO

UT_

B_1

RX

OU

T_B

_2R

XO

UT_

B_3

RX

OU

T_B

_4R

XO

UT_

B_5

RX

OU

T_B

_6R

XO

UT_

B_7

RX

OU

T_B

_8R

XO

UT_

B_9

RX

OU

T_B

_10

RX

OU

T_B

_11

RX

OU

T_B

_12

RX

CLK

_BR

XC

LK_B

RX

CLK

_B

DIN

_SD

E_S

DIN

C[1

..4]

RO

UT_

SR

E_S

TEM

P_SI

TEM

P_SC

TEM

P_C

S

LD[1

..4]

TEM

P_SO

LD1

LD2

LD3

LD4

LD[1

..4]

AN

Y_T

XA

NY

_OM

1A

NY

_GIP

1A

NY

_RES

ETA

NY

_IR

QA

NY

_GO

P0A

NY

_MI0

AN

Y_G

OP1

AN

Y_M

I1A

NY

_RW

AN

Y_O

EA

NY

_GIP

0A

NY

_LED

1AA

NY

_RX

AN

Y_L

ED2B

AN

Y_O

M0

AN

Y_O

M2

AN

Y_M

D0

AN

Y_C

EA

NY

_LED

1BA

NY

_LED

2A

TEM

P_SO

TEM

P_C

STE

MP_

SCTE

MP_

SI

RE_

SR

OU

T_S

DE_

SD

IN_S

RX

CLK

_MA

NY

_LED

2AA

NY

_LED

1BA

NY

_CE

AN

Y_M

D0

AN

Y_O

M2

AN

Y_O

M0

AN

Y_O

M1

AN

Y_L

ED2B

AN

Y_R

XA

NY

_LED

1AA

NY

_GIP

0A

NY

_OE

AN

Y_R

WA

NY

_MI1

AN

Y_G

OP1

AN

Y_M

I0A

NY

_GO

P0A

NY

_IR

QA

NY

_RES

ETA

NY

_GIP

1

AN

Y_T

X

Ban

k 15

Ban

k 16

ENC

DIN

C1

DIN

C3

DIN

C4

DIN

C2

ENC

DIN

C[1

..4]

PIU20G13

PIU20G15

PIU20G16

PIU20G17

PIU20G18

PIU20G20

PIU20H13

PIU20H14

PIU20H15

PIU20H17

PIU20H18

PIU20H19

PIU20H20

PIU20H22

PIU20J14

PIU20J15

PIU20J16

PIU20J17

PIU20J19

PIU20J20

PIU20J21

PIU20J22

PIU20K13

PIU20K14

PIU20K16

PIU20K17

PIU20K18

PIU20K19

PIU20K21

PIU20K22

PIU20L13

PIU20L14

PIU20L15

PIU20L16

PIU20L18

PIU20L19

PIU20L20

PIU20L21

PIU20M13

PIU20M15

PIU20M16

PIU20M17

PIU20M18

PIU20M20

PIU20M21

PIU20M22

PIU20N18

PIU20N19

PIU20N20

PIU20N22

COU2

B

PIU20A13

PIU20A14

PIU20A15

PIU20A16

PIU20A18

PIU20A19

PIU20A20

PIU20A21

PIU20B13

PIU20B15

PIU20B16

PIU20B17

PIU20B18

PIU20B20

PIU20B21

PIU20B22

PIU20C13

PIU20C14

PIU20C15

PIU20C17

PIU20C18

PIU20C19

PIU20C20

PIU20C22

PIU20D14

PIU20D15

PIU20D16

PIU20D17

PIU20D19

PIU20D20

PIU20D21

PIU20D22

PIU20E13

PIU20E14

PIU20E16

PIU20E17

PIU20E18

PIU20E19

PIU20E21

PIU20E22

PIU20F13

PIU20F14

PIU20F15

PIU20F16

PIU20F18

PIU20F19

PIU20F20

PIU20F21

PIU20G21

PIU20G22

COU2

C

PIU20N18

NLANY0CE

POANY0CE

PIU20K16

NLANY0GIP0

POANY0GIP0

PIU20K13

NLANY0GIP1

POANY0GIP1

PIU20L16

NLANY0GOP0

POANY0GOP0

PIU20K17

NLANY0GOP1

POANY0GOP1

PIU20M16

NLANY0IRQ

POANY0IRQ

PIU20J16

NLAN

Y0LE

D1A

POANY0LED1A

PIU20J15

NLAN

Y0LE

D1B

POANY0LED1B

PIU20K14

NLAN

Y0LE

D2A

POANY0LED2A

PIU20J17

NLAN

Y0LE

D2B

POANY0LED2B

PIU20L18

NLAN

Y0MD

0 POANY0MD0

PIU20N19

NLANY0MI0

POANY0MI0

PIU20M18

NLANY0MI1

POANY0MI1

PIU20M17

NLANY0OE

POANY0OE

PIU20M13

NLAN

Y0OM

0 POANY0OM0

PIU20L13

NLAN

Y0OM

1 POANY0OM1

PIU20M15

NLAN

Y0OM

2 POANY0OM2

PIU20L15

NLAN

Y0RE

SET

POANY0RESET

PIU20L14

NLAN

Y0RW

POANY0RW

PIU20H18

NLAN

Y0RX

POANY0RX

PIU20N20

NLANY0TX

POANY0TX

PIU20D16

NLDE

0S

PODE0S

PIU20E16

NLDIN0S

PODIN0S

PIU20C14

NLEN

C POENC

PIU20B15

PIU20F21

PIU20G21

PIU20G22

PIU20F15

NLRE0S

PORE0S

PIU20F14

NLROUT0S

POROUT0S

PIU20D17

NLRXCLK0B

PORXCLK0B

PIU20J19

NLRX

CLK0

M PORXCLK0M

PIU20C13

NLTE

MP0C

S POTEMP0CS

PIU20B13

NLTE

MP0S

C POTEMP0SC

PIU20D14

NLTEMP0SI

POTEMP0SI

PIU20A14

NLTEMP0SO

POTEMP0SO

PIU20C15

NLDINC010040

NLDINC1

PODINC010040

PIU20D15

NLDINC010040

NLDINC2

PODINC010040

PIU20F16

NLDINC010040

NLDINC3

PODINC010040

PIU20C17

NLDINC010040

NLDINC4

PODINC010040

PIU20E13

NLLD

0100

40

NLLD1

POLD010040

PIU20F13

NLLD

0100

40

NLLD2

POLD010040

PIU20E14

NLLD

0100

40

NLLD3

POLD010040

PIU20A13

NLLD

0100

40

NLLD4

POLD010040

PIU20C18

NLRXOUT0B00000270

NLRX

OUT0

B00

PORXOUT0B00000270

PIU20E17

NLRXOUT0B00000270

NLRX

OUT0

B01

PORXOUT0B00000270

PIU20C19

NLRXOUT0B00000270

NLRX

OUT0

B02

PORXOUT0B00000270

PIU20A15

NLRXOUT0B00000270

NLRX

OUT0

B03

PORXOUT0B00000270

PIU20B16

NLRXOUT0B00000270

NLRX

OUT0

B04

PORXOUT0B00000270

PIU20A16

NLRXOUT0B00000270

NLRX

OUT0

B05

PORXOUT0B00000270

PIU20B17

NLRXOUT0B00000270

NLRX

OUT0

B06

PORXOUT0B00000270

PIU20C20

NLRXOUT0B00000270

NLRX

OUT0

B07

PORXOUT0B00000270

PIU20A18

NLRXOUT0B00000270

NLRX

OUT0

B08

PORXOUT0B00000270

PIU20A19

NLRXOUT0B00000270

NLRX

OUT0

B09

PORXOUT0B00000270

PIU20B18

NLRXOUT0B00000270

NLRXOUT0B010

PORXOUT0B00000270

PIU20A20

NLRXOUT0B00000270

NLRXOUT0B011

PORXOUT0B00000270

PIU20B20

NLRXOUT0B00000270

NLRXOUT0B012

PORXOUT0B00000270

PIU20A21

NLRXOUT0B00000270

NLRXOUT0B013

PORXOUT0B00000270

PIU20B22

NLRXOUT0B00000270

NLRXOUT0B014

PORXOUT0B00000270

PIU20B21

NLRXOUT0B00000270

NLRXOUT0B015

PORXOUT0B00000270

PIU20C22

NLRXOUT0B00000270

NLRXOUT0B016

PORXOUT0B00000270

PIU20D21

NLRXOUT0B00000270

NLRXOUT0B017

PORXOUT0B00000270

PIU20D22

NLRXOUT0B00000270

NLRXOUT0B018

PORXOUT0B00000270

PIU20E21

NLRXOUT0B00000270

NLRXOUT0B019

PORXOUT0B00000270

PIU20E22

NLRXOUT0B00000270

NLRXOUT0B020

PORXOUT0B00000270

PIU20F20

NLRXOUT0B00000270

NLRXOUT0B021

PORXOUT0B00000270

PIU20F19

NLRXOUT0B00000270

NLRXOUT0B022

PORXOUT0B00000270

PIU20F18

NLRXOUT0B00000270

NLRXOUT0B023

PORXOUT0B00000270

PIU20E19

NLRXOUT0B00000270

NLRXOUT0B024

PORXOUT0B00000270

PIU20D19

NLRXOUT0B00000270

NLRXOUT0B025

PORXOUT0B00000270

PIU20D20

NLRXOUT0B00000270

NLRXOUT0B026

PORXOUT0B00000270

PIU20E18

NLRXOUT0B00000270

NLRXOUT0B027

PORXOUT0B00000270

PIU20G17

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M00

PORXOUT0M00000270

PIU20G20

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M01

PORXOUT0M00000270

PIU20G18

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M02

PORXOUT0M00000270

PIU20H20

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M03

PORXOUT0M00000270

PIU20H19

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M04

PORXOUT0M00000270

PIU20J20

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M05

PORXOUT0M00000270

PIU20K18

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M06

PORXOUT0M00000270

PIU20K19

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M07

PORXOUT0M00000270

PIU20L20

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M08

PORXOUT0M00000270

PIU20L19

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M09

PORXOUT0M00000270

PIU20H22

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M010

PORXOUT0M00000270

PIU20J21

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M011

PORXOUT0M00000270

PIU20J22

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M012

PORXOUT0M00000270

PIU20K21

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M013

PORXOUT0M00000270

PIU20K22

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M014

PORXOUT0M00000270

PIU20L21

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M015

PORXOUT0M00000270

PIU20M20

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M016

PORXOUT0M00000270

PIU20M22

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M017

PORXOUT0M00000270

PIU20M21

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M018

PORXOUT0M00000270

PIU20N22

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M019

PORXOUT0M00000270

PIU20J14

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M020

PORXOUT0M00000270

PIU20H17

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M021

PORXOUT0M00000270

PIU20H15

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M022

PORXOUT0M00000270

PIU20G16

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M023

PORXOUT0M00000270

PIU20G15

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M024

PORXOUT0M00000270

PIU20H14

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M025

PORXOUT0M00000270

PIU20H13

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M026

PORXOUT0M00000270

PIU20G13

NLRX

OUT0

M000

0027

0

NLRX

OUT0

M027

PORXOUT0M00000270

POANY0CE

POANY0GIP0

POANY0GIP1

POANY0GOP0

POANY0GOP1

POANY0IRQ

POANY0LED1A

POANY0LED1B

POANY0LED2A

POANY0LED2B

POANY0MD0

POANY0MI0

POANY0MI1

POANY0OE

POANY0OM0

POANY0OM1

POANY0OM2

POANY0RESET

POANY0RW

POANY0RX

POANY0TX

PODE0S

PODIN0S

PODINC1

PODINC2

PODINC3

PODINC4

PODINC010040

POENC

POLD1

POLD2

POLD3

POLD4

POLD010040

PORE0S

POROUT0S

PORXCLK0B

PORXCLK0M

PORXOUT0B00

PORXOUT0B01

PORXOUT0B02

PORXOUT0B03

PORXOUT0B04

PORXOUT0B05

PORXOUT0B06

PORXOUT0B07

PORXOUT0B08

PORXOUT0B09

PORXOUT0B010

PORXOUT0B011

PORXOUT0B012

PORXOUT0B013

PORXOUT0B014

PORXOUT0B015

PORXOUT0B016

PORXOUT0B017

PORXOUT0B018

PORXOUT0B019

PORXOUT0B020

PORXOUT0B021

PORXOUT0B022

PORXOUT0B023

PORXOUT0B024

PORXOUT0B025

PORXOUT0B026

PORXOUT0B027

PORXOUT0B00000270

PORXOUT0M00

PORXOUT0M01

PORXOUT0M02

PORXOUT0M03

PORXOUT0M04

PORXOUT0M05

PORXOUT0M06

PORXOUT0M07

PORXOUT0M08

PORXOUT0M09

PORXOUT0M010

PORXOUT0M011

PORXOUT0M012

PORXOUT0M013

PORXOUT0M014

PORXOUT0M015

PORXOUT0M016

PORXOUT0M017

PORXOUT0M018

PORXOUT0M019

PORXOUT0M020

PORXOUT0M021

PORXOUT0M022

PORXOUT0M023

PORXOUT0M024

PORXOUT0M025

PORXOUT0M026

PORXOUT0M027

PORXOUT0M00000270

POTEMP0CS

POTEMP0SC

POTEMP0SI

POTEMP0SO

XXXIV