Machine Language ELEC 330 Digital Systems Engineering Dr. Ron Hayne
Jan 17, 2016
Machine Language
ELEC 330
Digital Systems Engineering
Dr. Ron Hayne
330_02 2
The 68HC11 Microcomputer
Programming Model Memory Model Microprocessor Model
Internal Computer Operations Instruction Fetch Instruction Execution
Machine Language Programming
330_02 3
Programming Model
Motorola 68HC11 Microcomputer
7 A 0
7 B 0 8-bit Accumulators A & B
15 D 0 16-bit Double Accumulator D
15 X 0 Index Register X
15 Y 0 Index Register Y
15 SP 0 Stack Pointer
15 PC 0 Program Counter
S X H I N Z V C Condition Code Register
330_02 4
Memory Model
0000
C329 B6
C23A C1
C23B 33
FFFF 22
330_02 5
Instruction Format
Load Accumulator A LDAA $C200
C100 B6 Op Code of LDAA
C101 C2 Address of Data
C102 00
C200 44 Data number
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Microprocessor Model
Program Counter Instruction Register Accumulators
PC
IR
A
B
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Computer Operation
Example Instruction (LDAA) Register and Memory contents
PC
C100 B6 C1 00
C101 C2 IR
C102 00
A
22
B
C200 44 33
330_02 8
Instruction Fetch
PC to Memory as Address Read
PC
C100 B6 C1 00
C101 C2 IR
C102 00
A
22
B
C200 44 33
330_02 9
Instruction Fetch
Memory sends number at address to IR Increment PC
PC
C100 B6 C1 01
C101 C2 IR
C102 00 B6
A
22
B
C200 44 33
330_02 10
Instruction Fetch
PC to Memory as Address Read
PC
C100 B6 C1 01
C101 C2 IR
C102 00 B6
A
22
B
C200 44 33
330_02 11
Instruction Fetch
Memory sends number at address to IR Increment PC
PC
C100 B6 C1 02
C101 C2 IR
C102 00 B6 C2
A
22
B
C200 44 33
330_02 12
Instruction Fetch
PC to Memory as Address Read
PC
C100 B6 C1 02
C101 C2 IR
C102 00 B6 C2
A
22
B
C200 44 33
330_02 13
Instruction Fetch
Memory sends number at address to IR Increment PC
PC
C100 B6 C1 03
C101 C2 IR
C102 00 B6 C2 00
A
22
B
C200 44 33
330_02 14
Instruction Fetch
Register Contents after Fetch
PC
C100 B6 C1 03
C101 C2 IR
C102 00 B6 C2 00
A
22
B
C200 44 33
330_02 15
Instruction Execution
Data Address to Memory Read
PC
C100 B6 C1 03
C101 C2 IR
C102 00 B6 C2 00
A
22
B
C200 44 33
330_02 16
Instruction Execution
Memory sends data at address to A
PC
C100 B6 C1 03
C101 C2 IR
C102 00 B6 C2 00
A
44
B
C200 44 33
330_02 17
Instruction Execution
Final Register Contents
PC
C100 B6 C1 03
C101 C2 IR
C102 00 B6 C2 00
A
44
B
C200 44 33
330_02 18
Instruction Set Table
Operand hh ll high and low bytes of address
SourceForm
OperationBoolean
Expression
Machine Code BytesOp
CodeOperand
ADDA Add Memory to A A + M A BB hh ll 3
LDAA Load Accumulator A M A B6 hh ll 3
STAA Store Accumulator A A M B7 hh ll 3
STOP Stop Program 3F 1
330_02 19
Machine Language Programming
N1 + N2 SUM PC
LDAA C200 B6 C2 00
C201 C2 A
C202 0B
ADDA C203 BB B
C204 C2
C205 0C
STAA C206 B7
C207 C2 N1 C20B 02
C208 0D N2 C20C 29
STOP C209 3F SUM C20D FF
C20A
330_02 20
Machine Language Programming
N1 + N2 SUM PC
LDAA C200 B6 C2 03
C201 C2 A
C202 0B 02
ADDA C203 BB B
C204 C2
C205 0C
STAA C206 B7
C207 C2 N1 C20B 02
C208 0D N2 C20C 29
STOP C209 3F SUM C20D FF
C20A
330_02 21
Machine Language Programming
N1 + N2 SUM PC
LDAA C200 B6 C2 06
C201 C2 A
C202 0B 2B
ADDA C203 BB B
C204 C2
C205 0C
STAA C206 B7
C207 C2 N1 C20B 02
C208 0D N2 C20C 29
STOP C209 3F SUM C20D FF
C20A
330_02 22
Machine Language Programming
N1 + N2 SUM PC
LDAA C200 B6 C2 09
C201 C2 A
C202 0B 2B
ADDA C203 BB B
C204 C2
C205 0C
STAA C206 B7
C207 C2 N1 C20B 02
C208 0D N2 C20C 29
STOP C209 3F SUM C20D 2B
C20A
330_02 23
Machine Language Programming
N1 + N2 SUM PC
LDAA C200 B6 C2 0A
C201 C2 A
C202 0B 2B
ADDA C203 BB B
C204 C2
C205 0C
STAA C206 B7
C207 C2 N1 C20B 02
C208 0D N2 C20C 29
STOP C209 3F SUM C20D 2B
C20A
330_02 24
Summary
Programming Model Memory Model Microprocessor Model
Internal Computer Operations Instruction Fetch Instruction Execution
Machine Language Programming
330_02 25
Instructions and Addressing
Addressing Modes Extended Addressing Direct Addressing Inherent Addressing Immediate Addressing Indexed Addressing Relative Addressing
330_02 26
Addressing
Effective Address Address formed by microprocessor as part of
instruction execution
Addressing Modes Various ways addresses are formed
Memory Map Visual technique for understanding implications
of addressing modes
330_02 27
Extended Addressing
Complete 16-bit Address of Data PC
LDAA C200 B6 C2 00
EXT C201 C2 A
C202 0B
ADDA C203 BB B
EXT C204 C2
C205 0C
STAA C206 B7
EXT C207 C2 N1 C20B 02
C208 0D N2 C20C 29
STOP C209 3F SUM C20D FF
C20A
330_02 28
Direct Addressing
Shortened 8-bit Address Most-significant byte 00
Address Range 0000 through 00FF Zero Page Addressing
Shorter and Faster Instructions Use less memory Fetched faster
N1 0010 02
N2 0011 29
SUM 0012 FF
LDAA C200 96
DIR C201 10
ADDA C202 9B
DIR C203 11
STAA C204 97
DIR C205 12
STOP C206 3F
330_02 29
Inherent (Implied) Addressing
Some instructions operate on microprocessor registers only No memory address needed
Example ABA A + B A
N1 0010 02
N2 0011 29
SUM 0012 FF
LDAA C200 96
DIR C201 10
LDAB C202 D6
DIR C203 11
ABA C204 1B
STAA C205 97
DIR C206 12
STOP C207 3F
330_02 30
Double-Byte Data
Some registers hold 16-bit (double-byte) data D, X, Y, SP
Example LDX M:(M+1) X
Big-endian convention High byte at first (lower)
address Low byte at second
(higher) address
LDX FE
EXT C2
34
X
C234 56 56 78
C235 78
330_02 31
Immediate Addressing
Constant data placed inside an instruction No memory address Fewer bytes of memory
Data immediately available at end of fetch phase Faster execution
LDAA 86 A
IMM 22 22
LDX CE X
IMM 12 12 34
34
330_02 32
Indexed Addressing
Op Code and Offset Byte Effective Address
Offset (unsigned) added to Index Register (pointer)
Index Register unchanged
Example LDAA 2,X M[2+X] A
LDAA A6 A
INDX 02 47
C200 22 X
C201 33 C2 00
C202 47
C203 B7
330_02 33
Relative Addressing
Branch Instructions Make decisions Alter program flow
Condition Code Register Reports test results
S X H I N Z V C Condition Code Register
330_02 34
Condition Code Bits
C (Carry) Carry-out from the
most-significant bit
V (Overflow) Two’s complement
overflow error
Z (Zero) Result contains all zeros
N (Negative) Result is negative
H (Half-carry) Carry from halfway
(bit 3) Generally used only
with BCD numbers
S, X, I Hardware control bits
(later...)
330_02 35
Example
ADDA
C H
1 1 1 1
1 0 1 0 1 0 1 0 A = N1
+ 1 0 1 1 1 1 0 0 M = N2
0 1 1 0 0 1 1 0 A = SUM
N
x x 1 x 0 0 1 1 CCR
S X H I N Z V C
330_02 36
Condition Code Notation
Not all instructions affect all the condition code bits Always use the instruction set table to determine
how the bits work Don’t assume!
Symbol Operation
- Bit is unaffected by this instruction
0 Bit is always cleared to 0 by this instruction
1 Bit is always set to 1 by this instruction
Bit is set or cleared depending on instruction
330_02 37
Branch Instructions
May alter program flow based on the condition code bits Program Counter
Relative Addressing Signed Offset
Effective Address PC plus Offset Branch Range?
Op Code 27 PC
Offset 04 xx xx
No Branch
Branch
330_02 38
Branch Not Equal to Zero
BNE Branch if Not = Zero ? Z = 0
Example LDAA N1
LOOP ADDA #-1
BNE LOOP
STOP
N1 0010 04
LDAA C200 96
DIR C201 10
ADDA C202 8B
IMM C203 FF
BNE C204 26
REL C205 FC
STOP C206 3F
C273
330_02 39
Addressing Mode Summary
INHERENT Op Code
IMMEDIATE Op Code Op Code
Data Data-high
Data-low
DIRECT Op Code Effective Address
Address-low 00 dd
EXTENDED Op Code Effective Address
Address-high hh ll
Address-low
330_02 40
Addressing Mode Summary
INDEXED Op Code Effective Address
Offset +
Index Register
RELATIVE Op Code Effective Address
Relative offset +
Program Counter
330_02 41
Basic Instructions
Arithmetic and Logic Load and Store
Input and Output
Testing and Branching
330_02 42
Programming Model
Motorola 68HC11 Microcomputer
7 A 0
7 B 0 8-bit Accumulators A & B
15 D 0 16-bit Double Accumulator D
15 X 0 Index Register X
15 Y 0 Index Register Y
15 SP 0 Stack Pointer
15 PC 0 Program Counter
S X H I N Z V C Condition Code Register
330_02 43
Instruction Set Table
Source Form Instruction mnemonic Type of operand
(opr) data or data address (rel) relative offset
Operation Short word description
Booelan Expression Detailed description of register transfers
Addressing Mode
330_02 44
Instruction Set Table
Op Code Machine code for corresponding addressing mode
Operand ii 8-bit immediate data dd low byte of direct address hh ll high and low bytes of extended address ff unsigned 8-bit offset for indexed addressing jj kk high and low bytes of 16-bit immediate data rr signed 8-bit relative offset for branch
330_02 45
Instruction Set Table
Bytes Number of bytes of memory (op code + operand)
Cycles Number of clock cycles to fetch and execute
Condition Codes
Symbol Operation
- Bit is unaffected by this instruction
0 Bit is always cleared to 0 by this instruction
1 Bit is always set to 1 by this instruction
Bit is set or cleared depending on instruction
330_02 46
Instruction Set Table
SourceForm
OperationBoolean
ExpressionAddr.Mode
Machine Code Bytes
Cycles
OpCode
Op-erand
ABX Add B to X X + 00:B X INH 3A 1 3
ADDA (opr) Add Memory to A
A + M A A IMMA DIRA EXTA IND,XA IND,Y
8B9BBBAB
18 AB
iiddhh llffff
22323
23445
CLC Clear Carry Bit 0 C INH 0C 1 2
LDX (opr) Load Index Register X
M:(M + 1) X X IMMX DIR
CEDE
jj kkdd
32
34
330_02 47
Instruction Set Table (cont)
SourceForm
OperationBoolean
Expression
Condition Codes
S X H I N Z V C
ABX Add B to X X + 00:B X - - - - - - - -
ADDA (opr) Add Memory to A
A + M A - - -
CLC Clear Carry Bit 0 C - - - - - - - 0
LDX (opr) Load Index Register X
M:(M + 1) X - - - - 0 -
330_02 48
Arithmetic and Logic
ABA Add B to A
ABX Add B to X
ADDA, ADDB, ADDD Add memory to accumulator
ADCA, ADCB Add memory with carry to accumulator
330_02 49
Arithmetic and Logic
DEC, DECA, DECB Decrement memory or accumulator
DEX Decrement X
INC, INCA, INCB Increment memory or accumulator
INX Increment X
330_02 50
Arithmetic and Logic
NEG, NEGA, NEGB Negate memory or accumulator
SBA Subtract B from A
SBCA, SBCB Subtract with carry
SUBA, SUBB, SUBD Subtract memory from accumulator
330_02 51
Arithmetic and Logic
COM, COMA, COMB Complement memory or accumulator
ANDA, ANDB AND memory with accumulator
ORAA, ORAB OR memory with accumulator
EORA, EORB Exclusive OR memory with accumulator
330_02 52
Load and Store
LDAA, LDAB, LDD, LDX Load accumulator or index register from memory
STAA, STAB, STD, STX Store accumulator or index register into memory
TAB, TBA Transfer (copy) A to B or B to A
TPA Transfer condition codes to A
330_02 53
Testing and Branching
TST, TSTA, TSTB Test memory or
accumulator
CLR, CLRA, CLRB Clear memory or
accumulator
CLC, CLV Clear the carry or overflow
SEC, SEV Set the carry or overflow
BRA Branch always Relative addressing
JMP Jump (always) Extended, indexed
addressing
NOP No operation
330_02 54
Testing and Branching
BMI Branch on minus
BPL Branch on plus
BEQ Branch on equal to zero
BNE Branch on not equal to
zero
BCC Branch on carry clear
BCS Branch on carry set
BVC Branch on overflow clear
BVS Branch on overflow set
330_02 55
Comparison Branching
CBA Compare B to A
CMPA, CMPB Compare accumulator to memory
CPX Compare X to memory
SBA, SUBA, SUBB Subtraction
330_02 56
Comparison Branching
BGT Branch if greater than
BGE Branch if greater than
or equal to
BLT Branch if less than
BLE Branch if less than
or equal to
BHI Branch if higher
BHS Branch if higher
or same
BLO Branch if lower
BLS Branch if lower
or same
330_02 57
Instruction Summary
Arithmetic and Logic Load and Store
Input and Output
Testing and Branching
330_02 58
Machine Language Programming
Minimum Requirements of a Good Program Example
Copy a Table
Basic Program Loop Pointer Counter
330_02 59
Minimum Requirements of a Good Program
The program must: do the same thing every time not modify itself work correctly for all reasonable data values
The program should: separate instructions and data in memory adapt easily to different sets of data start at the first instruction and stop at the last
330_02 60
Copy a Table Example
Before After
C110 11 C110 11
C111 22 C111 22
C112 33 C112 33
C113 44 C113 44
C130 37 C130 11
C131 02 C131 22
C132 7A C132 33
C133 C1 C133 44
330_02 61
Brainstorming
Possible Approaches Copy-a-table Instruction Copy a Memory Byte Load and Store A Loop
330_02 62
Basic Program Loop
Pointer Points to the table entry to be copied Index Register X
Counter Counts entries to be copied Memory Register
Counting Method Initialize to number of entries Decrement to zero
330_02 63
Pointer and Counter
04 Counter
X
C110 11 Pointer
C111 22
C112 33 A
C113 44
C130 37
C131 02
C132 7A
C133 C1
330_02 64
Basic Program
Initialize Pointer Initialize Counter Break out of Loop Copy One Entry Advance Pointer Decrement Counter Loop Stop
330_02 65
Copy Table Program
Address Contents Instruction Description
0030 C1 Address of first table
0031 10
0032 04 Table length
0033 xx Working counter
C010 DE LDX DIR Initialize pointer to
C011 30 first table
C012 96 LDAA DIR Get initial counter
C013 32 value
C014 97 STAA DIR Store initial counter
C015 33 into working counter
330_02 66
Copy Table Program
Address Contents Instruction Description
C016 27 BEQ REL Branch to STOP (+10) if
C017 0A counter equals zero
C018 A6 LDAA IND,X Get next entry from
C019 00 first table
C01A A7 STAA IND,X Put entry into
C01B 20 second table
C01C 08 INX Advance pointer
C01D 7A DEC EXT Decrement working counter
C01E 00
C01F 33
C020 20 BRA REL Loop (-12) to BEQ
C021 F4
C022 3F STOP Stop the program
330_02 67
Limitations and Problems
Location of Tables Size of Tables Branch Dependency Mixing of program and data
330_02 68
Improved Copy Table Program
Address Contents Instruction Description
0020 C2 Address of first table
0021 20
0022 20 Spacing between tables
0023 04 Table length
0024 xx Working counter
0025 xx Save pointer
0026 xx
C100 DE LDX DIR Get address of
C101 20 first table
C102 DF STX DIR Store in save pointer
C103 25 location
330_02 69
Improved Copy Table Program
Address Contents Instruction Description
C104 96 LDAA DIR Get initial counter
C105 23 value
C106 97 STAA DIR Store initial counter
C107 24 into working counter
C108 D6 LDAB DIR Get table spacing
C109 22
C10A 7D TST EXT Test working counter
C10B 00
C10C 24
C10D 27 BEQ REL Branch to STOP (+17) if
C10E 11 counter equals zero
C10F DE LDX DIR Restore pointer to
C110 25 first table
330_02 70
Improved Copy Table Program
Address Contents Instruction Description
C111 A6 LDAA IND,X Get next entry from
C112 00 first table
C113 3A ABX INH Adjust ptr to second table
C114 A7 STAA IND,X Put entry into
C115 00 second table
C116 7A DEC EXT Decrement working counter
C117 00
C118 24
C119 DE LDX DIR Get pointer value
C11A 25
C11B 08 INX Advance pointer
C11C DF STX DIR Store pointer
C11D 25
330_02 71
Improved Copy Table Program
Address Contents Instruction Description
C11E 20 BRA REL Loop (-22) to TST
C11F EA
C120 20 BRA REL Loop to Here
C121 FE (Stop)
330_02 72
Summary
Minimum Requirements of a Good Program Basic Program Loop
Pointer Counter
Example Copy a Table Improved Copy Table Program