M2: Team Paradigm :: Milestone 3 2-D Discrete Cosine Transform Group M2: Tommy Taylor Brandon Hsiung Changshi Xiao Bongkwan Kim Project Manager: Yaping.

M2: Team Paradigm

:: Milestone 3 2-D Discrete Cosine Transform

Group M2:Tommy Taylor Brandon HsiungChangshi XiaoBongkwan Kim

Project Manager: Yaping Zhan

Feb 2nd 2004

Size estimates/Floor plan

M2: Team Paradigm

Team Paradigm

M2: Team Paradigm

Project statusDesign Proposal (Complete)Architecture Proposal (Complete): Algorithm description (Done): High level simulation (Done): Mapping algorithm into hardware (Done): Behavioral Verilog and test bench (Done, bug

fixed)Size estimates/floor plan (Complete): Structural Verilog (Done): More accurate transistor count (Done): Floor plan (Done)

M2: Team Paradigm

Design decisions

Do not include motion prediction

Go with 2-D DCT

Use SRAM

No pipelining

Will not run in real-time

M2: Team Paradigm

1D DCT architecture

out_data(16)

Selector

+ -

+ +R R

Parallel to serial

Control logic

ROM

in_data(16)

in_valid

out_valid

out_ready

out_done

clk

vdd

vss

reset

Register file 8x16

Register file 8x16

Bit addressgenerator

Bit addressgenerator

ROM

M2: Team Paradigm

2D DCT :

Two 1D DCT can operate in pipeline to boost throughput performance, this requires RAM can be read and wrote at the same time and each 1D DCT module read/write the RAM in row and column order alternatively.

1D DCT (on rows)

1D DCT (on columns)

Transpose RAM

Data in

Data out

Control logic

M2: Team Paradigm

Transistor count and performance estimation :

adder register ROM Control logic total pins

4x(15x24+14)4x374=1496

18x16x15=4320

8x16x2=256

1000 ~10.5k 40

1DDCT module :

2DDCT = 2x1DDCT + SRAM ~ 29k

throughput latency

8 samples/64 cycle 528 cycle

Shift Register Muxes SRAM

mux(44x20)+ff(18x15)=1150

2560 8000

M2: Team Paradigm

New vs old estimation

adder register ROM Control logic

SRAM Total

1920 5760 256 1000 6000 24k

Old estimation:

adder register ROM Control logic

Muxes SRAM Total

1496 4590 256 1000 3440 8000 29k

New estimation

M2: Team Paradigm

1D DCTSimply repeat on rows to make 2D

-

Selector

R0 R7

R7R0

Bit Address Generator

R0 R7

Rom0 Rom7

R5 R6S1S0

Parallel to Serial

bit 1bit 1bit 1bit 1

1011

M2: Team Paradigm

Verilog

M2: Team Paradigm

Verilog

M2: Team Paradigm

Layout Size Proposal

: Using a reference of an inverter- 5u x 2.3u =11.5u total area- Contain 2 transistors

: Our design has total of approx 29k- add space for wiring

: Total area estimation of around 162,500 + 30,000

: =190,000um2

M2: Team Paradigm

Layout Proposal 1D DCT

MUX4x1

32'

Sub

Add

DeMux4x1

DeMux4x1 Reg

8x16'

R7

R0

R6

R1

R5

R2

R4

R1

Take bits 0-

15

Take bits 16-

32

Add

Add

Rom

Rom

ShiftReg

ControlLogic

approx. 70,000um2

M2: Team Paradigm

Overall floor plan

1D DCT1D

DC

T

SRAM

1D D

CT

150

200

200

350

Dimensions: 550 x 350 =192500um2

M2: Team Paradigm

Interconnect

: Metals 1 & 2 used locally- Metal 1 is horizontal- Metal 2 is vertical

: Metals 3 & 4 used globally- Metal 3 is horizontal- Metal 4 is vertical

: Metal 4 reserved for clk and rst

M2: Team Paradigm

::conclusion & questions

: Roughly 29k transistor count

: Will try to optimize design further and enhance performance