M S Engineering College Navarathna Agrahara, Sadahalli Post Off. Kempe Gowda International Airport Road, Bengaluru - 562110, Karnataka, India, HDL LAB MANUAL (17ECL58) Prof. Tejaswini C Associate Professor Department of Electronics and Communication Engineering M. S. Engineering College, Bengaluru – 562110
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M S Engineering College Navarathna Agrahara, Sadahalli Post
Off. Kempe Gowda International Airport Road,
Bengaluru - 562110, Karnataka, India,
HDL LAB MANUAL
(17ECL58)
Prof. Tejaswini C Associate Professor
Department of Electronics and Communication Engineering
M. S. Engineering College, Bengaluru – 562110
M S Engineering College
Vision
M.S.Engineering College shall blossom into a technical institution of national importance with global network.
Mission
• To be the leading institution in imparting Quality Engineering Education with value systems amongst students to face global challenges.
• To inculcate best engineering practices amongst students through quality education, creativity, innovation and entrepreneurial skills.
• To make the institute to be recognized as among the leading institutions imparting Quality Engineering Education; To produce world class professionals who possess knowledge, skills and necessary values that help them take challenges at a global level
Quality Policy
Striving for Excellence in Quality Engineering Education.
Our commitment to comply with mandatory requirements.
Continually improve the effectiveness and quality management system.
Our commitment to achieve total customer satisfaction by assuring successful completion of the degree with skill sets to solve the Engineering problems
By providing training at all the levels with placement assistance.
Use of modern technology and its conditional up gradation.
Participation of all the stakeholders to meet the expectations.
Department of Electronics and Communication Engineering
Vision
To equip students with strong technical knowledge by logical and innovative thinking in Electronics and Communication Engineering domain to meet expectations of the industry as well as society.
Mission
To educate a new generation of Electronics and Communication Engineers by providing them with a strong theoretical foundation, good design experience and exposure to research and development to meet ever changing and ever demanding needs of the Electronic Industry in particular, along with IT & other inter disciplinary fields in general.
Provide ethical and value based education by promoting activities addressing the societal needs.
To build up knowledge and skills of students to face the challenges across the globe with confidence and ease.
Quality Policy
Our quality policy is to develop an effective source of technical man power with the ability to adapt to an intellectually and technologically changing environment to contribute to the growth of nation with the participative efforts of the management, staff, students and industry while keeping up ethical and moral standards required
Program Outcomes:
1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering fundamentals, and an engineering specialization to the solution of complex engineering problems.
2. Problem analysis: Identify, formulate, review research literature, and analyze complex engineering problems reaching substantiated conclusions using first principles of mathematics, natural sciences, and engineering sciences.
3. Design/development of solutions: Design solutions for complex engineering problems and design system components or processes that meet the specified needs with appropriate consideration for the public health and safety, and the cultural, societal, and environmental considerations.
4. Conduct investigations of complex problems: Use research-based knowledge and research methods including design of experiments, analysis and interpretation of data, and synthesis of the information to provide valid conclusions.
5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern engineering and IT tools including prediction and modeling to complex engineering activities with an understanding of the limitations.
6. The engineer and society: Apply reasoning informed by the contextual knowledge to assess societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to the professional engineering practice.
7. Environment and sustainability: Understand the impact of the professional engineering Solutions in societal and environmental contexts, and demonstrate the knowledge of, and need for sustainable development.
8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms of the engineering practice.
9. Individual and team work: Function effectively as an individual, and as a member or leader in diverse teams, and in multidisciplinary settings.
10. Communication: Communicate effectively on complex engineering activities with the engineering community and with society at large, such as, being able to comprehend and write effective reports and design documentation, make effective presentations, and give and receive clear instructions.
11. Project management and finance: Demonstrate knowledge and understanding of the engineering and management principles and apply these to one’s own work, as a member and leader in a team, to manage projects and in multidisciplinary environments.
12. Life-long learning: Recognize the need for, and have the preparation and ability to
engage in independent and life-long learning in the broadest context of technological change.
PSO-Program Specific Objectives
1. An ability to understand the concepts of basic Electronics & Communication Engineering and to apply them to various areas like Signal processing, VLSI, Embedded systems, Communication Systems, Digital & Analog Devices, etc.
2. An ability to solve complex Electronics and Communication Engineering problems, using latest hardware and software tools, along with analytical skills to arrive cost effective and appropriate solutions.
3. Wisdom of social and environmental awareness along with ethical responsibility to have a successful career and to sustain passion and zeal for real-world applications using optimal resources as an Entrepreneur.
Program Educational Objectives
PEO I: To develop the ability among students to understand the concept of core electronics
subjects that will facilitate understanding of new technology.
PEO II: To embed a strong foundation in the engineering fundamentals to solve, analyze and
design real time engineering products.
PEO III: To give exposures to emerging edge technologies, adequate training and
opportunities to work as team on multidisciplinary projects with effective communication
skills and leadership qualities.
HDL LAB
V SEMESTER ELECTRONICS AND COMMUNICATION ENGINEERING
Sub Code
17ECL58
CIE Marks
40
Number of Lecture
Hours/Week
03
SEE Marks 60
RBT Levels L1, L2, L3 Exam Hours 03Hrs
Course Objectives:
This course will enable students to:
Familiarize with the CAD tool to write HDL
programs.
Understand simulation and synthesis of digital
design.
Program FPGAs/CPLDs to synthesize the digital
designs.
Interface hardware to programmable ICs through
I/O ports.
Choose either Verilog or VHDL for a given
Abstraction level.
Note: Programming can be done using any compiler. Download the programs on a
FPGA/CPLD boards such as Apex/Max/Spartan/Sinfi or equivalent and performance testing
may be done using 32 channel pattern generator and logic analyzer apart from verification by
simulation with tools such as Altera /Modelsim or equivalent.
Course Syllabus (As Per VTU CBCS Scheme 2017)
Part–A: PROGRAMMING
1. Write Verilog code to realize all the logic gates
2. Write a Verilog program for the following combinational designs
a. 2 to 4 decoder
b. 8 to 3 (encoder without priority & with priority)
c. 8 to 1 multiplexer.
d. 4 bit binary to gray converter
e. Multiplexer, de-multiplexer, comparator.
3. Write a VHDL and Verilog code to describe the functions of a Full Adder using three
modeling styles.
4. Write a Verilog code to model 32 bit ALU using the schematic diagram shown below
ALU should use combinational logic to calculate an output based on the four bit op-code
input. ALU should pass the result to the out bus when enable line in high, and tri-state the
out bus when the enable line is low. ALU should decode the 4 bit op-code according to the
example given below
OPCODE ALU Operation
1. A+B
2. A-B
3. A Complement
4. A*B
5. A AND B
6. A OR B
7. A NAND B
8. A XOR B
5. Develop the Verilog code for the following flip-flops, SR, D, JK and T.
6. Design a 4 bit binary, BCD counters (Synchronous reset and Asynchronous reset) and
"any sequence" counters, using Verilog code.
Part–B: INTERFACING (at least four of the following must be covered using
VHDL/Verilog)
1. Write HDL code to display messages on an alpha numeric LCD display.
2. Write HDL code to interface Hex key pad and display the key code on seven segment
display.
3. Write HDL code to control speed, direction of DC and Stepper motor.
4. Write HDL code to accept Analog signal, Temperature sensor and display the data on
LCD or Seven segment display.
5. Write HDL code to generate different waveforms (Sine, Square, Triangle, Ramp etc.,)
using DAC - change the frequency.
6. Write HDL code to simulate Elevator operation.
Course Outcomes:
At the end of this course, students should be able to:
Write the Verilog /VHDL programs to simulate Combinational circuits in Dataflow,
Behavioral and Gate level Abstractions.
Describe sequential circuits like flip flops and counters in Behavioral description and
obtain simulation waveforms.
Synthesize Combinational and Sequential circuits on programmable ICs and test the
hardware.
Interface the hardware to the programmable chips and obtain the required output.
Conduct of Practical Examination: 1. All laboratory experiments are to be included for practical examination.
2. Strictly follow the instructions as printed on the cover page of answer script for breakup of
marks.
3. Change of experiment is allowed only once and Marks allotted to the procedure part to be
made zero.
LIST OF EXPERIMENTS
CYCLE I Page No MARKS
1 Write Verilog code to realize all the logic gates 9- 18
2 Write a Verilog program for the following combinational designs
a. 2 to 4 decoder
b. 8 to 3 (encoder without priority & with priority)
c. 8 to 1 multiplexer.
d. 4 bit binary to gray converter
e. Multiplexer, de-multiplexer, comparator.
19- 30
3 Write a VHDL and Verilog code to describe the functions of a
Full Adder using three modeling styles. 31- 34
4 Write a Verilog code to model 32 bit ALU 35 - 37
5 Develop the Verilog code for the following flip-flops, SR, D, JK
and T. 38 - 44
6 Design a 4 bit binary, BCD counters (Synchronous reset and
Asynchronous reset ) and “any sequence” counters, using Verilog
code.
45 - 50
CYCLE II
1 Write HDL code to display messages on an alpha numeric LCD display.
51 - 53
2 Write HDL code to control speed, direction of DC and Stepper
motor.
Write HDL code to interface Hex key pad and display the key
code on seven segment display.
54 - 56
3 Write HDL code to generate different waveforms (Sine, Square,
Triangle, Ramp etc.,) using DAC - change the frequency. 57 - 63
4 Write HDL code to simulate Elevator operation.
64 - 68
AVERAGE
Scheme of Evaluation
IA Evaluation
Record
maintenance
(weekly submission)
Conduction of Lab Internals Total
Write up Execution of the
required Result
Viva
20M 5M 10M 5M 40M
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OVERVIEW OF HDL LAB
HDL
In electronics, a hardware description language or HDL is any language from a class of
Computer languages for formal description of electronic circuits. It can describe the circuit's
operation, its design and organization, and tests to verify its operation by means of simulation
HDLs are standard text-based expressions of the spatial, temporal structure and behavior of
electronic systems. In contrast to a software programming language, HDL syntax, semantics
include explicit notations for expressing time and concurrency, which are the attributes of
hardware. Languages whose only characteristic is to express circuit connectivity between a
hierarchies of blocks are properly classified as netlist languages.
HDLs are used to write executable specifications of some piece of hardware. A simulation
program, designed to implement the underlying semantics of the language statements,
coupled with simulating the progress of time, provides the hardware designer with the
ability to model a piece of hardware before it is created physically. It is this execute ability
that gives HDLs the illusion of being programming languages. Simulators capable of supporting
discrete-event and continuous-time (analog) modeling exist, and HDLs targeted for each are
available.
It is certainly possible to represent hardware semantics using traditional programming languages
such as C++, although to function such programs must be augmented with extensive and
unwieldy class libraries. Primarily, however, software programming languages function as a
hardware description language
Using the proper subset of virtually any language, a software program called a synthesizer
can infer hardware logic operations from the language statements and produce an equivalent
netlist of generic hardware primitives to implement the specified behavior. This typically
requires the synthesizer to ignore the expression of any timing constructs in the text.
The two most widely-used and well-supported HDL varieties used in industry are
VHDL (VHSIC HDL)
Verilog
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VHDL
VHDL (Very High Speed Integrated Circuit Hardware Description Language) is
commonly used as a design-entry language for field-programmable gate arrays and application-
specific integrated circuits in electronic design automation of digital circuits.
VHDL is a fairly general-purpose language, and it doesn’t require a simulator on which to run
the code. There are a lot of VHDL compilers, which build executable binaries. It can read and
write files on the host computer, so a VHDL program can be written that generates another
VHDL program to be incorporated in the design being developed. Because of this general-
purpose nature, it is possible to use VHDL to write a test bench that verifies with the user,
and compares results with those expected. This is similar to the capabilities of the Verilog
language
VHDL is not a case sensitive language. One can design hardware in a VHDL IDE (such as
Xilinx) to produce the RTL schematic of the desired circuit. After that, the generated schematic
can be verified using simulation software (such as ModelSim) which shows the waveforms of
inputs and outputs of the circuit after generating the appropriate test bench. To generate an
appropriate test bench for a particular circuit or VHDL code, the inputs have to be defined
correctly. For example, for clock input, a loop process or an iterative statement is required.
The key advantage of VHDL when used for systems design is that it allows the behavior of the
required system to be described (modeled) and verified (simulated) before synthesis tools
translate the design into real hardware (gates and wires). When a VHDL model is
translated into the "gates and wires" that are mapped onto a programmable logic device such
as a CPLD or FPGA, then it is the actual hardware being configured, rather than the
VHDL code being "executed" as if on some form of a processor chip.
Both VHDL and Verilog emerged as the dominant HDLs in the electronics industry while
older and less-capable HDLs gradually disappeared from use. But VHDL and Verilog share
many of the same limitations: neither HDL is suitable for analog/mixed-signal circuit
simulation. Neither possesses language constructs to describe recursively-generated logic
structures
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Verilog
Verilog is a hardware description language (HDL) used to model electronic systems. The
language supports the design, verification, and implementation of analog, digital, and mixed -
signal circuits at various levels of abstraction
The designers of Verilog wanted a language with syntax similar to the C programming
language so that it would be familiar to engineers and readily accepted. The language is case-
sensitive, has a preprocessor like C, and the major control flow keywords, such as "if"
and "while", are similar. The formatting mechanism in the printing routines and language
operators and their precedence are also similar
The language differs in some fundamental ways. Verilog uses Begin/End instead of curly braces
to define a block of code. The concept of time, so important to a HDL won't be found in C The
language differs from a conventional programming language in that the execution of statements
is not strictly sequential. A Verilog design consists of a hierarchy of modules are defined
with a set of input, output, and bidirectional ports. Internally, a module contains a list of wires
and registers. Concurrent and sequential statements define the behavior of the module by
defining the relationships between the ports, wires, and registers Sequential statements are
placed inside a begin/end block and executed in sequential order within the block. But all
concurrent statements and all begin/end blocks in the design are executed in parallel,
qualifying Verilog as a Dataflow language. A module can also contain one or more instances
of another module to define sub-behavior
A subset of statements in the language is synthesizable. If the modules in a design contains a
netlist that describes the basic components and connections to be implemented in hardware only
synthesizable statements, software can be used to transform or synthesize the design into the net
list may then be transformed into, for example, a form describing the standard cells of an
integrated circuit (e.g. ASIC) or a bit stream for a programmable logic device (e.g. FPGA).
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Design using HDL
The vast majority of modern digital circuit design revolves around an HDL
description of the desired circuit, device, or subsystem.
Most designs begin as a written set of requirements or a high-level architectural diagram.
The process of writing the HDL description is highly dependent on the designer's diagram.
The process of writing the HDL description is highly dependent on the designer's
background and the circuit's nature. The HDL is merely the 'capture language'–often begin
with a high-level algorithmic description such as MATLAB or a C++ mathematical model
Control and decision structures are often prototyped in flowchart applications, or entered in a
state-diagram editor. Designers even use scripting languages (such as PERL) to automatically
generate repetitive circuit structures in the HDL language. Advanced text editors (such as
PERL) to automatically generate repetitive circuit structures in the HDL language. Advanced
text editors (such as Emacs) offer editor templates for automatic indentation, syntax-
dependent coloration, and macro-based expansion of entity/architecture/signal declaration.
As the design's implementation is fleshed out, the HDL code invariably must undergo code
review, or auditing. In preparation for synthesis, the HDL description is subject to an array
of automated checkers. The checkers enforce standardized code guidelines, identifying
ambiguous code construct before they can cause misinterpretation by downstream synthesis, and
check for common logical coding errors, such as dangling ports or shorted outputs.
In industry parlance, HDL design generally ends at the synthesis stage. Once the synthesis
tool has mapped the HDL description into a gate net list, this net list is passed off to the back -
end stage. Depending on the physical technology (FPGA, ASIC gate-array, ASIC standard-
cell), HDLs may or may not play a significant role in the back-end flow. In general, as the
design flow progresses toward a physically realizable form, the design database becomes
progressively more laden with technology-specific information, which cannot be becomes
progressively more laden with technology-specific information, which cannot be stored in a
generic HDL-description. Finally, a silicon chip is manufactured.
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HDL Programming using Xilinx ISE design suite
Xilinx ISE means Xilinx® Integrated Software Environment (ISE), i.e programmable logic
design tool in electronics industry. This Xilinx ® design software suite allows taking
design from design entry through Xilinx device programming. The ISE Project Navigator
manages and processes design through several steps in the ISE design flow. These steps are
Design Entry, Synthesis, Implementation, Simulation/Verification, and Device
Configuration. Xilinx is one of most popular software tool used to synthesize
VHDL/Verilog code.
INTRODUCTION TO FPGA (FIELD PROGRAMMABLE GATE ARRAY)
FPGA contains a two dimensional arrays of logic blocks and interconnections between
logic blocks. Both the logic blocks and interconnects are programmable. Logic blocks
are programmed to implement a desired function and the interconnects are programmed
using the switch boxes to connect the logic blocks.
To implement a complex design (CPU for instance), the design is divided into small sub
functions and each sub function is implemented using one logic block. All the sub
functions implemented in logic blocks must be connected and this is done by
programming the interconnects.
INTERNAL STRUCTURE OF AN FPGA
FPGAs, alternative to the custom ICs, can be used to implement an entire System On one
Chip (SOC). The main advantage of FPGA is ability to reprogram. User can reprogram
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an FPGA to implement a design and this is done after the FPGA is manufactured. This
brings the name “Field Programmable.”
Custom ICs are expensive and takes long time to design so they are useful when
produced in bulk amounts. But FPGAs are easy to implement within a short time with
the help of Computer Aided Designing (CAD) tools.
XILINX FPGA
Xilinx logic block consists of one Look Up Table (LUT) and one Flip-flop. An LUT is
used to implement number of different functionality. The input lines to the logic block go
into the LUT and enable it. The output of the LUT gives the result of the logic function
that it implements and the output of logic block is registered or
unregistered output from the LUT.
4-INPUT LUT BASED IMPLEMENTATION OF LOGIC BLOCK.
Xilinx LUT
Part –A Software Experiments
Procedure : 1. Double click on Xilinx Design Suite 13.1 Icon.
2. Select new project in file menu.
3. Enter the project name and location as shown below and press Next .
4. Select the Family, Device, Package and speed as per the requirements and press Next .
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5. Create a new source by using new source icon or right click on the device/project folder
to create new source.
6. Select the appropriate source type and enter the file name in New Source Wizard
window and press Next .
7. Enter the architecture name – dataflow/behavioral/structural, port name and select the
direction. This will create .v source file. Press Next and finish the initial project creation.
8. Write complete VHDL/Verilog code implementation and save.
9. Click on implementation and check for syntax using “Check syntax” option under
synthesize tab. If any error, edit and correct VHDL/Verilog code and repeat check syntax
until zero errors.
10. Double click on ISIM simulator by selecting simulation mode to complete the
functional simulation of your design.
Part –B Hardware Interfacing
Procedure :
1. Repeat the steps 1 to 10 from the procedure for software experiments .
2. Make the connection between appropriate FRC’s of the FPGA board and the DIP switch
connector of the GPIOcard-2/
3. Make the connection between appropriate FRC’s of the FPGA board and the LED
connector of the GPIOcard-2.
4. Right click on the device and select “New Source”, Select the option “Implementation
constraint File” and provide the file name and click on next and then hit Finish. This
creates an .ucf file.
6. Double click on the added .ucf file and assign the pin numbers to inputs and outputs
referring to FRC sheet using the syntax as shown.Save the constraint file.
7. Connect USB programmer for FPGA between FPGA kit and USB port of your
computer.
8. Go to process window, select the VHDL or Verilog file and click on “configure target
device”.
9. Click OK for the warning below.
10. Select boundary scan to impact the target device.
11. Right click on the impact window to establish a connection between system and FPGA
by selecting “INTIALIZE CHAIN” option.
12. Both prom device and FPGA device gets identified after step 10 and bypass the
procedure to select only FPGA which of main interest.
13. Now choose device 2(FPGA XC3S400) and hit ok to complete the impact.
14. Now right click on the device to assign a new .bit file by selecting an option “ASSIGN
NEW CONFIGURATION FILE”.
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15. Select the corresponding .bit file from the project folder and hit Open .
16. Press ‘No’ on the following dialog box.
17. Finally right click on the device(XC3S400) and implement the program by choosing an
option “PROGRAM”
18. Once again select the FPGA device (XC3S400) by clicking ok and now the program
will be identified and succeeded.
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Experiment No 1
Realize all the logic gates Using Verilog code
Objective: - To write and simulate the Verilog code to realize the basic logic gates and to check
the functionality by simulating the design .
Theory :-
Logic gates are the basic building blocks of any digital system. It is an
electronic circuit having one or more than one input and only one output. The relationship
between the input and the output is based on a certain logic. Based on this, logic gates are
named as AND gate, OR gate, NOT gate
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Verilog Code:
1.a) Realizing AND gate: module and_gate (a,b,y);
input a,b ; //defines two input port
output y; // defines one output port
and g1(y,a,b); /*gate declaration with predefined keyword or representing
logic OR, g1 is optional user defined gate identifier */
endmodule
Functional table:
Input
A
Input
B
Output
Y
0 0 0
0 1 0
1 0 0
1 1 1
Simulation Results:-
1.b) Realizing OR gate:
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Verilog Code :
//Verilog module for OR gate
module or_gate(a,b,y);
input a,b; //defines two input port
output y; // defines one output port
or g1(y,a,b); /*gate declaration with predefined keyword or representing
logic OR, g1 is optional user defined gate identifier */