m P Based Systems

P Based Systems

Read Chapter 3

(David E. Simon, An Embedded Software Primer)

(04/20/23)Embedded Systems Development Introduction Saâd Biaz 2

P Based Systems

PMemorySystem

I/O

Address Bus

Data Bus

Digital inputs (parallel input)

P based system

LED

Switch

TemperatureSensor

Digital outputs (parallel port)

Serial portAnalog input/output

Storage


Memory and I/O mapping

• Consider an 8-bit P (imaginary) with a 6-bit address bus. First instruction to execute (after power on) is at address 48.

• We have:– 16B ROM components (16 x 1B)– 16B RAM components (16 x 1B)

• We plan to ¼ of the memory with ROM, ½ of the memory in RAM, and ¼ I/O


Memory and I/O mapping (2)• Let us map our address space

– What is the address range for the ROM space?– What is the address range for the RAM space?– What is the address range for the I/O space

000000 = 0001111 = 15010000 = 16011111 = 31010000 = 32011111 = 47110000 = 48111111 = 63

I/O

RAM 1

RAM 2

ROM

A5A4A3A2A1A0

26=64


Memory and I/O mapping (3)

• 1) What is the size of the address space?

• 2) What is the size of the address bus for the ROM and RAM components?

P

Address Bus

Data Bus

6

8

16BRAM

D0D7

A3

A0

16BROM

D0D7

A3

A0


Memory Wiring

RAMA3

A0 D7-D0

R/WCS

Address Bus

8

A3

A0

A4

A5

P

Data BusD7-D0

R/WRAM

A3

A0 D7-D0

R/WCS

ROMA3

A0 D7-D0

R/WCS

A5

A4

= 01 A5

A4

= 10 A5

A4

= 11


Input (switch) Wiring

RAMA3

A0 D7-D0

R/WCS

Address Bus

8

A3

A0

A4

A5

P

Data BusD7-D0

R/WRAM

A3

A0 D7-D0

R/WCS

ROMA3

A0 D7-D0

R/WCS

VCC

How to interface a switch?First, choose the address where to map the switchSecond, build a circuit that connects the swich to data busonly when associated address is given by P.


Input (switch) Wiring

RAMA3

A0 D7-D0

R/WCS

Address Bus

8

A3

A0

A4

A5

P

Data BusD7-D0

R/WRAM

A3

A0 D7-D0

R/WCS

ROMA3

A0 D7-D0

R/WCS

VCC

Let us choose the address 0 (bit D0) to map the switchA5A4A3A2A1A0

D0


Output (LED) Wiring

RAMA3

A0 D7-D0

R/WCS

Address Bus

8

A3

A0

A4

A5

P

Data BusD7-D0

R/WRAM

A3

A0 D7-D0

R/WCS

ROMA3

A0 D7-D0

R/WCS

Exercise I : Interface a LED at address 1, data bus line D4

A5A4A3A2A1A0

D4


I/O: Device Controllers

• The P communicates with the device controller through registers accessible as if they are memory cells.

• Example: a device controller with 2m registers

ChipAm-1

A0 D7-D0

R/WCS

I/OFunction


Example of Device Controllers:Parallel I/O Port

• Ports A, B, and C can be configured to be inputs or outputs.• Configuration is made by writing in the 8-bit control register• After configuration, ports A,B, or C can be read or written to as

if they were memory cells.

Intel 8255

A1

A0 D7-D0

RDCSA

B

C

8

8

8

8-bit Control Reg.

WD


Example of Device Controllers:UART or Serial I/O Port

• The 8-bit configuration register is used to select the speed (110bps to 19200bps), parity check, number of bits per word, lentgh of stop bits.

• The P writes to the data register the data to be sent serially on TX

• The P reads from the data register data received serially on RX.

Intel 8251

A0 D7-D0

RDCS

8-bit Data Reg.

WD

8-bit Config. Reg.

TX

RX


Example of Device Controllers:Timer

• The P initializes a counter Ci with some value.• All counters are decremented at each tick of the clock input• When the counter Ci reaches 0, an impulse is output on the

corresponding output Oi.

Intel 8253

A0 D7-D0

RDCS 16-bit Counter 0WD

8-bit Config. Reg.

O0

A1

O1

O2

16-bit Counter 1

16-bit Counter 2

CLK


Direct Memory Access (DMA)

• The idea is to transfer directly I/O stream to/from memory without using the CPU (long bus cycles)

• Reminder, to transfer a word from I/O to memory. The P must:• Fetch its “reading” instruction (IN AX,DX)• Decode the instruction, execute it• Fetch the “write” instruction• Decode the instruction, execute it• Test if done (involves loops/jumps..etc)


Direct Memory Access (DMA) (2)

• Transfering CONTIGUOUS data can be made more efficiently:• A counter is needed to generate increasing

addresses and proper control signals to the memory.


Address/Control Bus

P

Data Bus

Direct Memory Access (DMA)

RAM

I/ODMA

Controller

BusReqBusAck

DMAReq

DMAAck


Gluing a P-based system

• Decoding functions may require some components (especially if address bus very large 32 to 64 bits).

• PALs

• FGPAs


Built-Ins on Microcontrollers

• Address decoding

• Timers

• I/O

• DMA

• ADC-DAC (Analog-Digital Converter … )

P Based Systems(Example: Microcontroller Rabbit 2000)

Read Chapter 1 and 2

(Rabbit Semiconductor, Rabbit 2000 Microprocessor User’s Manual)

http://www.rabbitsemiconductor.com/docs/


Rabbit 2000 Characteristics

• 8-bit data bus

• 20-bit address bus (extensible)

• Software driven system clock

• 2 timers

• 40 bit parallel configurable I/O

• 4 serial ports

• 1 watchdog timer


Rab

bit 2

000

Cha

ract

eris

tics

(2)


Rabbit 2000 System Clock


Saving Power (By Software)

• Add memory wait states

• Turn off clock doubler (if in use)

• Divide frequency by 8 (select f/8)

• Run code in RAM, not in flash

• Use for the CPU and peripheral clock the 32K oscillator (disable main oscillator)


Timers

• RTC: 48-bit register driven by 32K

• Watchdog timer (0.25s, 0.5s, 1s, or 2s)


Timers (2)


Serial Communication

m P Based Systems

Documents

address range

address bus

address spacewhat

embedded software primer

data register data

memory cells

memory wiringa5a4

device controllersthe