M. Meyyappan NASA Ames Research Center Moffett Field, CA 94035 [email protected] Phase-Change Nonvolatile Memory: Current Status and Possible Advances.

M. MeyyappanNASA Ames Research Center

Moffett Field, CA [email protected]

Phase-Change Nonvolatile Memory:

Current Status and Possible Advances

using Nanowires

Acknowledgement: Bin Yu, Xuhui Sun

• Combine the best of these:

- High speed of the Static Random Access Memory (SRAM)

- Nonvolatile nature of flash memory

- Density of DRAM

• Low Cost

• Scalability

Some Candidates

• Magnetic RAM

• Ferroelectric RAM

• Ovonic Unified Memory (after Ovshinsky who proposed it in 1968) or

Phase-change Random Access Memory (PRAM)

Requirements for an Ideal Memory

Phase Change Materials

• Phase change materials date back to 1960s- Mainstream optical storage media (CD-RW, DVD-RW)

• Common phase-change material candidates- GeTe, GeSbTe, In2Se3, InSb, SbTe, GaSb, InSbTe, GaSeTe, …

- Thermally induced phase change (orderly single crystalline or polycrystalline C-phase vs. less orderly amorphous -phase)

• Electrically operated phase-change Random Access Memory (PRAM)

- Proposed nearly 3 decades ago- Binary or multiple resistive states of

the programmable element to represent logic levels

• PRAM advantages Simpler fabrication than FET-based NVMs Improved endurance (resistor-based) Faster read/write Binary or multiple resistive states Soft-error or radiation free operation

Phase-Change Random Access Memory (PRAM)

• PRAM Issues- Large programming current to generate the

thermal energy needed for inducing the phase change

- Joule heating induced power dissipation issues- Intercell thermal interference- Scaling difficulties due to the above

• In the beginning, reluctance to introduce an unknown complex alloy into main stream silicon processing

• At the same time, silicon flash memory started to advance rapidly

All of this together put the brakes somewhat, slowing down developments

If that good, Why is it not on the market?

Why Renewed Interest in PRAM Now?

• Difficulties scaling Flash Memory, leading to extensive search for alternatives

• Phase change material is no longer mysterious, much more known about these alloys in the last two decades

• Steady developments in addressing key issues

- programming current reduction- endurance- intercell interferance- new architectures

• Major players involved- Intel, IBM, Samsung, Infineon,

Philips…

PRAM Technology Advancement

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IBM Infineon Macronix PCRAM Joint Project (2006 VLSI Symp)

• Pillar phase change memory, 180 nm CMOS

• N-doped GST pillar on top of W contact

• Current-confining pillar leads to self heating

• Reset current 900 µA (at 75 nm diameter)

• Endurance test 106 cycles

PRAM Technology Advancement

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• 90 nm PRAM, cell area 12 F2

• Vertical PNP BJT Selector device - base of BJT is the word line

- emitter connected to the bottom of PRAM cell

• Programming current ~ 400 µA

• Endurance 108 reset/set cycles

ST Microelectronics, VLSI Tech. Digest (2006)

PRAM Technology Advancement

Lee et al Microelec. Eng.Vol. 84, 573-576 (2007)

• Cross bar array of PRAM devices

• Efforts to confine switching volume into nanometer scale

• Fabrication at 60 nm scale with UV nanoimprint lithography

PRAM TechnologyInsight from 3-D Modeling

Kim et al J. Appl. Phys. 101, 064512 (2007)(RWTH Aachen University)

• Current density and temperature at the GST/electrode interface are lower than in the center of the GST layer; due to larger heat dissipation on the TiN electrode.

• In the center, 616°C is reached in 3 ns.

• Temporal evolution of temperature and phase help to understand dynamics.

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PRAM Technology Advancement

Wright et al, IEEE Trans. Nanotech. Vol. 5, p 50 (2006)U. of Exeter

• Tip based memory, no separate selecting device

• Sharp scanning tip reduces the volume between the head that does R/W and the PRAM layer

• Slow scanning speed is to be compensated by parallel array of tips, just as in Millipede

• Modeling shows bits that are 15-30 nm dia and tips ~ 20 nm dia are possible and can give 1 Tbit/inch2

Restraints to aggressive scaling Critical material dimension depends on “top-down” process

Lithography resolution, etching-induced surface damage, line-edge roughness, difficulty to achieve high aspect ratio geometry, and more.

Fabrication cost increases dramatically as critical size scale down

Y. Chen et al , IEDM, 2006 (IBM)M. Lankhorst et al., Nat. Mater., Vol. 4, 2005, P347-352 (Philips)

PRAM with Etched-down wires

• narrow line of GeSb

• Reset 90 µA for 60 nm2

Limits of Phase Change Properties

• Does phase change property exist when you reach extremely small particle size?

• Test cell: Aluminum top electrode 20 µmGST layer 100 nmp-doped silicon waferIn situ laser ablation to generate< 10 nm GST particles

• Phase change properties exist down to 10 nm particle size

• Projected reset current 1 µA

Nanoscale Benefits Smaller cell volume, leads to direct reduction of energy needs Reduced melting point (30-50%) Reduced thermal conductivity (1-2 orders of mag.) Large aspect ratio (self-heating resistor) Perfect surface morphology (not etched)

Growth Benefits Highly scalable critical size – diameter depends on catalyst size

(down to ~ a few nm) Etching-free One-step LPCVD or MOCVD

Why 1-D Phase-Change Nanowire?

2-D Thin film PRAM

1-D Nanowire PRAM

Top electrode PCM Layer Active Bottom electrode Dielectric material

Projected Nanowire-based Memory Features

Ultra-low reset current (< 10µA/cell)

Possible very low-cost manufacturing

Pitch depends on innovative cell design

Break lithography limit with high-density template-guided large-scale self-assembly

Vertical nanowire (NASA-Ames)

Schematic diagram of thermal evaporation CVD

Carrier gas flow

Vapor-Liquid-Solid (VLS) Mechanism

Nanowire Chemical Synthesis

Binary Ternary Quaternary

Ge Te Ge Sb Te Ag In Sb TeIn Sb In Sb Te (Ge Sn)Sb TeIn Se Ga Se Te Ge Sb (Se Te)Sb Te Sn Sb Te Te Ge Sb SGa Sb In Sb Ge …… …

Family of Phase-Change Materials

(Red: nanowires synthesized at NASA-Ames)

Critical Parameters

Melting Point Phase-change energy

threshold Reliability/stability Multi-level storage

Electrical Resistance Self-heating efficiency Programming energy

Thermal Conductivity &

Specific Heat Self-heating efficiency Programming energy

Binary /Ternary Phase-Change Nanowires

X. Sun, B. Yu, M. Meyyappan, abstract submitted to MRS Spring Meeting, 2008

(a) TEM image of an individual GeTe nanowire with a diameter of ~ 40 nm. The inset shows an SAED pattern of fcc cubic lattice structure. (b) EDS spectrum of the same GeTe nanowire.

X. Sun et al., JPCC, 111, 2421 (2007)

40 nm

<110>

Ge:Te≈1:1

GeTe Nanowires: TEM, SAED, and EDS

TEM image and corresponding EDS spectra of an individual In2Se3 nanowire. Scare bar is 100 nm.

X. Sun et al., APL, 89, 233121 (2006)

In:Se2:3

In2Se3 Nanowires: TEM and EDS Spectra

d ~ 40nm

GeSb Nanowires: TEM, SAED and EDS

40 nm

100 nm

Ge:Te≈1:1Ge:Sb ≈ 7:93 ~ 9:91

Diameter range: 40-100nm

In-situ Tm measurement of GeTe nanowire under TEM image monitoring (a) The GeTe nanowire is under room temperature. (b) The GeTe nanowire is heated up to 400C when the nanowire melts and its mass is gradually lost through evaporation. The remaining oxide shell can be seen from the image.

Liquid GeTe

X. Sun et al., J. Phys. Chem. C, Vol. 111 (2007)

GeTe Nanowires: Melting Experiment

and In-Situ Monitoring by TEM

Tm of bulk PCM

Tm of PCM nanowires

•The melting temperature of the phase-change nanowire is identified as the point at which (1) the electron diffraction pattern disappears and (2) the nanowire starts to evaporate.

•This property is diameter-dependent: reduction even more

significant for smaller diameters

PCM Nanowires: Melting Point

GeTe

(d=70nm)

In2Se3

(d=40nm)

Bulk Tm 725°C 890°C

Nanowire Tm 390°C 680°C

Reduction 46% 24%

Melting Point Reduction

=

Tb

L

1

r(1

1

AR)

∆ = Deviation of melting point from the

bulk valueTo = Bulk melting point = Surface tension coefficient for a

liquid-solid interface = Material densityr = Nanowire radiusAR = Nanowire aspect ratioL = Latent heat of fusion

Thermally induced nano-encoding on an individual 1-D GST nanowire with scanning focused electron beam. A series of α-GST nanodots were created by highly localized thermal heating with an e-beam spot. The amorphous-to-crystalline boundary is marked by red dash line.

X. Sun et al., APL, 90, 183116 (2007)

After 5-sec e-beam localized thermal writingfrom crystal to amorphous

Electron-Beam Based GST Nanowire

Thermal Programming

d ~ 55nm

Before After

Nanowire Phase-Change Memory Prototype

Fabrication/Measurement

Mo Pad

Pt

PC-NW

PC-NW

Pt

Pt

RESET

SET

In2Se3 nanowire phase change memory switching behavior as a function of reset/set pulse voltage

Pulse width: (a) Reset at 20 nsec. (b) Set at 100 μsec.

Could be further reduced via memory size scaling

In2Se3 Nanowire MemorySwitching Behavior

B. Yu et al., Appl. Phys. Lett. 91, 133119 (2007)

In2Se3 Nanowire Memory

(a)

0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1

10-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

High resistance state

Low resistance state

Dev

ice

Cu

rren

t (A

)

Applied Voltage (V)

(b)

0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1105

106

107

108

109

1010

1011

1012

1013

Low resistance state

High resistance state

Dev

ice

Res

ista

nce

()

Applied Voltage (V)

I-V R-V

• Device characteristics in either state with successive measurement

sweeps show stable resistive behavior

• Dynamic switching ratio (on/off resistance) is ~105

Repeated resistance measurement of In2Se3 phase-change nanowire memory device. Device was switched between high- and low-resistive states using voltage pulses: LRS - HRS using 7V / 20 ns reset pulse; HRS - LRS using 5V / 100 S set pulse.

In2Se3 Nanowire MemoryRepeated Reset-set Cycles

reset reset reset

set set

Reading

GeTe nanowire phase change memory switching behavior as a function of reset/set voltage

Pulse width: (a) Reset at 20 nsec. (b) Set at 20 μsec.

GeTe Nanowire Phase-Change Memory

@2.5V

@1.1V

Storage Media In2Se3 nanowire In2Se3

Thin Film

Resistive Switching Ratio

105 103

Reset

Current

11 A 0.4 mA

Reset Power/Energy 80 W / 1.6 pJ 16 mW / 1.12 nJ

Set Power/Energy 0.25 nW / 25 fJ 14 W / 140 pJ

Reference Our Work IEEE Trans. Mag. 41, 1034 (2005)

PRAM Performance Comparison: Nanowire vs.

Thin Film

Why In2Se3 is Attractive?

• High resistance material, leading to inherently lower current

• Highly amenable for multilevel operation

• No need for doping and other strategies used with GST to increase resistance

• No phase segregation problems as are likely with ternary alloys

Material/ form

Reference RSR Reset power, energy and pulse width

Set power, energy and pulse width

Reset current

GeTe nanowire

This work 2200 125 W 2.5 pJ (20ns)

11 nW 220 fJ (20 s)

50 A

In2Se3 nanowire

This work 2X105 80 W 1.6 pJ (20ns)

0.25 nW 25 fJ (100 s)

11.7 A

In2Se3 thin film

IEEE Tran. Mag (2005)

300 20 mW 1.4 nJ (70ns)

12 W 120 pJ (10 s)

7.0 mA

Doped-SbTe thin film

Nat. Mater (2005)

200 300 W 15 pJ (50ns)

1 W 100 fJ (100ns)

0.25 mA

GST thin film

IEDM (2003)

50 200 W 3 pJ (15 ns)

1 W 1.25 pJ (1.25 s)

70 A

GST thin film

VLSI (2004)

6 mW - 3.6 mW - -

GST nanowire

U. Penn. 200 1.3 mW - 0.4 mW - 0.4 mA

Nanowire PRAM Performance

Challenges ahead for Nanowire Approach

• Controlled growth direction, diameter

• Overall process flow development; such things have never been done before

• Scalability modeling to demonstrate minimum pitch without interference

If successful, Advantages would be• Scalability at reduced cost (down to 5 nm)

• Thin film PRAM pitch is way larger than litho limit. NW-PRAM can be pushed to state-of-the-art litho limit (if catalyst is patterned) or lower (if catalyst self-assembled)

• Thin film PRAM footprint is large with large selecting device to deliver the needed current. NW-PRAM will also reduce the selecting device size and overall footprint.

Technology Goal Technology Goal

Develop low-power high-density data storage using nanomaterial array, enabling 102~103X faster R/W, 10~15X lower write voltage, and 10~100X higher integration density

Technology ChallengesTechnology Challenges

Super-scalable R-switching nanowire memory Large-scale self-assembly / patterned assembly 3-D integration / selecting device

• Target 0.5~1 V R/W operation

• 1 µA/cell reset current

• Target 0.5~1 V R/W operation

• 1 µA/cell reset current

• 1 TB/cm2 density

• <10-12 J/bit switch energy

• 1 TB/cm2 density

• <10-12 J/bit switch energy

Anticipated Performance MetricsAnticipated Performance MetricsResistive Switching in PC NanowireResistive Switching in PC Nanowire

Next-generation highly scalable, ultra-low power, resistive switching non-volatile memory chip technology based on phase-change nanomaterials Next-generation highly scalable, ultra-low power, resistive switching non-volatile memory chip technology based on phase-change nanomaterials

Technical ApproachTechnical Approach

3-D vertical nanowire array Non-charge-based (radiation-

free) Significantly reduced thermal

writing energy (102~103X) Super scalable memory cell Reduced thermal interference Multi-layer stacking for high

integration density Binary or analog data storage Low temperature assembly

compatible with Si-IC platform • Less than 10 ns write time

• 1010 cycle endurance

• Less than 10 ns write time

• 1010 cycle endurance

Programming(set)

electrode Nanowire after programming

Erasing(reset)

High-resistancestate

Low-resistancestate

Nanowire before programming

Ultimate Phase-Change Memory ?