LTC6258/LTC6259/LTC6260 - 1.3MHz, 20µA Power …...1.3MHz, 20µA Power Efficient Rail-to-Rail I/O Op Amps The LTC®6258/LTC6259/LTC6260 are single/dual/quad operational amplifiers

LTC6258/LTC6259/LTC6260

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1For more information www.linear.com/LTC6258

APPLICATIONSn Micropower Active Filtersn Portable Instrumentationn Battery or Solar Powered Systemsn Automotive Electronics

n Gain Bandwidth Product: 1.3MHzn Low Quiescent Current: 20µAn C-Load™ Op Amp Drives all Capacitive Loadsn Offset Voltage: 400µV Maximumn Rail-to-Rail Input and Outputn Supply Voltage Range: 1.8V to 5.25Vn EMI Rejection Ratio: 45dB at 1GHzn Input Bias Current: 75nA Maximumn CMRR/PSRR: 95dB/90dBn Shutdown Current: 7µA Maximumn Operating Temperature Range: –40°C to 125°Cn Single in 6-Lead TSOT-23, 2mm × 2mm DFN

Packagesn Dual in 8-Lead MS8, MS10, TS0T-23, 2mm × 2mm

DFN Packagesn Quad in MS16 Package

TYPICAL APPLICATION

DESCRIPTION

1.3MHz, 20µA Power Efficient Rail-to-Rail I/O

Op Amps

The LTC®6258/LTC6259/LTC6260 are single/dual/quad operational amplifiers with low noise, low power, low supply voltage, and rail-to-rail inputs and outputs. They are unity gain stable with or without capacitive loads. They feature 1.3MHz gain-bandwidth product, 0.24V/µs slew rate while consuming only 20µA of supply current per amplifier operating on supply voltages ranging from 1.8V to 5.25V. The combination of low supply current, low supply volt-age, high gain bandwidth product and low noise makes the LTC6258 family unique among rail-to-rail input/output op amps with similar supply current. These operational amplifiers are ideal for power efficient applications.

For applications that require power-down, the LTC6258 in 2mm × 2mm DFN and LTC6259 MS10 packages respectively offer shutdown which reduces the current consumption to 7µA maximum.

The LTC6258 family can be used as plug-in replacements for many commercially available op amps to reduce power and improve input/output range and performance.L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and Over-The-Top and C-Load are trademarks of Analog Devices, Inc. All other trademarks are the property of their respective owners.

Low Noise Reference

FEATURES

Reference Buffer Noise Density

–+

5V

V+OUT

LTC6258

6258960 TA01

22µF22µF

RIN12.7k

22µFIN OUT

GND

LT6656

* 2.7K + 22µF FILTER

OP AMP, 44µF CLOADOP AMPFILTERED REFERENCEREFERENCE OUTPUTINSTRUMENT ONLY

FREQUENCY (kHz)0.01 0.1 1 10 1000

500

1000

1500

2000

2500

3000

3500

4000

4500

5000

NOIS

E DE

NSIT

Y (n

V/√H

z)

6258960 TA01a

http://www.linear.com/LTC6258


LTC6258/LTC6259/LTC6260

26258960fa

For more information www.linear.com/LTC6258

ABSOLUTE MAXIMUM RATINGS

Supply Voltage: V+ – V– ...........................................5.5VInput Voltage ................................... V– – 0.2 to V+ + 0.2Input Current: +IN, –IN, SHDN (Note 2) ............... ±10mAOutput Current: OUT ........................................... ±20mAOutput Short-Circuit Duration (Note 3) ............ IndefiniteOperating Temperature Range (Note 4) ..... –40°C to 125°C

(Note 1)

DC PACKAGE6-LEAD (2mm × 2mm × 0.8mm) PLASTIC DFN

TOP VIEW

OUT

–IN

SHDN

V+

+IN

V– 4

57V–

6

3

2

1

TJMAX = 150°C, qJA = 80°C/W (NOTE 6) EXPOSED PAD (PIN 7) IS V–, MUST BE SOLDERED TO PCB

TOP VIEW

OUTA

–INA

+INA

V–

V+

OUTB

–INB

+INB

DC PACKAGE8-LEAD (2mm × 2mm × 0.8mm) PLASTIC DFN

9V–

4

1

2

3 6

5

7

8

TJMAX = 150°C, qJA = 80°C/W (NOTE 6)

EXPOSED PAD (PIN 9) IS V–, MUST BE SOLDERED TO PCB

1234

8765

TOP VIEW

TS8 PACKAGE8-LEAD PLASTIC TSOT-23

V+

OUTB–INB+INB

OUTA–INA+INA

V– +–

+–


1234

OUTA–INA+INA

V–

8765

V+

OUTB–INB+INB

TOP VIEW

MS8 PACKAGE8-LEAD PLASTIC MSOP

+–+

–


12345

OUTA–INA+INA

V–

SHDNA

109876

V+

OUTB–INB+INBSHDNB

TOP VIEW

MS PACKAGE10-LEAD PLASTIC MSOP

+–+

–


12345678

OUTA–INA+INA

V+

+INB–INB

OUTBNC

161514131211109

OUTD–IND+INDV–

+INC–INCOUTCNC

TOP VIEW

MS PACKAGE16-LEAD PLASTIC MSOP

+–

+–

+–

+–


1

2

3

6

5

4

TOP VIEW

S6 PACKAGE6-LEAD PLASTIC TSOT-23

V+

SHDN

–IN

OUT

V–

+IN

+ –


PIN CONFIGURATION

Specified Temperature Range (Note 5) LTC6258I/LTC6259I/LTC6260I ............–40°C to 85°C LTC6258H/LTC6259H/LTC6260H ...... –40°C to 125°C

Maximum Junction Temperature .......................... 150°CStorage Temperature Range .................. –65°C to 150°CLead Temperature (Soldering, 10 sec)TS8, MS8, MS only ............................................... 300°C


LTC6258/LTC6259/LTC6260

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ORDER INFORMATION

5V ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VSUPPLY = 5V, VCM = VOUT = VSUPPLY/2, CL = 10pF, VSHDN is unconnected.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VOS Input Offset Voltage VCM = V– + 0.3V

l

–400 –1000

100 400 1000

µV µV

VCM = V+ – 0.3V

l

–400 –1000

100 400 1000

µV µV

∆VOS/∆T Input Offset Voltage Drift VCM = V– + 0.3V, V+ – 0.3V 1.5 µV/°C

IB Input Bias Current (Note 7) VCM = V– + 0.3V l –75 –5 75 nA

VCM = V+ – 0.3V l –75 0 75 nA

IOS Input Offset Current VCM = V– + 0.3V l –75 –1 75 nA

VCM = V+ – 0.3V l –75 –1 75 nA

en Input Voltage Noise Density f = 1kHz 38 nV/√Hz

Input Noise Voltage f = 0.1Hz to 10Hz 2 µVP-P

in Input Current Noise Density f = 1kHz, VCM = 0V to 4V f = 1kHz, VCM = 4V to 5V

500 500

fA/√Hz fA/√Hz

RIN Input Resistance Differential Common Mode

1 10

MΩ MΩ

TAPE AND REEL (MINI) TAPE AND REEL PART MARKING* PACKAGE DESCRIPTIONSPECIFIED TEMPERATURE RANGE

LTC6258IS6#TRMPBF LTC6258IS6#TRPBF LTGWD 6-Lead Plastic TSOT-23 –40°C to 85°C

LTC6258HS6#TRMPBF LTC6258HS6#TRPBF LTGWD 6-Lead Plastic TSOT-23 –40°C to 125°C

LTC6258IDC#TRMPBF LTC6258IDC#TRPBF LGZS 6-Lead Plastic DFN (2mm × 2mm × 0.8mm) –40°C to 85°C

LTC6258HDC#TRMPBF LTC6258HDC#TRPBF LGZS 6-Lead Plastic DFN (2mm × 2mm × 0.8mm) –40°C to 125°C

LTC6259ITS8#TRMPBF LTC6259ITS8#TRPBF LTGWX 8-Lead Plastic TSOT-23 –40°C to 85°C

LTC6259HTS8#TRMPBF LTC6259HTS8#TRPBF LTGWX 8-Lead Plastic TSOT-23 –40°C to 125°C

LTC6259IDC#TRMPBF LTC6259IDC#TRPBF LGWT 8-Lead (2mm × 2mm × 0.8mm) Plastic DFN –40°C to 85°C

LTC6259HDC#TRMPBF LTC6259HDC#TRPBF LGWT 8-Lead (2mm × 2mm × 0.8mm) Plastic DFN –40°C to 125°C

TUBE

LTC6259IMS8#PBF LTC6259IMS8#TRPBF LTGWW 8-Lead Plastic MSOP –40°C to 85°C

LTC6259HMS8#PBF LTC6259HMS8#TRPBF LTGWW 8-Lead Plastic MSOP –40°C to 125°C

LTC6259IMS#PBF LTC6259IMS8#TRPBF LTGWY 10-Lead Plastic MSOP –40°C to 85°C

LTC6259HMS#PBF LTC6259HMS8#TRPBF LTGWY 10-Lead Plastic MSOP –40°C to 125°C

LTC6260IMS#PBF LTC6260IMS#TRPBF 6260 16-Lead Plastic MSOP –40°C to 85°C

LTC6260HMS#PBF LTC6260HMS#TRPBF 6260 16-Lead Plastic MSOP –40°C to 125°CConsult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Parts ending with PBF are RoHS and WEEE Compliant.For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/.

http://www.linear.com/product/LTC6258#orderinfo


http://www.linear.com/leadfree/

http://www.linear.com/tapeandreel/

http://www.linear.com/product/LTC6258#orderinfo

LTC6258/LTC6259/LTC6260

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5V ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VSUPPLY = 5V, VCM = VOUT = VSUPPLY/2, CL = 10pF, VSHDN is unconnected.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITSCIN Input Capacitance Differential

Common Mode0.65 1.2

pF pF

CMRR Common Mode Rejection Ratio VCM = 0.3V to 3.5V VCM = –0.1V to 5.1V

l

l

66 64

95 95

dB dB

IVR Input Voltage Range l –0.1 5.1 VPSRR Power Supply Rejection Ratio VCM = 0.4V, VS = 1.8V to 5.25V

l

78 68

90 dB dB

Supply Voltage Range l 1.8 5.25 VAV Large Signal Gain VOUT = 0.5V to 4.5V, RLOAD = 100k

l

14 2.8

40 V/mV V/mV

VOUT = 0.5V to 4.5V, RLOAD = 10k

l

3.5 0.5

10 V/mV V/mV

VOL Output Swing Low (Input Overdrive 30mV). Measured from V–

No Load

l

12 40 50

mV mV

ISINK = 100µA

l

80 105 120

mV mV

ISINK = 1mA

l

145 180 250

mV mV

VOH Output Swing High (Input Overdrive 30mV). Measured from V+

No Load

l

25 40 65

mV mV

ISOURCE = 100µA

l

35 55 100

mV mV

ISOURCE = 1mA

l

100 140 350

mV mV

ISC Output Short-Circuit Current

l

4 1

10 mA mA

IS Supply Current per Amplifier

l

16 11

20 23 25

µA µA

Supply Current in Shutdown

l

4 5 7

µA µA

ISHDN Shutdown Pin Current VSHDN = 0.6V VSHDN = 1.5V

l

l

60 0

200 15

nA nA

VIL SHDN Input Low Voltage Disable l 0.6 VVIH SHDN Input High Voltage Enable l 1.5 VtON Turn-On Time SHDN Toggle from 0V to 5V 152 µstOFF Turn-Off Time SHDN Toggle from 5V to 0V 7 µsGBW Gain-Bandwidth Product f = 10kHz

l

1.0 0.4

1.3 MHz MHz

tS Settling Time, 0.5V to 4.5V, Unity Gain 0.1% 0.01%

14 18

µs µs

SR Slew Rate AV = –1, VOUT = 0.5V to 4.5V, CLOAD = 10pF, RF = RG = 10kΩ

l

0.2 0.1

0.24 V/µs V/µs

FPBW Full Power Bandwidth (Note 8) 4VP-P 20 kHzTHD+N Total Harmonic Distortion and Noise f = 500Hz, AV = 2, RL = 4kΩ, VOUTP-P = 1V

VIN = 2.25V to 2.75V0.025

72% dB

ILEAK Output Leakage Current in Shutdown VSHDN = 0V, VOUT = 0V VSHDN = 0V, VOUT = 5V

l

l

100 100

nA nA

%MP Large Signal Overshoot VIN = 0.5V to 4.5V, AV = 1, CL = 100nF 2.7 %EMIRR Electromagnetic Interference Rejection Ratio Input Power –10dB to Input Pins at 1GHz 45 dB


LTC6258/LTC6259/LTC6260

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1.8V ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VSUPPLY = 1.8V, VCM = VOUT = 0.4V, CL = 10pF, VSHDN is unconnected.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VOS Input Offset Voltage VCM = V– + 0.3V

l

–400 –1000

100 400 1000

µV µV

VCM = V+ – 0.3V

l

–400 –1000

100 400 1000

µV µV

∆VOS/∆T Input Offset Voltage Drift VCM = V– + 0.3V, V+ – 0.3V 1.5 µV/°C

IB Input Bias Current (Note 7) VCM = V– + 0.3V l –75 2 75 nA

VCM = V+ – 0.3V l –75 5 75 nA

IOS Input Offset Current VCM = V– + 0.3V l –75 2 75 nA

VCM = V+ – 0.3V l –75 2 75 nA

en Input Voltage Noise Density f = 1kHz, VCM = 0.4V 38 nV/√Hz

Input Noise Voltage f = 0.1Hz to 10Hz 2 µVP-P

in Input Current Noise Density f = 1kHz, VCM = 0V to 0.8V f = 1kHz, VCM = 1V to 1.8V

500 500

fA/√Hz fA/√Hz

RIN Input Resistance Differential Common Mode

1 10

MΩ MΩ

CIN Input Capacitance Differential Common Mode

0.65 1.2

pF pF

CMRR Common Mode Rejection Ratio VCM = 0.2V to 1.6V

l

70 61

90 dB dB

IVR Input Voltage Range l –0.1 1.9 V

PSRR Power Supply Rejection Ratio VCM = 0.4V, VS = 1.8V to 5.25V

l

78 68

90 dB dB

AV Large Signal Gain VOUT = 0.5V to 1.3V, RLOAD = 100k

l

15 1.6

50 V/mV V/mV

VOUT = 0.5V to 1.3V, RLOAD = 10k

l

4 0.4

10 V/mV V/mV

VOL Output Swing Low (Input Overdrive 30mV), Measured from V–

No Load

l

15 30 50

mV mV

ISINK = 100µA

l

80 110 130

mV mV

ISINK = 1mA

l

150 200 230

mV mV


LTC6258/LTC6259/LTC6260

66258960fa


Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.Note 2: The inputs are protected by back-to-back diodes as well as ESD protection diodes to each power supply. If the differential input voltage exceeds 1.4V or the input extends more than 500mV beyond the power supply, the input current should be limited to less than 10mA.Note 3: A heat sink may be required to keep the junction temperature below the absolute maximum rating when the output is shorted indefinitely.Note 4: LTC6258I/LTC6259I/LTC6260I and LTC6258H/LTC6259H/LTC6260H are guaranteed functional over the temperature range of –40°C to 125°C.

1.8V ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VSUPPLY = 1.8V, VCM = VOUT = 0.4V, CL = 10pF, VSHDN is unconnected.SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VOH Output Swing High (Input Overdrive 30mV), Measured from V+

No Load

l

25 40 50

mV mV

ISOURCE = 100µA

l

35 60 100

mV mV

ISOURCE = 1mA

l

95 140 300

mV mV

ISC Output Short-Circuit Current

l

4 1

10 mA mA

IS Supply Current per Amplifier

l

17 10

20 21 23

µA µA

Supply Current in Shutdown

l

1.0 1.5 2

µA µA

ISHDN Shutdown Pin Current VSHDN = 0.5V VSHDN = 1.5V

l

l

50 0

80 10

nA nA

VIL SHDN Input Low Voltage Disable l 0.5 V

VIH SHDN Input High Voltage Enable l 1.5 V

tON Turn-On Time SHDN Toggle From 0V to 1.8V 47 µs

tOFF Turn-Off Time SHDN Toggle From 1.8V to 0V 17 µs

GBW Gain-Bandwidth Product f = 10kHz

l

1.0 0.4

1.3 MHz MHz

TS Settling Time, 0.3V to 1.5V, Unity Gain 0.1% 0.01%

7 12

µs µs

SR Slew Rate AV = –1, VOUT = 0.3V to 1.5V, CLOAD = 10pF RF = RG = 10kΩ

l

0.16 0.1

0.22 V/µs V/µs

FPBW Full Power Bandwidth (Note 8) 1.2VP-P 58 kHz

THD+N Total Harmonic Distortion and Noise f = 500Hz, AV = 2, RL = 4kΩ, VOUTP-P = 1V VIN = 0.65V to 0.15V

0.04 68

% dB

Note 5: The LTC6258I/LTC6259I/LTC6260I are guaranteed to meet specified performance from –40°C to 85°C. The LTC6258H/LTC6259H/LTC6260H are guaranteed to meet specified performance from –40°C to 125°C.Note 6: Thermal resistance varies with the amount of PC board metal connected to the package. The specified values are for short traces connected to the leads.Note 7: The input bias current is the average of the currents into the positive and negative input pins.Note 8: Full power bandwidth is calculated from the slew rate FPBW = SR/π • VP-P.


LTC6258/LTC6259/LTC6260

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TYPICAL PERFORMANCE CHARACTERISTICS

Input Offset Drift Distribution VOS vs Supply Voltage (25°C)VOS vs Common Mode Voltage

VOS vs IOUT

Input Bias Current vs Common Mode Voltage

Input Bias Current vs Common Mode Voltage

Input VOS Histogram Input VOS Histogram VOS vs Temperature

VS = ±2.5VVCM = 0V

VOS (µV)–350 –250 –150 –50 50 150 250 3500

10

20

30

40

50

60

70

80

90

100

NUM

BER

OF P

ARTS

6258 G01

VS = ±2.5VVCM = 2.2V

VOS (µV)–350 –250 –150 –50 50 150 250 3500

10

20

30

40

50

60

70

80

90

100

NUM

BER

OF P

ARTS

6258 G02

VS = ±2.5VVCM = 0V

TEMPERATURE (°C)–40 –25 –10 5 20 35 50 65 80 95 110 125

–500

–400

–300

–200

–100

0

100

200

300

400

500

V OS

(µV)

6258 G03

VS = ±2.5VVCM=0V

HGRADEIND

DISTRIBUTION (µV/°C)–5 –4 –3 –2 –1 0 1 2 3 4 5

0

1

2

3

4

5

6

7

8

9

10

11

NUM

BER

OF U

NITS

6258 G04

VCM = 0.4V

SUPPLY VOLTAGE (V)1.8 2.4 3.0 3.6 4.2 4.8 5.4

–200

–160

–120

–80

–40

0

40

80

120

160

200

V OS

(µV)

6258 G05

VS = 5V

VCM (V)–0.5 0.5 1.5 2.5 3.5 4.5 5.5

–500

–400

–300

–200

–100

0

100

200

300

400

500

V OS

(µV)

6258 G06

VS = ±2.5VVCM = 0V –40°C

25°C125°C

IOUT (mA)–5 –4 –3 –2 –1 0 1 2 3 4 5

–1

–0.8

–0.6

–0.4

–0.2

0

0.2

0.4

0.6

0.8

1.0

V OS

(mV)

6258 G07

VS = 5V +IN–IN

VCM (V)0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

–20

–16

–12

–8

–4

0

4

8

12

16

20

INPU

T BI

AS C

URRE

NT (n

A)

6258 G08

VS = 1.8V +IN–IN

VCM (V)0 0.3 0.6 0.9 1.2 1.5 1.8

–20

–16

–12

–8

–4

0

4

8

12

16

20

INPU

T BI

AS C

URRE

NT (n

A)

6258 G09


LTC6258/LTC6259/LTC6260

86258960fa



Supply Current vs Temperature Per Channel

Output Saturation Voltage vs Load Current

Output Saturation Voltage vs Load Current

Output Short-Circuit Current vs Supply Voltage (Sourcing)

Output Short-Circuit Current vs Supply Voltage (Sinking)

0.1Hz to 10Hz Output Voltage Noise

Input Bias Current vs Supply Voltage Input Bias Current vs Temperature

Supply Current vs Supply Voltage per Channel

VCM = 0.4V +IB (nA)–IB (nA)

SUPPLY VOLTAGE (V)1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3

–10

–8

–6

–4

–2

0

2

4

6

8

10

INPU

T BI

AS C

URRE

NT (n

A)

6258 G10

VS = ±2.5V

+IB, VCM = 2V–IB, VCM = 2V+IB, VCM = –2V–IB, VCM = –2V

TEMPERATURE (°C)–40 –25 –10 5 20 35 50 65 80 95 110 125

–20

–15

–10

–5

0

5

10

15

20

INPU

T BI

AS C

URRE

NT (n

A)

6262 G11

VS = 5VVCM = 0.4V

25°C–40°C125°C

SUPPLY VOLTAGE (V)0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

0

2

4

6

8

10

12

14

16

18

20

SUPP

LY C

URRE

NT (u

A)

6258 G12

VCM = 0.4VVS = 5VVS = 1.8V

TEMPERATURE (°C)–50 –20 10 40 70 100 130

0

5

10

15

20

25

SUPP

LY C

URRE

NT (µ

A)

6258 G13

–40°C/5V25°C/5V85°C/5V125°C/5V–40°C/1.8V25°C/1.8V85°C/1.8V125°C/1.8V

LOAD CURRENT (mA)0 0.5 1 1.5 2

–350

–300

–250

–200

–150

–100

–50

0

SATU

RATI

ON V

OLTA

GE F

ROM

TOP

RAI

L (m

V)

6258 G14

–40°C/5V25°C/5V85°C/5V125°C/5V–40°C/1.8V25°C/1.8V85°C/1.8V125°C/1.8V

LOAD CURRENT (mA)0 0.5 1 1.5 2

0

50

100

150

200

250

300

350

SATU

RATI

ON V

OLTA

GE F

ROM

BOT

TOM

RAI

L (m

V)

6258 G15

VCM = 0.4V

25°C125°C

–40°C

SUPPLY VOLTAGE (V)1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3

0

5

10

15

20

25

MAX

IMUM

SOU

RCIN

G CU

RREN

T (m

A)

6258 G16

VCM = 0.4V

SUPPLY VOLTAGE (V)1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3

0

5

10

15

20

25

30

MAX

IMUM

SIN

KING

CUR

RENT

(mA)

6259 G17

25°C125°C

–40°C

VS = ±2.5VVCM = 0.4VAV = 1

TIME (s)0 1 2 3 4 5 6 7 8 9 10

–5

–4

–3

–2

–1

0

1

2

3

4

5

NOIS

E VO

LTAG

E (µ

V)

6258 G18


LTC6258/LTC6259/LTC6260

6258960fa



Total Harmonic Distortion and Noise

Total Harmonic Distortion and Noise

Gain and Phase vs Frequency

Noise Voltage Density vs Frequency

Input Referred Current Noise vs Frequency

Slew Rate vs Supply Voltage

Common Mode Rejection Ratio vs Frequency

Power Supply Rejection Ratio vs Frequency

VS = ±2.5VVCM = 0V

FREQUENCY (Hz)1 10 100 1k 10k 100k 1M

0

50

100

150

200

250

300

350

400

450

500

INPU

T RE

FERR

ED V

OLTA

GE N

OISE

(nV/

√Hz)

6258 G19

VS = 2.5VVCM = 0V

FREQUENCY (MHz)0.1 1

0.01

0.1

1

10

INPU

T RE

FERR

ED C

URRE

NT N

OISE

(pA/

√Hz)

6258 G20

VS = ±0.9VVCM = 0VAV = 2RG = RF = 10kΩ

1kHz500Hz

VOUTP–P (V)0.01 0.1 1

0.01

0.1

1

THD+

N (%

)

6259 G21

VS = ±2.5VVCM = 0VAV = 2RG = RF = 10kΩ

1kHz500Hz

VOUTP-P (V)0.01 0.1 1 10

0.01

0.1

1

THD+

N (%

)

6258 G23

VS = ±2.5VVCM = 0V

GAINPHASE

FREQUENCY (Hz)10k 100k 1M 10M

–50

–40

–30

–20

–10

0

10

20

30

40

50

0

9

18

27

36

45

54

63

72

81

90

GAIN

(dB) PHASE

6258 G23

VSTEP = VS – 1VAV = –1RG=RF = 10kΩ

RISINGFALLING

SUPPLY VOLTAGE (V)1.8 2.6 3.4 4.2 5

0

0.1

0.2

0.3

0.4

0.5

SLEW

RAT

E (V

/µs)

6258 G24

VS = 5V

VCM = ±2.5VVCM = 0V

FREQUENCY (Hz)1k 10k 100k 1M 10M

0

10

20

30

40

50

60

70

80

90

100

CMRR

(dB)

6258 G25

VS = 5VVCM = 0.4V

FREQUENCY (Hz)100 1k 10k 100k 1M 10M

0

10

20

30

40

50

60

70

80

90

100

PSRR

(dB)

6258 G26

VS = ±2.5VVCM = 0VAV = 1VIN = ±2V

CAPACITIVE LOAD (nF)0.01 0.1 1 10 1000

1

2

3

4

5

OVER

SHOO

T (%

)

6258 G27

Capacitive Load Handling Overshoot vs Capacitive Load


LTC6258/LTC6259/LTC6260

106258960fa



Small-Signal Response

Small-Signal Response

Electromagnetic Interference Rejection Ratio

Large-Signal Response

Supply Current vs SHDN Pin Voltage

Supply Current vs SHDN Pin Voltage

Large-Signal Response

Output Impedance vs Frequency

VS = ±2.5VAV = 1RLOAD = 100kΩ

10pF100pF1nF10nF100nF

TIME (µs)0 200 400 600 800 1000

–2.5

–2.0

–1.5

–1.0

–0.5

0

0.5

1.0

1.5

2.0

2.5

VOLT

AGE

(V)

6258 G28


CLOAD = 10pFCLOAD = 100pFCLOAD = 1nFCLOAD = 10nFCLOAD = 100nF

TIME (µs)0 200 400 600 800 1000

–50

–40

–30

–20

–10

0

10

20

30

40

50

VOLT

AGE

(mV)

6259 G30



TIME (µs)0 200 400 600 800 1000

–1.0

–0.8

–0.6

–0.4

–0.2

0.0

0.2

0.4

0.6

0.8

1.0

VOLT

AGE

(V)

6258 G30



TIME (µs)0 200 400 600 800 1000

–50

–40

–30

–20

–10

0

10

20

30

40

50

VOLT

AGE

(mV)

6258 G31

VS = ±2.5VVCM = 0V

AV = 10AV = 1

FREQUENCY (kHz)0.01 0.1 1 10

0.1

1

10

100

1k

10k

OUTP

UT IM

PEDA

NCE

(Ω)

6258 G32

VS = 5VVCM = 0.4V

TA = 125°CTA = 25°CTA = –40°C

VSHDN (V)0 0.4 0.8 1.2 1.6 2

0

5

10

15

20

25

SUPP

LY C

URRE

NT (µ

A)

6258 G33

VS = 1.8VVCM = 0.4V

TA = 125°CTA = 25°CTA = –40°C

VSHDN (V)0 0.4 0.8 1.2 1.6 2

0

5

10

15

20

25

SUPP

LY C

URRE

NT (µ

A)

6258 G34

VS = 2.5VVCM = 0VINPUT POWER = –10dBm

+IN–IN

FREQUENCY (MHz)10 100 1000 10000

0

10

20

30

40

50

60

70

80

90

100

EMI R

EJEC

TION

RAT

IO (d

B)

6258 G35


LTC6258/LTC6259/LTC6260

6258960fa


PIN FUNCTIONS–IN: Inverting Input of the Amplifier. Voltage range of this pin can go from V– – 0.1V to V+ + 0.1V.

+IN: Noninverting Input of Amplifier. This pin has the same voltage range as –IN.

V+: Positive Power Supply. Typically the voltage is from 1.8V to 5.25V. Split supplies are possible as long as the voltage between V+ and V– is between 1.8V and 5.25V. A bypass capacitor of 0.1µF as close to the part as possible should be used between power supply pins or between supply pins and ground.

V–: Negative Power Supply. It is normally tied to ground. It can also be tied to a voltage other than ground as long as the voltage between V+ and V– is from 1.8V to 5.25V. If it is not connected to ground, bypass it with a capacitor of 0.1µF as close to the part as possible.

SHDN: Active Low Shutdown. Shutdown threshold is 0.6V above negative rail. If left unconnected, the amplifier will be on.

OUT: Amplifier Output. Rail-to rail amplifier output capable of delivering 4mA.


LTC6258/LTC6259/LTC6260

126258960fa


SIMPLIFIED SCHEMATIC

Figure 1. LTC6258/LTC6259/LTC6260 Simplified Schematic

+I2

Q17 Q18

ESDD4

–IN

+IN

V–

Q3Q4

Q6

Q8

R2

R4

Q9

Q12

R1

R3R6

Q7

Q16

ESDD3

V+

ESDD1

V+

ESDD2

V–

V–

V+

SHDN

V–

D8

D7

ESDD5

ESDD6

D6

D5

Q2

Q5 VBIAS

Q1

+I1

I3

Q19

R5

Q11

Q10

Q13

Q15

OUT

C2

C1

+

Q14

CC

BUFFER ANDOUTPUT BIAS

6258960 F01

LOGIC


LTC6258/LTC6259/LTC6260

6258960fa


OPERATIONThe LTC6258 family input signal range extends beyond the negative and positive power supplies. Figure 1 depicts a Simplified Schematic of the amplifier. The input stage is comprised of two differential amplifiers, a PNP stage Q1/Q2 and NPN stage Q3/Q4 that are active over different ranges of common mode input voltage. The PNP stage is active between the negative power supply to approxi-mately 1V below the positive supply. As the input voltage approaches the positive supply, transistor Q5 will steer the tail current I1 to the current mirror Q6/Q7, activating the NPN differential pair and the PNP pair becomes inactive for the remaining input common mode range. Also for the

input stage, devices Q17, Q18 and Q19 act to cancel the bias current of the PNP input pair. When Q1/Q2 is active, the current in Q16 is controlled to be the same as the current Q1/Q2. Thus, the base current of Q16 is normally equal to the base current of the input devices of Q1/Q2. Similar circuitry (not shown) is used to cancel the base current of Q3/Q4. The buffer and output bias stage uses a special compensation technique to take full advantage of the process technology to drive high capacitive loads. The common emitter topology of Q14/Q15 enables the output to swing from rail to rail.


LTC6258/LTC6259/LTC6260

146258960fa


APPLICATIONS INFORMATIONLow Supply Voltage and Low Power Consumption

The LTC6258 family of operational amplifiers can oper-ate with power supply voltages from 1.8V to 5.25V. Each amplifier draws 20µA. The low supply voltage capability and low supply current are ideal for portable applications.

High Capacitive Load Driving Capability and Wide Bandwidth

The LTC6258 family is optimized for wide bandwidth low power applications. They have a high gain-bandwidth to power ratio and are unity gain stable. When the load capacitance increases, the increased capacitance at the output pushes the non-dominant pole to lower frequency in the open loop frequency response, worsening the phase and gain margin. The LTC6258 family are designed to directly drive up to 100nF of capacitive load in unity gain configuration (see Typical Performance Characteristics, Capacitive Load Handling).

Low Input Referred Noise

The LTC6258 family provides a low input referred noise of 38nV/√Hz at 1kHz. The average noise voltage density over a 100kHz bandwidth is less than 80nV/√Hz. The LTC6258 family is ideal for low noise and low power signal process-ing applications.

Low Input Offset Voltage

The LTC6258 family has a low offset voltage of 400μV, which is essential for precision applications. The offset voltage is trimmed with a proprietary trim algorithm to ensure low offset voltage over the entire common mode voltage range.

Low Input Bias Current

The LTC6258 family uses a bias current cancellation circuit to compensate for the base current of the input transistors. When the input common mode voltage is within 200mV of either rail, the bias cancellation circuit is no longer active. For common mode voltages ranging from 0.2V above the negative supply to 0.2V below the positive supply, the low input bias current allows the amplifiers to be used in applications with high resistance sources.

Ground Sensing and Rail to Rail Output

The LTC6258 family delivers over 4mA of output drive current. The output stage is a rail-to-rail topology that is capable of swinging to within 300mV of either rail. If output swing to the negative rail is required, an external pull down resistor to a negative supply can be added. For 5V/0V op amp supplies, a pull down resistor of 10k to –2V will allow a ‘true zero’ output swing. In this case, the output can swing all the way to the bottom rail while maintaining 45dB of open loop gain. Since the inputs can go 100mV beyond either rail, the op amp can easily perform ‘true ground’ sensing.

The maximum output current is a function of total supply voltage. As the supply voltage to the amplifier increases, the maximum output current also increases. Attention must be paid to keep the junction temperature of the IC below 150°C when the output is in continuous short-circuit. The output of the amplifier has reverse-biased diodes con-nected to each supply. The output should not be forced more than 0.5V beyond either supply, otherwise current will flow through these diodes.

EMI Rejection

Electromagnetic interference (EMI) rejection is built into the LTC6258 op amp family. Rejection is measured by injecting 200mVP-P (–10dBm) RF signal into the pins and measuring the offset change (delta_VOS). The rejection ratio is calculated as 20log (100mV/delta_VOS).

Input Protection and Output Overdrive

To prevent breakdown of the input transistors, the input stages are protected against a large differential input voltage by two pairs of back-to-back diodes, D5 to D8. If the differential input voltage exceeds 1.4V, the current in these diodes must be limited to less than 10mA. These amplifiers are not intended for open loop applications such as comparators. When the output stage is overdriven, internal limiting circuitry is activated to improve overdrive recovery. In some applications, this circuitry may draw as much as 1mA supply current.


LTC6258/LTC6259/LTC6260

6258960fa


ESD

The LTC6258 family has reverse-biased ESD protection diodes on all inputs and output as shown in Figure 1.

Supply Voltage Ramping

Fast ramping of the supply voltage can cause a current glitch in the internal ESD protection circuits. Depending on the supply inductance, this could result in a supply volt-age transient that exceeds the maximum rating. A supply voltage ramp time of greater than 1ms is recommended.

Feedback Components

Care must be taken to ensure that the pole formed by the feedback resistors and the parasitic capacitance at the inverting input does not degrade stability. For example, in a gain of +2 configuration with gain and feedback resis-tors of 100k, a poorly designed circuit board layout with parasitic capacitance of 5pF (part +PC board) at the ampli-fier’s inverting input will cause the amplifier to oscillate due to a pole formed at 640kHz. An additional capacitor of 4.7pF across the feedback resistor as shown in Figure 2 will eliminate any ringing or oscillation.

Shutdown

The single and dual versions have package options with SHDN pins that can shut down the amplifier to less than 7µA supply current. The SHDN pin voltage needs to be within 0.6V of V– for the amplifier to shut down. During shutdown, the output is in a high output impedance state. When left floating, the SHDN pin is internally pulled up to the positive supply and the amplifier remains enabled.

100k

100k

4.7pF

CPAR VOUT

VIN 6258960 F02

+

–LTC6258

Figure 2.

Figure 3a. 10kHz Bandpass Filter

Figure 3b. Frequency Response of 10kHz Bandpass Filter of Figure 3a

APPLICATIONS INFORMATION

V+

V+

C14.7nF

C24.7nF

R221k

C34.7nF

R3562Ω

RA1499k

6258 F03a

RA2499k

CD11µF

R110k

R810kIN

OUT

CD20.1µF

U1

LT6259

–+

5dB/DIV

5dB

–45dB6258 F03b

Active Filter

The bandpass filter Figure 3a is AC-coupled to an input. As a result, LTC6259 input does not place a burden on the previous stage to develop an absolute common mode voltage. A simple resistor divider with RA1 and RA2 provides biasing for the LTC6259 inputs. Pegging the op amp inputs to a fixed voltage helps to reduce distortion that might arise with moving common mode. This filter is centered at 10kHz. The exact resistance and capacitance values can be tweaked upwards or downwards, depending on whether lowest resistor noise or lowest total supply current is more important.


LTC6258/LTC6259/LTC6260

166258960fa


Figure 4b. Low Power Sine Generator

Figure 4c. FFT

Figure 4a. Low Power Squarewave - Sinewave Oscillator


Low Power Sine Wave Generator

A low power sine wave generator can be derived by driving a square wave into the bandpass filter. A complete schematic is shown in Figure 4a. The LTC6992-1 easily configures as a 50% duty cycle 10kHz square wave, and can drive the relatively benign loading seen in the bandpass filter.

Figures 4b and 4c show the LTC6992-1 output and bandpass filter output. THD of the sine wave is –30.5 dBc. Note, even harmonics that appear in the distortion products of the filtered output already appear in the source square wave.

Low Noise Reference

The LT6656 is a 1µA precision series voltage reference. Yet with low power comes low drive current capability and higher noise. The LTC6259 can be used as a buf-fer that follows a filter to enhance the utilization of the LT6656 in low power applications. Figure 5a shows such a configuration. First a very low cutoff frequency follows the LT6656 output (RIN1 and CIN1, lower than 5Hz cutoff). Choice of filter resistor RIN1 is such that the bias current in the LTC6259, multiplied by the resistance value, is lower than the nominal offset voltage of the op amp. CIN1 can be larger or smaller, with more or less filtering accord-ingly. The voltage withstanding requirement of CIN1 is low, resulting in large capacitance in a small volume.

V+

V+

4.7nF

4.7nF

21k

4.7nF

154k 182k

976k 0.1µF154k562Ω

499k

6258 F04a

499k1µF

10k 10kMOD

LTC6992-1GND

SET

OUT

V+

DIV

OUT

0.1µF

LT6258

–+

V+

50µs/Div0

1.0

2.0

3.0

4.0

5.0

LTC6

992–

1 OU

TPUT

(V)

6258 F04b

FILTERED OUTPUTSQUARE WAVE

FREQUENCY (kHz)0 10 20 30 40 50 60 70 80 90 100

–120

–100

–80

–60

–40

–20

0

20

AMPL

ITUD

E (d

B)

6258 F04c


LTC6258/LTC6259/LTC6260

6258960fa



–+

5V

V+OUT

LTC6258

6258960 F05a

22µF22µF

RIN12.7k

22µFIN OUT

GND

LT6656

Figure 5a. Low Noise Reference Use LT6656 for a Low Current Starting Reference

Figure 5b. Noise Density, Reference Buffer

Figure 5c. Reference Buffer Transient Response

* 2.7k + 22µF FILTER

OP AMP, 44µF CLOADOP AMPFILTERED REFERENCEREFERENCE OUTPUTINSTRUMENT ONLY

FREQUENCY (kHz)0.01 0.1 1 10 1000

500

1000

1500

2000

2500

3000

3500

4000

4500

5000

NOIS

E DE

NSIT

Y (n

Vrm

s/rt(

Hz))

6258 F05b

This circuit takes advantage of the ability of the LTC6259 to drive large capacitive loads. Use of a large output capacitor attached to the LT6659 enables significant bypassing of follow-on circuits that use the reference voltage. In total, the combination of LT6656 and LTC6259, in this configuration, develops a reference voltage, with low noise, at low power, and with appreciably large available bypass capacitance.

Voltage spectral noise densities are shown in Figure 5b. Larger noise from the reference below 10kHz noticeably drops down once a filter (RIN1 and CIN1) follow the refer-ence. The op amp, configured in unity gain, with a large 44µF load, remains stable and contributes only a small amount of low frequency noise. Figure 5c shows the tran-sient response of the combination of RIN1-CIN1 filter and op amp circuit, with and without the 44µF output capacitor.

Figure 5c shows the time domain response of the refer-ence buffer.

The total measured supply current consumption is 21µA.

Analog LED Control

Figure 6a shows a voltage controlled LED drive circuit. When VIN is at 0V, the op amp supply current is nominally 20μA. The offset, for example, could be 450µV, appears across R1, inducing a 0.45mA current in the LED. Some applications want a guaranteed zero LED current at VIN = 0, and this is the purpose of R5. R5 forces 2.5μA current through R7, creating a negative 0.6mV sense offset. This offset guarantees a zero LED current.

INPUTNO 44µF OUTPUT CAPADD 44µF OUTPUT CAP

200ms/Div1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

VOLT

S (V

)

6258 F05c


LTC6258/LTC6259/LTC6260

186258960fa



Figure 6a. Lower Power LED Driver with Voltage Command

Figure 6b. LED Current

–+

D1D

M12N7002

R11Ω

R6100k

R7237Ω

R451Ω

R52M

LTC6258

5V

R32.2k

R297.6k

VIN

C1100nF

6258 F06a

C210nF

VG

Indeed, the circuit works nicely. Once the input voltage is near 0, the LED current output is 0 and the total supply current is 20µA. Gain from the input voltage to LED cur-rent is 0.022A/V, as can be taken from the R2/R3 voltage divider and the sense resistor value.

LED Current= VIN

R1•

R3R2+R3

Self-Oscillating LED Driver

Taking the circuit of the above application a step further, the circuit of Figure 7a combines edge detection with use of the shutdown pin of the LTC6259. R2 and R3 bring in a divided down copy of the supply voltage as a reference into the positive terminal. The op amp forces this voltage on the sense resistor RSENSE in “LED ON” operation. In that sense this circuit is similar to the one above.

20 µA SUPPLY WHEN LED OFF

MEASUREDCALCULATED

INPUT VOLTAGE (V)0 1 2 3 4 5

0

20

40

60

80

100

LED

CURR

ENT

(mA)

6258 F06b

However, whereas the previous circuit assumes an always-on operation mode, this new circuit hijacks the shutdown pin. C2 can AC couple fast action signals into the signal VC. Hence when the gate voltage VG increases when “LED ON” begins, VC will suddenly rise. VC connects to the shutdown pin; a rising edge on the shutdown pin enables the LTC6259, which is already active, to stay on. However, M3 is also on while M1 is on, and as a result will work with R9 to charge C2 slowly until VC falls below the shutdown threshold. At that moment, the active low shutdown kicks in, and the LTC6259 turns off. A negative falling VG voltage again feeds through C2, and a falling VC and hence a falling shutdown pin voltage keeps the circuit in an “LED OFF” state for some time. M3 turns off, and C2 discharges until VC is high enough to reactivate the LTC6259.

It may seem a bit odd to develop such a circuit when a microprocessor or a LTC6992 can provide on-off capabil-ity in combination with a single MOSFET and resistor. The problem with those circuits, however, is the lack of control over the LED current. In the circuit of this application, a voltage is controlled across a sense resistor. There is no dependence on the LED voltage in how much current drives the LED. And generation of the on-off, or blinking, comes with the addition of only a handful of low cost components.


LTC6258/LTC6259/LTC6260

6258960fa



It is interesting to note that the LED current depends on the supply in this implementation in as much as the supply feeds through R2 and R3 to create a reference. The supply also figures into the time of the on and off cycle since the supply powers the edge detection and relaxation part of the circuitry. When the supply falls, the LED current drops and the cycle time increases. This change of behavior can help in battery powered LED blinking applications to predict end of life.

The figure shows the sense resistor voltage (red) and the shutdown pin voltage (blue). The shutdown voltage is tied to VC; the gate drive couples through C2 as already described.

Components RF and CF may apparently slow edges down greatly. Adding this much delay is not essential, but it can help to smooth out any hiccups that occur when the part goes through a startup sequence after the shutdown pin goes inactive. 47µs as a time constant is insignificant in the time scale of the blinking (10’s or 100’s of ms). The 47µs is much smaller than any time constant associated with C2 and its resistors.

VG

VG

VC

VC

R451Ω M1

2N7002

LED

D

RSENSE10Ω

R2275k

R315k

C11nF

C21µF

RGATE10k

R51M

R81M

M32N7002

6258 F07a

R7470k

R9140k

U2

LTC6258RF

100Ω

CF470nF

5V

–+

Figure 7a. LED Driver with Self-Oscillation

Figure 7b. LED Blinker Circuit

50ms/Div–60.0

0

60.0

120.0

180.0

240.0

300.0

–2.0

–1.0

0

1.0

2.0

3.0

4.0

SENS

E RE

SIST

OR V

OLTA

GE (m

V) SHUTDOWN PIN VOLTAGE (V)

6258 F07b


LTC6258/LTC6259/LTC6260

206258960fa


PACKAGE DESCRIPTIONPlease refer to http://www.linear.com/product/LTCLTC6258#packaging for the most recent package drawings.

1.50 – 1.75(NOTE 4)

2.80 BSC

0.30 – 0.45 6 PLCS (NOTE 3)

DATUM ‘A’

0.09 – 0.20(NOTE 3) S6 TSOT-23 0302

2.90 BSC(NOTE 4)

0.95 BSC

1.90 BSC

0.80 – 0.90

1.00 MAX0.01 – 0.10

0.20 BSC

0.30 – 0.50 REF

PIN ONE ID

NOTE:1. DIMENSIONS ARE IN MILLIMETERS2. DRAWING NOT TO SCALE3. DIMENSIONS ARE INCLUSIVE OF PLATING4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR5. MOLD FLASH SHALL NOT EXCEED 0.254mm6. JEDEC PACKAGE REFERENCE IS MO-193

3.85 MAX

0.62MAX

0.95REF

RECOMMENDED SOLDER PAD LAYOUTPER IPC CALCULATOR

1.4 MIN2.62 REF

1.22 REF

S6 Package6-Lead Plastic TSOT-23

(Reference LTC DWG # 05-08-1636)


http://www.linear.com/product/LTC%23%23%23%23-X%23packaging

LTC6258/LTC6259/LTC6260

6258960fa


PACKAGE DESCRIPTION

1.50 – 1.75(NOTE 4)

2.80 BSC

0.22 – 0.36 8 PLCS (NOTE 3)

DATUM ‘A’

0.09 – 0.20(NOTE 3)

TS8 TSOT-23 0710 REV A

2.90 BSC(NOTE 4)

0.65 BSC

1.95 BSC

0.80 – 0.90

1.00 MAX0.01 – 0.10

0.20 BSC

0.30 – 0.50 REF

PIN ONE ID

NOTE:1. DIMENSIONS ARE IN MILLIMETERS2. DRAWING NOT TO SCALE3. DIMENSIONS ARE INCLUSIVE OF PLATING4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR5. MOLD FLASH SHALL NOT EXCEED 0.254mm6. JEDEC PACKAGE REFERENCE IS MO-193

3.85 MAX

0.40MAX

0.65REF

RECOMMENDED SOLDER PAD LAYOUTPER IPC CALCULATOR

1.4 MIN2.62 REF

1.22 REF

TS8 Package8-Lead Plastic TSOT-23

(Reference LTC DWG # 05-08-1637 Rev A)

Please refer to http://www.linear.com/product/LTC6259#packaging for the most recent package drawings.


http://www.linear.com/product/LTC6259#packaging

LTC6258/LTC6259/LTC6260

226258960fa


PACKAGE DESCRIPTIONPlease refer to http://www.linear.com/product/LTC6259#packaging for the most recent package drawings.

MSOP (MS8) 0213 REV G

0.53 ±0.152(.021 ±.006)

SEATINGPLANE

NOTE:1. DIMENSIONS IN MILLIMETER/(INCH)2. DRAWING NOT TO SCALE3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

0.18(.007)

0.254(.010)

1.10(.043)MAX

0.22 – 0.38(.009 – .015)

TYP

0.1016 ±0.0508(.004 ±.002)

0.86(.034)REF

0.65(.0256)

BSC

0° – 6° TYP

DETAIL “A”

DETAIL “A”

GAUGE PLANE

1 2 3 4

4.90 ±0.152(.193 ±.006)

8 7 6 5

3.00 ±0.102(.118 ±.004)

(NOTE 3)

3.00 ±0.102(.118 ±.004)

(NOTE 4)

0.52(.0205)

REF

5.10(.201)MIN

3.20 – 3.45(.126 – .136)

0.889 ±0.127(.035 ±.005)

RECOMMENDED SOLDER PAD LAYOUT

0.42 ± 0.038(.0165 ±.0015)

TYP

0.65(.0256)

BSC

MS8 Package8-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1660 Rev G)



LTC6258/LTC6259/LTC6260

6258960fa



MSOP (MS) 0213 REV F

0.53 ±0.152(.021 ±.006)

SEATINGPLANE

0.18(.007)

1.10(.043)MAX

0.17 – 0.27(.007 – .011)

TYP

0.86(.034)REF

0.50(.0197)

BSC

1 2 3 4 5

4.90 ±0.152(.193 ±.006)

0.497 ±0.076(.0196 ±.003)

REF8910 7 6

3.00 ±0.102(.118 ±.004)

(NOTE 3)

3.00 ±0.102(.118 ±.004)

(NOTE 4)


0.254(.010) 0° – 6° TYP

DETAIL “A”

DETAIL “A”

GAUGE PLANE

5.10(.201)MIN

3.20 – 3.45(.126 – .136)

0.889 ±0.127(.035 ±.005)


0.305 ±0.038(.0120 ±.0015)

TYP

0.50(.0197)

BSC

0.1016 ±0.0508(.004 ±.002)

MS Package10-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1661 Rev F)



LTC6258/LTC6259/LTC6260

246258960fa



MSOP (MS16) 0213 REV A

0.53 ±0.152(.021 ±.006)

SEATINGPLANE

0.18(.007)

1.10(.043)MAX

0.17 – 0.27(.007 – .011)

TYP

0.86(.034)REF

0.50(.0197)

BSC

16151413121110

1 2 3 4 5 6 7 8

9


0.254(.010) 0° – 6° TYP

DETAIL “A”

DETAIL “A”

GAUGE PLANE

5.10(.201)MIN

3.20 – 3.45(.126 – .136)

0.889 ±0.127(.035 ±.005)


0.305 ±0.038(.0120 ±.0015)

TYP

0.50(.0197)

BSC

4.039 ±0.102(.159 ±.004)

(NOTE 3)

0.1016 ±0.0508(.004 ±.002)

3.00 ±0.102(.118 ±.004)

(NOTE 4)

0.280 ±0.076(.011 ±.003)

REF

4.90 ±0.152(.193 ±.006)

MS Package16-Lead Plastic MSOP




LTC6258/LTC6259/LTC6260

6258960fa



2.00 ±0.10(4 SIDES)

NOTE:1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WCCD-2)2. DRAWING NOT TO SCALE3. ALL DIMENSIONS ARE IN MILLIMETERS4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

0.40 ±0.10

BOTTOM VIEW—EXPOSED PAD

0.60 ±0.10(2 SIDES)

0.75 ±0.05

R = 0.125TYP

R = 0.05TYP

1.37 ±0.10(2 SIDES)

13

64

PIN 1 BARTOP MARK

(SEE NOTE 6)

0.200 REF

0.00 – 0.05

(DC6) DFN REV C 0915

0.25 ±0.050.50 BSC

0.25 ±0.05

1.37 ±0.10(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

0.60 ±0.10(2 SIDES)

1.15 ±0.05

0.70 ±0.05

2.55 ±0.05

PACKAGEOUTLINE

0.50 BSC

PIN 1 NOTCH R = 0.20 OR 0.25 × 45° CHAMFER

DC6 Package6-Lead Plastic DFN (2mm × 2mm)

(Reference LTC DWG # 05-08-1703 Rev C)



LTC6258/LTC6259/LTC6260

266258960fa



2.00 ±0.10(4 SIDES)

NOTE:1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE2. DRAWING NOT TO SCALE3. ALL DIMENSIONS ARE IN MILLIMETERS4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

0.40 ±0.10

BOTTOM VIEW—EXPOSED PAD

0.64 ±0.10(2 SIDES)

0.75 ±0.05

R = 0.115TYP

R = 0.05TYP

1.37 ±0.10(2 SIDES)

14

85

PIN 1 BARTOP MARK

(SEE NOTE 6)

0.200 REF

0.00 – 0.05

(DC8) DFN 0409 REVA

0.23 ±0.050.45 BSC

0.25 ±0.05

1.37 ±0.05(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONSAPPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.64 ±0.05(2 SIDES)

1.15 ±0.05

0.70 ±0.05

2.55 ±0.05

PACKAGEOUTLINE

0.45 BSC

PIN 1 NOTCH R = 0.20 OR 0.25 × 45° CHAMFER

DC8 Package8-Lead Plastic DFN (2mm × 2mm)




LTC6258/LTC6259/LTC6260

6258960fa


Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

REVISION HISTORYREV DATE DESCRIPTION PAGE NUMBER

A 04/17 Added SOT-23 package. 1, 2, 3, 20


LTC6258/LTC6259/LTC6260

286258960fa

For more information www.linear.com/LTC6258 LINEAR TECHNOLOGY CORPORATION 2017

LT 0417 REV A • PRINTED IN USAwww.linear.com/LTC6258

TYPICAL APPLICATION

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–1.0

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LTC6258/LTC6259/LTC6260 - 1.3MHz, 20µA Power …...1.3MHz, 20µA Power Efficient Rail-to-Rail I/O Op Amps The LTC®6258/LTC6259/LTC6260 are single/dual/quad operational amplifiers

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