LTC2309 2309fd BLOCK DIAGRAM FEATURES APPLICATIONS DESCRIPTION 8-Channel, 12-Bit SAR ADC with I 2 C Interface n Industrial Process Control n Motor Control n Accelerometer Measurements n Battery-Operated Instruments n Isolated and/or Remote Data Acquisition n Power Supply Monitoring Integral Nonlinearity vs Output Code n 12-Bit Resolution n Low Power: 1.5mW at 1ksps, 35µW Sleep Mode n 14ksps Throughput Rate n Low Noise: SNR = 73.4dB n Guaranteed No Missing Codes n Single 5V Supply n 2-Wire I 2 C Compatible Serial Interface with Nine Addresses Plus One Global for Synchronization n Fast Conversion Time: 1.3µs n Internal Reference n Internal 8-Channel Multiplexer n Internal Conversion Clock n Unipolar or Bipolar Input Ranges (Software Selectable) n Guaranteed Operation from –40°C to 125°C (TSSOP Package) n 24-Pin 4mm × 4mm QFN and 20-Pin TSSOP Packages The LTC ® 2309 is a low noise, low power, 8-channel, 12-bit successive approximation ADC with an I 2 C compatible serial interface. This ADC includes an internal reference and a fully differential sample-and-hold circuit to reduce common mode noise. The LTC2309 operates from an internal clock to achieve a fast 1.3µs conversion time. The LTC2309 operates from a single 5V supply and draws just 300µA at a throughput rate of 1ksps. The ADC enters nap mode when not converting, reducing the power dissipation. The LTC2309 is available in both a small 24-pin 4mm × 4mm QFN and a 20-pin TSSOP package. The internal 2.5V reference and 8-channel multiplexer further reduce PCB board space requirements. The low power consumption and small size make the LTC2309 ideal for battery-operated and portable applica- tions, while the 2-wire I 2 C compatible serial interface makes this ADC a good match for space-constrained systems. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarksand Easy Drive is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM 2309 TA01 I 2 C PORT ANALOG INPUT MUX ANALOG INPUTS 0V TO 4.096V UNIPOLAR ±2.048V BIPOLAR REFCOMP INTERNAL 2.5V REF V DD 5V GND LTC2309 0.1μF 12-BIT SAR ADC + – 2.2μF 10μF 0.1μF 10μF V REF SDA SCL AD1 AD0 OUTPUT CODE 0 INL (LSB) 0 0.25 0.50 4096 2309 G01 –0.25 –0.50 –1.00 1024 2048 3072 –0.75 1.00 0.75
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Embed
LTC2309 - 8-Channel, 12-Bit SAR ADC with I2C Interface · ch1 ch2 ch3 ch4 ch5 ch6 ch7 com 2309 ta01 i2c port analog input mux analog inputs 0v to 4.096v unipolar ±2.048v bipolar
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LTC2309
2309fd
BLOCK DIAGRAM
FeAtuRes
AppLICAtIOns
DesCRIptIOn
8-Channel, 12-Bit SAR ADC with I2C Interface
n IndustrialProcessControln MotorControln AccelerometerMeasurementsn Battery-OperatedInstrumentsn Isolatedand/orRemoteDataAcquisitionn PowerSupplyMonitoring
Integral Nonlinearity vs Output Code
n 12-Bit Resolutionn Low Power: 1.5mW at 1ksps, 35µW Sleep Moden 14ksps Throughput Raten Low Noise: SNR = 73.4dBn GuaranteedNoMissingCodesn Single5VSupplyn 2-WireI2CCompatibleSerialInterfacewithNine
TheLTC®2309isalownoise,lowpower,8-channel,12-bitsuccessive approximation ADC with an I2C compatibleserialinterface.ThisADCincludesaninternalreferenceandafullydifferentialsample-and-holdcircuittoreducecommon mode noise. The LTC2309 operates from aninternalclocktoachieveafast1.3µsconversiontime.
The LTC2309 operates from a single 5V supply anddraws just 300µA at a throughput rate of 1ksps. TheADCentersnapmodewhennot converting, reducingthepowerdissipation.
The low power consumption and small size make theLTC2309idealforbattery-operatedandportableapplica-tions,whilethe2-wireI2CcompatibleserialinterfacemakesthisADCagoodmatchforspace-constrainedsystems.L,LT,LTC,LTM,LinearTechnologyandtheLinearlogoareregisteredtrademarksandEasyDriveisatrademarkofLinearTechnologyCorporation.Allothertrademarksarethepropertyoftheirrespectiveowners.
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
2309 TA01
I2CPORT
ANALOGINPUTMUX
ANALOG INPUTS0V TO 4.096V UNIPOLAR
±2.048V BIPOLAR
REFCOMP
INTERNAL2.5V REF
VDD
5V
GND
LTC2309
0.1µF
12-BITSAR ADC
+–
2.2µF
10µF0.1µF
10µF
VREF
SDA
SCL
AD1AD0
OUTPUT CODE0
INL
(LSB
)
0
0.25
0.50
4096
2309 G01
–0.25
–0.50
–1.001024 2048 3072
–0.75
1.00
0.75
LTC2309
2309fd
ABsOLute MAxIMuM RAtInGs (Notes 1, 2)
ORDeR InFORMAtIOnLEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
COnVeRteR AnD MuLtIpLexeR CHARACteRIstICsPARAMETER CONDITIONS MIN TYP MAX UNITSResolution(NoMissingCodes) l 12 BitsIntegralLinearityError (Note6) l ±0.45 ±1 LSBDifferentialLinearityError l ±0.35 ±1 LSBBipolarZeroError (Note7) l ±1 ±8 LSBBipolarZeroErrorDrift 0.002 LSB/°CBipolarZeroErrorMatch ±0.1 ±3 LSBUnipolarZeroError (Note7) l ±0.4 ±6 LSBUnipolarZeroErrorDrift 0.002 LSB/°CUnipolarZeroErrorMatch ±0.2 ±1 LSBBipolarFull-ScaleError ExternalReference(Note8)
IIN AnalogInputLeakageCurrent l ±1 µACIN AnalogInputCapacitance SampleMode
HoldMode555
pFpF
CMRR InputCommonModeRejectionRatio 70 dB
AnALOG Input The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITSSINAD Signal-to-(Noise+Distortion)Ratio fIN=1kHz l 71 73.3 dBSNR Signal-to-NoiseRatio fIN=1kHz l 71 73.4 dBTHD TotalHarmonicDistortion fIN=1kHz,First5Harmonics l –88 –77 dBSFDR SpuriousFreeDynamicRange fIN=1kHz l 79 90 dB
DYnAMIC ACCuRACY The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Notes 4, 10)
LTC2309
2309fd
pOWeR ReQuIReMents
PARAMETER CONDITIONS MIN TYP MAX UNITSVREFOutputVoltage IOUT=0(QFN)
InteRnAL ReFeRenCe CHARACteRIstICs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
I2C Inputs AnD DIGItAL Outputs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITSVIH HighLevelInputVoltage l 2.85 VVIL LowLevelInputVoltage l 1.5 VVIHA HighLevelInputVoltageforAddressPinsA1,A0 l 4.75 VVILA LowLevelInputVoltageforAddressPinsA1,A0 l 0.25 VRINH ResistancefromA1,A0,toVDDtoSetChip
II DigitalInputCurrent VIN=VDD l –10 10 µAVHYS HysteresisofSchmittTriggerInputs (Note9) l 0.25 VVOL LowLevelOutputVoltage(SDA) I=3mA l 0.4 VtOF OutputFallTimeVHtoVIL(MAX) (Note12) l 20+0.1CB 250 nstSP InputSpikeSuppression l 50 nsCCAX ExternalCapacitanceLoadOn-ChipAddressPins
(A1,A0)forValidFloatl 10 pF
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITSVDD SupplyVoltage l 4.75 5 5.25 VIDD SupplyCurrent 14kspsSampleRate l 2.3 3 mA
NapMode SLPBit=0,ConversionDone l 210 350 µASleepMode SLPBit=1,ConversionDone l 7 15 µA
PD PowerDissipation 14kspsSampleRate l 11.5 15 mWNapMode SLPBit=0,ConversionDone l 1.05 1.75 mWSleepMode SLPBit=1,ConversionDone l 35 75 µW
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
LTC2309
2309fd
I2C tIMInG CHARACteRIstICs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITSfSCL SCLClockFrequency l 400 kHztHD(SDA) HoldTime(Repeated)STARTCondition l 0.6 µstLOW LOWPeriodoftheSCLPin l 1.3 µstHIGH HIGHPeriodoftheSCLPin l 0.6 µstSU(STA) Set-UpTimeforaRepeatedSTARTCondition l 0.6 µstHD(DAT) DataHoldTime l 0 0.9 µstSU(DAT) DataSet-UpTime l 100 nstr RiseTimeforSDA/SCLSignals (Note12) l 20+0.1CB 300 nstf FallTimeforSDA/SCLSignals (Note12) l 20+0.1CB 300 nstSU(STO) Set-UpTimeforSTOPCondition l 0.6 µstBUF BusFreeTimeBetweenaSTOPandSTARTCondition l 1.3 µs
ADC tIMInG CHARACteRIstICs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITSfSMPL ThroughputRate(SuccessiveReads) l 14 kspstCONV ConversionTime (Note9) l 1.3 1.8 µstACQ AcquisitionTime (Note9) l 240 nstREFWAKE REFCOMPWake-UpTime(Note13) CREFCOMP=10µF,CREF=2.2µF 200 ms
pIn FunCtIOnsCH3-CH7 (Pins 1-5):Channel3toChannel7AnalogInputs.CH3-CH7canbeconfiguredassingle-endedor differential input channels. See the Analog InputMultiplexersection.
COM (Pin 6): Common Input. This is the referencepoint for all single-ended inputs. It must be free ofnoiseandshouldbeconnectedtogroundforunipolarconversionsandmidwaybetweenGNDandREFCOMPforbipolarconversions.
AD1 (Pin 15):ChipAddressControlPin.Thispin isconfigured as a three-state (LOW, HIGH, floating)address control bit for the device I2C address. SeeTable2foraddressselection.
SCL (Pin 16):SerialClockPinoftheI2CInterface.TheLTC2309canonlyactasaslaveandtheSCLpinonlyaccepts anexternal serial clock.Data is shifted intotheSDApinontherisingedgesoftheSCLclockandoutputthroughtheSDApinonthefallingedgesoftheSCLclock.
CH0-CH2 (Pins 22-24):Channel0toChannel2AnalogInputs.CH0-CH2canbeconfiguredassingle-endedor differential input channels. See the Analog InputMultiplexersection.
Exposed Pad (Pin 25): Ground. Must be soldereddirectlytogroundplane.
(QFN)
LTC2309
2309fd
pIn FunCtIOnsREFCOMP (Pin 1):ReferenceBufferOutput.Bypassto GND with 10µF and 0.1µF ceramic capacitors inparallel.Nominaloutputvoltageis4.096V.Theinternalreferencebufferdrivingthispinisdisabledbyground-ingVREF,allowingREFCOMPtobeoverdrivenbyanexternalsource.
AD1 (Pin 5): Chip Address Control Pin. This pin isconfigured as a three-state (LOW, HIGH, floating)address control bit for the device I2C address. SeeTable2foraddressselection.
SCL (Pin 6):SerialClockPinoftheI2CInterface.TheLTC2309canonlyactasaslaveandtheSCLpinonlyaccepts anexternal serial clock.Data is shifted intotheSDApinontherisingedgesoftheSCLclockandoutputthroughtheSDApinonthefallingedgesoftheSCLclock.
CH0-CH7 (Pins 11-18):Channel0toChannel7AnalogInputs.CH0-CH7canbeconfiguredassingle-endedor differential input channels. See the Analog InputMultiplexersection.
COM (Pin 19):CommonInput.Thisisthereferencepoint for all single-ended inputs. It must be free ofnoiseandshouldbeconnectedtogroundforunipolarconversionsandmidwaybetweenGNDandREFCOMPforbipolarconversions.
The LTC2309 communicates through a 2-wire I2Ccompatibleserial interface.Conversionsare initiatedbysignalingaSTOPconditionaftertheparthasbeensuccessfullyaddressedforaread/writeoperation.Thedevicewillnotacknowledge(NACK)anexternalrequestuntiltheconversionisfinished.Afteraconversionisfinished, the device is ready to accept a read/writerequest. Once the LTC2309 is addressed for a readoperation, the device begins outputting the conver-sionresultunderthecontroloftheserialclock(SCL).Thereisnolatencyintheconversionresult.Thereare12bitsofoutputdatafollowedby4trailingzeros.Dataisupdatedonthe fallingedgesofSCL,allowingtheusertoreliablylatchdataontherisingedgeofSCL.AwriteoperationmayfollowthereadoperationbyusingarepeatSTARToraSTOPconditionmaybegiventostartanewconversion.Byselectingawriteoperation,theADCcanbeprogrammedwitha6-bitDINword.TheDINwordconfigurestheMUXandprogramsvariousmodesofoperationoftheADC.
During a conversion, the internal 12-bit capacitivechargeredistributionDACoutputissequencedthroughasuccessiveapproximationalgorithmbytheSARstart-ing from themostsignificantbit (MSB) to the leastsignificantbit(LSB).ThesampledinputissuccessivelycomparedwithbinaryweightedchargessuppliedbythecapacitiveDACusingadifferentialcomparator.Attheendofaconversion,theDACoutputbalancestheanaloginput.TheSARcontents(a12-bitdataword)thatrepresentthesampledanaloginputareloadedinto12outputlatchesthatallowthedatatobeshiftedoutviatheI2Cinterface.
Programming the LTC2309
Thevariousmodesofoperationof theLTC2309areprogrammedbya6-bitDINword.TheSDIinputdatabitsareloadedontherisingedgeofSCLduringawriteoperation,withtheS/DbitloadedonthefirstrisingedgeandtheSLPbitonthesixthrisingedge(seeFigure8bin the I2C Interfacesection).The inputdataword isdefinedasfollows:
S/D O/S S1 S0 UNI SLP
S/D=SINGLE-ENDED/DIFFERENTIALBIT
O/S=ODD/SIGNBIT
S1=CHANNELSELECTBIT1
S0=CHANNELSELECTBIT0
UNI=UNIPOLAR/BIPOLARBIT
SLP=SLEEPMODEBIT
Analog Input Multiplexer
The analog input MUX is programmed by the S/D,O/S,S1andS0bitsoftheDINword.Table1liststheMUXconfigurationsforallcombinationsofthecon-figurationbits.Figure1ashowsseveralpossibleMUXconfigurationsandFigure1bshowshowtheMUXcanbereconfiguredfromoneconversiontothenext.
The noise and distortion of the input amplifier andothercircuitrymustbeconsideredsincetheywilladdtotheADCnoiseanddistortion.Therefore,noisyinputcircuitryshouldbefilteredpriortotheanaloginputstominimizenoise.Asimple1-poleRCfilterissufficientformanyapplications.
TheanaloginputsoftheLTC2309canbemodeledasa55pFcapacitor(CIN)inserieswitha100Ωresistor(RON),asshowninFigure3a.CINgetsswitchedtotheselectedinputonceduringeachconversion.LargefilterRCtimeconstantswillslowthesettlingoftheinputs.It is importantthattheoverallRCtimeconstantsbeshortenoughtoallowtheanaloginputstocompletelysettleto12-bitresolutionwithintheacquisitiontime(tACQ)ifDCaccuracyisimportant.
Figure 3b. Analog Input Equivalent Circuit for Large Filter Capacitances
Figures4aand4bshowexamplesofinputfilteringforsingle-ended and differential inputs. For the single-endedcaseinFigure4a,a50Ωsourceresistoranda2000pFcapacitortogroundontheinputwilllimittheinputbandwidthto1.6MHz.HighqualitycapacitorsandresistorsshouldbeusedintheRCfiltersincethesecomponentscanadddistortion.NPOandsilvermicatypedielectriccapacitorshaveexcellentlinearity.Carbonsurfacemountresistorscangeneratedistortionfrom
2309 F04a
CH0
COM
LTC2309
REFCOMP
2000pF
0.1µF 10µF
50ΩANALOGINPUT
Figure 4a. Optional RC Input Filtering for Single-Ended Input
1000pF
2309 F04b
CH0
CH1
LTC2309
REFCOMP
1000pF
1000pF
0.1µF 10µF
50Ω
50Ω
DIFFERENTIALANALOGINPUTS
Figure 4b. Optional RC Input Filtering for Differential Inputs
LTC2309
2309fd
Total Harmonic Distortion (THD)
Total harmonic distortion (THD) is the ratio of theRMSsumofallharmonicsoftheinputsignaltothefundamentalitself.Theout-of-bandharmonicsaliasintothefrequencybandbetweenDCandhalfthesamplingfrequency(fSMPL/2).THDisexpressedas:
THD
V V V VV
N=+ + +
20 22
32
42 2
1log
...
where V1 is the RMS amplitude of the fundamentalfrequencyandV2throughVNaretheamplitudesofthesecondthroughNthharmonics.
Internal Reference
The LTC2309 has an on-chip, temperature compen-sated bandgap reference that is factory trimmed to2.5V(RefertoFigure6a).ItisinternallyconnectedtoareferenceamplifierandisavailableatVREF.VREFshouldbebypassedtoGNDwitha2.2μFceramiccapacitortominimizenoise.An8kresistorisinserieswiththeoutputsothatitcanbeeasilyoverdrivenbyanexternalrefer-enceifmoreaccuracyand/orlowerdriftarerequired,asshowninFigure6b.ThereferenceamplifiergainstheVREFvoltageby1.638to4.096VatREFCOMP.Tocompensatethereferenceamplifier,bypassREFCOMPwitha10μFceramiccapacitorinparallelwitha0.1μFceramic capacitor for best noise performance. The
Figure 6b. Using the LT®1790A-2.5 as an External Reference
FREQUENCY (kHz)0
–140
MAG
NITU
DE (d
B)
–120
–100
–80
0
–40
1 3 4 7
2309 G03
–20
–60
2 5 6
SNR = 73.4dBSINAD = 73.3dBTHD = –88dB
Figure 6c. Overdriving REFCOMP Using the LT1790A-4.096
0.1µF
0.1µF
10µF
2309 F06c
LT1790A-4.096VOUT
VIN
5V
VREF
LTC2309
GND
REFCOMP
LTC2309
2309fd
Internal Conversion Clock
The internal conversion clock is factory trimmed toachieveatypicalconversiontime(tCONV)of1.3μsanda maximum conversion time of 1.8μs over the fulloperatingtemperaturerange.
I2C Interface
TheLTC2309communicatesthroughanI2Cinterface.TheI2Cinterfaceisa2-wireopen-draininterfacesup-porting multiple devices and multiple masters on asinglebus.Theconnecteddevicescanonlypull theserialdataline(SDA)LOWandcanneverdriveitHIGH.SDAisrequiredtobeexternallyconnectedtothesup-plythroughapull-upresistor.WhenthedatalineisnotbeingdrivenLOW,itisHIGH.DataontheI2Cbuscanbetransferredatratesupto100kbits/sinthestandardmodeandupto400kbits/sinthefastmode.TheVDDpowershouldnotberemovedfromtheLTC2309whentheI2CbusisactivetoavoidloadingtheI2CbuslinesthroughtheinternalESDprotectiondiodes.
When the bus is in use, it stays busy if a repeatedSTART(Sr)isgeneratedinsteadofaSTOPcondition.TherepeatedSTARTtimingisfunctionallyidenticaltotheSTARTandisusedforwritingandreadingfromthedevicebeforetheinitiationofanewconversion.
AppLICAtIOns InFORMAtIOn
S
START Condition STOP Condition
P
2309 F07
SDA
SCL
SDA
SCL
Figure 7. Timing Diagrams of START and STOP Conditions
Data Transferring
After theSTARTcondition, theI2Cbus isbusyanddatatransfercanbeginbetweenthemasterandtheaddressedslave.Dataistransferredoverthebusingroups of nine bits, one byte followed by one ac-knowledge(ACK)bit.Themaster releases theSDAlineduringtheninthSCLclockcycle.TheslavedevicecanissueanACKbypullingSDALOWorissueaNotAcknowledge (NACK) by leaving the SDA line highimpedance(theexternalpull-upresistorwillholdthelinehigh).ChangeofdataonlyoccurswhiletheSCLlineisLOW.
Data Format
After a START condition, the master sends a 7-bitaddressfollowedbyaread/write(R/W)bit.TheR/Wbit is1forareadrequestand0forawriterequest.If the 7-bit address matches one of the LTC2309’s9pin-selectableaddresses,theADCisselected.When
a read operation, it acknowledges by pulling SDALOW and acts as a transmitter. The master/receivercanreadupto twobytes fromtheLTC2309.Afteracompletereadoperationof2bytes,aSTOPconditionisneededtoinitiateanewconversion.ThedevicewillNACKsubsequentreadoperationswhileaconversionisbeingperformed.
Thedataoutputstreamis16bitslongandisshiftedoutonthefallingedgesofSCL(seeFigure8a).ThefirstbitistheMSBandthe12thbitistheLSBoftheconversion result. The remaining four bits are zero.Figures14and15arethetransfercharacteristicsforthebipolarandunipolarmodes.DataisoutputontheSDAlinein2’scomplementformatforbipolarreadingsorinstraightbinaryforunipolarreadings.
1 2
A6SDA
START BYMASTER
ACK BYADC
ACK BYMASTER
NACK BYMASTER
STOPBY MASTER
CONVERSIONINITIATED
SCL
SCL(CONTINUED)
A5 A4 A3 A2 A1 A0 R/W
3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
1 2 3 4 5 6 7 8 9
2309 F08a
B11 B10
READ 1 BYTE
B9 B8 B7
MOST SIGNIFICANT DATA BYTE
B6 B5 B4
• • •
• • •
SDA(CONTINUED) • • •
• • •
B3 B2 B1 B0
LEAST SIGNIFICANT DATA BYTE
READ 1 BYTE
ADDRESS FRAME
Figure 8a. Timing Diagram for Reading from the LTC2309
LTC2309
2309fd
Input Data Format
WhentheLTC2309isaddressedforawriteoperation,itacknowledgesbypullingSDALOWduringtheLOWperiodbeforethe9thcycleandactsasareceiver.Themaster/transmittercanthensend1bytetoprogramthedevice.Theinputbyteconsistsofthe6-bitDINwordfollowedbytwobitsthatareignoredbytheADCandare considered don’t cares (X) (see Figure8b). TheinputbitsarelatchedontherisingedgeofSCLduringthewriteoperation.
After power-up, the ADC initiates an internal resetcyclewhichsetstheDINwordtoall0s(S/D=O/S=S0=S1=UNI=SLP=0).AwriteoperationmaybeperformedifthedefaultstateoftheADC’sconfigurationisnotdesired.Otherwise,theADCmustbeproperlyaddressedandfollowedbyaSTOPconditiontoinitiateaconversion.
Initiating a New Conversion
TheLTC2309awakensfromeithernaporsleepwhenproperlyaddressedforaread/writeoperation.ASTOPcommand may then be issued after performing theread/writeoperationtotriggeranewconversion.
In addition to the configurable addresses listed inTable2, theLTC2309alsocontainsaglobaladdress(1101011)whichmaybeusedforsynchronizingmul-tipleLTC2309sorotherI2CLTC230XSARADCs(seeSynchronizingMultipleLTC2309swithGlobalAddressCallsection).
TheADCentersnapmodeafteraconversioniscom-plete(tCONV)iftheSLPbitissettoalogic0.Thesup-plycurrentdecreasesto210μAinnapmodebetweenconversions, thereby reducing the average powerdissipationasthesampleratedecreases.Forexample,theLTC2309drawsanaverageof300µAata1kspssamplingrate.TheLTC2309keepsonlythereference(VREF)andreferencebuffer(REFCOMP)circuitryactivewheninnapmode.
Figure 11. Synchronous Multiple LTC2309s with a Global Address Call
S
CONVERSION SLEEP tREFWAKE CONVERSION
R/W ACK7-BIT ADDRESS P
2309 F12
Figure 12. Exiting Sleep Mode and Starting a New Conversion
LTC2309
2309fd
AppLICAtIOns InFORMAtIOnAcquisition
TheLTC2309beginsacquiringtheinputsignalatdif-ferentinstancesdependingonwhetherareadorwriteoperation isbeingperformed. If a readoperation isbeingperformed,acquisitionoftheinputsignalbeginsontherisingedgeofthe9thclockpulsefollowingtheaddressframe,asshowninFigure13a.
Ifawriteoperationisbeingperformed,acquisitionoftheinputsignalbeginsonthefallingedgeofthesixthclockcycleaftertheDINwordhasbeenshiftedin,asshown in Figure 13b. The LTC2309 will acquire thesignalfromtheinputchannelthatwasmostrecentlyprogrammedbytheDINword.Aminimumof240nsisrequiredtoacquiretheinputsignalbeforeinitiatinganewconversion.
1 2
A6SDA
SCL
A5 A4 A3 A2 A1 A0 R/W
3 4 5 6 7 8 9 1 2
B11
ACQUISITION BEGINS
tACQ2309 F13a
B10
1 2
A2 A1 A0 R/WSDA
SCL
S/D O/S S1 S0 UNI X X
3 4 55 6 7 8 9 6 7 8 9
ACQUISITION BEGINS
tACQ 2309 F13b
SLP
Figure 13a. Timing Diagram Showing Acquisition During a Read Operation
Figure 13b. Timing Diagram Showing Acquisition During a Write Operation
INPUT VOLTAGE (V)
0V
OUTP
UT C
ODE
(TW
O’S
COM
PLEM
ENT)
–1 LSB
2309 F14
011...111
011...110
000...001
000...000
100...000
100...001
111...110
1LSB
BIPOLARZERO
111...111
FS/2 – 1LSB–FS/2
FS = 4.096V1LSB = FS/212
1LSB = 1mV
INPUT VOLTAGE (V)
OUTP
UT C
ODE
2309 F15
111...111
111...110
100...001
100...000
000...000
000...001
011...110
011...111
FS – 1LSB0V
UNIPOLARZERO
FS = 4.096V1LSB = FS/212
1LSB = 1mV
Figure 14. Bipolar Transfer Characteristics (2’s Complement) Figure 15. Unipolar Transfer Characteristics (Straight Binary)
andVDDshouldbebypassedtothegroundplaneasclosetothepinaspossible.Maintainingalowimpedancepathfor the common return of these bypass capacitors isessential to the lownoiseoperationof theADC.Thesetracesshouldbeaswideaspossible.SeeFigures16a-eforasuggestedlayout.
NOTE:1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED2. DRAWING NOT TO SCALE3. ALL DIMENSIONS ARE IN MILLIMETERS4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT5. EXPOSED PAD SHALL BE SOLDER PLATED6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
PIN 1TOP MARK(NOTE 6)
0.40 ± 0.10
2423
1
2
BOTTOM VIEW—EXPOSED PAD
2.45 ± 0.10(4-SIDES)
0.75 ± 0.05 R = 0.115TYP
0.25 ± 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UF24) QFN 0105
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.70 ±0.05
0.25 ±0.050.50 BSC
2.45 ± 0.05(4 SIDES)3.10 ± 0.05
4.50 ± 0.05
PACKAGE OUTLINE
PIN 1 NOTCHR = 0.20 TYP OR 0.35 45° CHAMFER
LTC2309
2309fd
F Package20-Lead Plastic TSSOP (4.4mm)(ReferenceLTCDWG#05-08-1650)
F20 TSSOP 0204
0.09 – 0.20(.0035 – .0079)
0° – 8°
0.25REF
0.50 – 0.75(.020 – .030)
4.30 – 4.50**(.169 – .177)
1 3 4 5 6 7 8 9 10
111214 13
6.40 – 6.60*(.252 – .260)
20 19 18 17 16 15
1.10(.0433)
MAX
0.05 – 0.15(.002 – .006)
0.65(.0256)
BSC
6.40(.252)BSC
0.19 – 0.30(.0075 – .0118)
TYP
2
MILLIMETERS(INCHES)
DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDEDIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEADFLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
*
**
NOTE:1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
RECOMMENDED SOLDER PAD LAYOUT
0.45 ±0.05 0.65 BSC
4.50 ±0.106.60 ±0.10
1.05 ±0.10
pACKAGe DesCRIptIOn
LTC2309
2309fd
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Linear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417(408)432-1900FAX: (408)434-0507www.linear.com LINEAR TECHNOLOGY CORPORATION 2008