LTC2241-12 - 12-Bit, 210Msps ADC - Analog

LTC2241-12

1224112fc

Typical applicaTion

FeaTures

applicaTions

DescripTion

12-Bit, 210Msps ADC

The LTC®2241-12 is a 210Msps, sampling 12-bit A/D con-verter designed for digitizing high frequency, wide dynamic range signals. The LTC2241-12 is perfect for demanding communications applications with AC performance that includes 65.5dB SNR and 78dB SFDR. Ultralow jitter of 95fsRMS allows IF undersampling with excellent noise performance.

DC specs include ±0.7LSB INL (typ), ±0.4LSB DNL (typ) and no missing codes over temperature.

The digital outputs can be either differential LVDS, or single-ended CMOS. There are three format options for the CMOS outputs: a single bus running at the full data rate or two demultiplexed buses running at half data rate with either interleaved or simultaneous update. A separate output power supply allows the CMOS output swing to range from 0.5V to 2.625V.

The ENC+ and ENC– inputs may be driven differentially or single ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional clock duty cycle stabilizer allows high performance over a wide range of clock duty cycles.

SFDR vs Input Frequency

n Sample Rate: 210Mspsn 65.5dB SNRn 78dB SFDRn 1.2GHz Full Power Bandwidth S/Hn Single 2.5V Supplyn Low Power Dissipation: 585mWn LVDS, CMOS, or Demultiplexed CMOS Outputsn Selectable Input Ranges: ±0.5V or ±1Vn No Missing Codesn Optional Clock Duty Cycle Stabilizern Shutdown and Nap Modesn Data Ready Output Clockn Pin Compatible Family 250Msps: LTC2242-12 (12-Bit), LTC2242-10 (10-Bit) 210Msps: LTC2241-12 (12-Bit), LTC2241-10 (10-Bit) 170Msps: LTC2240-12 (12-Bit), LTC2240-10 (10-Bit) 185Msps: LTC2220-1 (12-Bit)* 170Msps: LTC2220 (12-Bit), LTC2230 (10-Bit)* 135Msps: LTC2221 (12-Bit), LTC2231 (10-Bit)*n 64-Pin 9mm × 9mm QFN Package

n Wireless and Wired Broadband Communicationn Cable Head-End Systemsn Power Amplifier Linearizationn Communications Test Equipment

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. *LTC2220-1, LTC2220, LTC2221, LTC2230, LTC2231 are 3.3V parts.

–

+INPUT

S/HCORRECTION

LOGICOUTPUTDRIVERS

12-BITPIPELINEDADC CORE

CLOCK/DUTYCYCLE

CONTROL

FLEXIBLEREFERENCE

D11•••

D0

ENCODEINPUT

REFH

REFL

ANALOGINPUT

224112 TA01

CMOSORLVDS

0.5VTO 2.625V

2.5V

VDD

OVDD

OGND

INPUT FREQUENCY (MHz)0

SFDR

(dBF

S)

70

80

85

800

224112 G11

60

50

65

75

55

45

40200100 400300 600 700 900500 1000

1V RANGE

2V RANGE

LTC2241-12

2224112fc

absoluTe MaxiMuM raTingsSupply Voltage (VDD) ...............................................2.8VDigital Output Ground Voltage (OGND) ........ –0.3V to 1VAnalog Input Voltage (Note 3) ...... –0.3V to (VDD + 0.3V)Digital Input Voltage..................... –0.3V to (VDD + 0.3V)Digital Output Voltage ................ –0.3V to (OVDD + 0.3V)

OVDD = VDD (Notes 1, 2)

TOP VIEW

UP PACKAGE64-LEAD (9mm × 9mm) PLASTIC QFN

EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCBTJMAX = 150°C, θJA = 20°C/W

AIN+ 1

AIN+ 2

AIN– 3

AIN– 4

REFHA 5REFHA 6REFLB 7REFLB 8REFHB 9

REFHB 10REFLA 11REFLA 12

VDD 13VDD 14VDD 15GND 16

48 D9+/DA6 47 D9–/DA5 46 D8+/DA4 45 D8–/DA344 D7+/DA2 43 D7–/DA142 OVDD41 OGND40 D6+/DA0 39 D6–/CLKOUTA38 D5+/CLKOUTB37 D5–/OFB36 CLKOUT+/DB1135 CLKOUT–/DB1034 OVDD33 OGND

64 G

ND63

VDD

62 V

DD61

GND

60 V

CM59

SEN

SE58

MOD

E57

LVD

S56

OF+ /O

FA55

OF– /D

A11

54 D

11+ /D

A10

53 D

11– /D

A952

D10

+ /DA8

51 D

10– /D

A750

OGN

D49

OV D

D

ENC+ 1

7EN

C– 18

SHDN

19

OE 2

0DO

– /DB0

21

DO+ /D

B1 2

2D1

– /DB2

23

D1+ /D

B3 2

4OG

ND 2

5OV

DD 2

6D2

– /DB4

27

D2+ /D

B5 2

8D3

– /DB6

29

D3+ /D

B7 3

0D4

– /DB8

31

D4+ /D

B9 3

2

65

pin conFiguraTion

orDer inForMaTionLEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC2241CUP-12#PBF LTC2241CUP-12#TRPBF LTC2241UP-12 64-Lead (9mm × 9mm) Plastic QFN 0°C to 70°C

LTC2241IUP-12#PBF LTC2241IUP-12#TRPBF LTC2241UP-12 64-Lead (9mm × 9mm) Plastic QFN –40°C to 85°C

LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC2241CUP-12 LTC2241CUP-12#TR LTC2241UP-12 64-Lead (9mm × 9mm) Plastic QFN 0°C to 70°C

LTC2241IUP-12 LTC2241IUP-12#TR LTC2241UP-12 64-Lead (9mm × 9mm) Plastic QFN –40°C to 85°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *Temperature grades are identified by a label on the shipping container.For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

Power Dissipation .............................................1500mWOperating Temperature Range LTC2241C-12 ............................................ 0°C to 70°C LTC2241I-12 .........................................–40°C to 85°CStorage Temperature Range .................. –65°C to 150°C

LTC2241-12

3224112fc

converTer characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)PARAMETER CONDITIONS MIN TYP MAX UNITS

Resolution (No Missing Codes) 12 Bits

Integral Linearity Error Differential Analog Input (Note 5) –2.3 ±0.7 2.3 LSB

Differential Linearity Error Differential Analog Input –1 ±0.4 1 LSB

Offset Error (Note 6) –15 ±5 15 mV

Gain Error External Reference –3.4 ±0.7 3.4 %FS

Offset Drift ±10 µV/C

Full-Scale Drift Internal Reference External Reference

±60 ±45

ppm/C ppm/C

Transition Noise SENSE = 1V 0.74 LSBRMS

analog inpuT The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIN Analog Input Range (AIN+ – AIN

–) 2.375V < VDD < 2.625V (Note 7) ±0.5 to ±1 V

VIN, CM Analog Input Common Mode (AIN+ + AIN

–)/2 Differential Input (Note 7) 1.2 1.25 1.3 V

IIN Analog Input Leakage Current 0 < AIN+, AIN

– < VDD –1 1 µA

ISENSE SENSE Input Leakage 0V < SENSE < 1V –1 1 µA

IMODE MODE Pin Pull-Down Current to GND 7 µA

ILVDS LVDS Pin Pull-Down Current to GND 7 µA

tAP Sample and Hold Acquisition Delay Time 0.4 ns

tJITTER Sample and Hold Acquisition Delay Time Jitter 95 fsRMS

Full Power Bandwidth Figure 8 Test Circuit 1200 MHz

DynaMic accuracy The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

SNR Signal-to-Noise Ratio (Note 10) 10MHz Input 65.5 dB

70MHz Input l 64 65.4 dB

140MHz Input 65.4 dB


SFDR Spurious Free Dynamic Range 2nd or 3rd Harmonic (Note 11)

10MHz Input 78 dB

70MHz Input l 65 74 dB

140MHz Input 73 dB

240MHz Input 72 dB

Spurious Free Dynamic Range 4th Harmonic or Higher (Note 11)

10MHz Input 87 dB

70MHz Input l 74 87 dB

140MHz Input 87 dB

240MHz Input 87 dB

S/(N+D) Signal-to-Noise Plus Distortion Ratio (Note 12)

10MHz Input 65.4 dB

70MHz Input l 62.1 65.2 dB



IMD Intermodulation Distortion fIN1 = 135MHz, fIN2 = 140MHz 81 dBc

LTC2241-12

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inTernal reFerence characTerisTics (Note 4)

PARAMETER CONDITIONS MIN TYP MAX UNITS

VCM Output Voltage IOUT = 0 1.225 1.25 1.275 V

VCM Output Tempco ±35 ppm/°C

VCM Line Regulation 2.375V < VDD < 2.625V 3 mV/V

VCM Output Resistance –1mA < IOUT < 1mA 2 Ω

DigiTal inpuTs anD DigiTal ouTpuTs The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)


ENCODE INPUTS (ENC+, ENC–)

VID Differential Input Voltage (Note 7) 0.2 V

VICM Common Mode Input Voltage Internally Set Externally Set (Note 7)

1.2

1.5 1.5

2.0

V V

RIN Input Resistance 4.8 kΩ

CIN Input Capacitance (Note 7) 2 pF

LOGIC INPUTS (OE, SHDN)

VIH High Level Input Voltage VDD = 2.5V 1.7 V

VIL Low Level Input Voltage VDD = 2.5V 0.7 V

IIN Input Current VIN = 0V to VDD –10 10 µA

CIN Input Capacitance (Note 7) 3 pF

LOGIC OUTPUTS (CMOS MODE)

OVDD = 2.5V

COZ Hi-Z Output Capacitance OE = High (Note 7) 3 pF

ISOURCE Output Source Current VOUT = 0V 37 mA

ISINK Output Sink Current VOUT = 2.5V 23 mA

VOH High Level Output Voltage IO = –10µA IO = –500µA

2.495 2.45

V V

VOL Low Level Output Voltage IO = 10µA IO = 500µA

0.005 0.07

V V

OVDD = 1.8V

VOH High Level Output Voltage IO = –500µA 1.75 V

VOL Low Level Output Voltage IO = 500µA 0.07 V

LOGIC OUTPUTS (LVDS MODE)

VOD Differential Output Voltage 100Ω Differential Load 247 350 454 mV

VOS Output Common Mode Voltage 100Ω Differential Load 1.125 1.250 1.375 V

LTC2241-12

5224112fc

power requireMenTs


V DD Analog Supply Voltage (Note 8) 2.375 2.5 2.625 V

PSLEEP Sleep Mode Power SHDN = High, OE = High, No CLK 1 mW

PNAP Nap Mode Power SHDN = High, OE = Low, No CLK 28 mW

LVDS OUTPUT MODE

OVDD Output Supply Voltage (Note 8) 2.375 2.5 2.625 V

IVDD Analog Supply Current 226 252 mA

IOVDD Output Supply Current 58 70 mA

PDISS Power Dissipation 710 805 mW

CMOS OUTPUT MODE

OVDD Output Supply Voltage (Note 8) 0.5 2.5 2.625 V

IVDD Analog Supply Current (Note 7) 226 252 mA

PDISS Power Dissipation 585 mW

The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9)

TiMing characTerisTics The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)


fS Sampling Frequency (Note 8) 1 210 MHz

tL ENC Low Time (Note 7) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On

2.26 1.5

2.38 2.38

500 500

ns ns

tH ENC High Time (Note 7) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On

2.26 1.5

2.38 2.38

500 500

ns ns

tAP Sample-and-Hold Aperture Delay 0.4 ns

tOE Output Enable Delay (Note 7) 5 10 ns

LVDS OUTPUT MODE

tD ENC to DATA Delay (Note 7) 1 1.7 2.8 ns

tC ENC to CLKOUT Delay (Note 7) 1 1.7 2.8 ns

DATA to CLKOUT Skew (tC – tD) (Note 7) –0.6 0 0.6 ns

Rise Time 0.5 ns

Fall Time 0.5 ns

Pipeline Latency 5 Cycles

CMOS OUTPUT MODE

tD ENC to DATA Delay (Note 7) 1 1.7 2.8 ns

tC ENC to CLKOUT Delay (Note 7) 1 1.7 2.8 ns

DATA to CLKOUT Skew (tC – tD) (Note 7) –0.6 0 0.6 ns

Pipeline Latency

Full Rate CMOS 5 Cycles

Demuxed Interleaved 5 Cycles

Demuxed Simultaneous 5 and 6 Cycles

LTC2241-12

6224112fc

elecTrical characTerisTicsNote 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.Note 2: All voltage values are with respect to ground with GND and OGND wired together (unless otherwise noted).Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup.Note 4: VDD = 2.5V, fSAMPLE = 210MHz, LVDS outputs, differential ENC+/ENC– = 2VP-P sine wave, input range = 2VP-P with differential drive, unless otherwise noted.Note 5: Integral nonlinearity is defined as the deviation of a code from a “best straight line” fit to the transfer curve. The deviation is measured from the center of the quantization band.

Typical perForMance characTerisTics

Note 6: Offset error is the offset voltage measured from –0.5 LSB when the output code flickers between 0000 0000 0000 and 1111 1111 1111 in 2’s complement output mode.Note 7: Guaranteed by design, not subject to test.Note 8: Recommended operating conditions.Note 9: VDD = 2.5V, fSAMPLE = 210MHz, differential ENC+/ENC– = 2VP-P sine wave, input range = 1VP-P with differential drive, output CLOAD = 5pF.Note 10: SNR minimum and typical values are for LVDS mode. Typical values for CMOS mode are typically 0.3dB lower.Note 11: SFDR minimum values are for LVDS mode. Typical values are for both LVDS and CMOS modes.Note 12: SINAD minimum and typical values are for LVDS mode. Typical values for CMOS mode are typically 0.3dB lower.

Integral Nonlinearity

Differential Nonlinearity

8192 Point FFT, fIN = 5MHz, –1dB, 2V Range, LVDS Mode

(TA = 25°C unless otherwise noted, Note 4)

OUTPUT CODE0

–1.0

INL

(LSB

)

–0.8

–0.4

–0.2

0

1.0

0.4

1024 2048

224112 G01

–0.6

0.6

0.8

0.2

3072 4096OUTPUT CODE

0–1.0

DNL

(LSB

)

–0.8

–0.4

–0.2

0

1.0

0.4

1024 2048

224112 G02

–0.6

0.6

0.8

0.2

3072 4096FREQUENCY (MHz)

0

AMPL

ITUD

E (d

B)

–80

–20

–10

0

20 40 60 80

224112 G03

–100

–40

–60

–90

–30

–110

–50

–70

100

LTC2241-12

7224112fc

Typical perForMance characTerisTics





8192 Point FFT, fIN = 1GHz, –1dB, 1V Range, LVDS Mode

8192 Point 2-Tone FFT, fIN = 135MHz and 140MHz, –1dB, 2V Range, LVDS Mode

SNR vs Input Frequency, –1dB, LVDS Mode

SFDR (HD2 and HD3) vs Input Frequency, –1dB, LVDS Mode

SFDR (HD4+) vs Input Frequency, –1dB, LVDS Mode


FREQUENCY (MHz)0

AMPL

ITUD

E (d

B)

–80

–20

–10

0

20 40 60 80

224112 G04

–100

–40

–60

–90

–30

–110

–50

–70

100FREQUENCY (MHz)

0

AMPL

ITUD

E (d

B)

–80

–20

–10

0

20 40 60 80

224112 G05

–100

–40

–60

–90

–30

–110

–50

–70

100FREQUENCY (MHz)

0

AMPL

ITUD

E (d

B)

–80

–20

–10

0

20 40 60 80

224112 G06

–100

–40

–60

–90

–30

–110

–50

–70

100

FREQUENCY (MHz)0

AMPL

ITUD

E (d

B)

–80

–20

–10

0

20 40 60 80

224112 G07

–100

–40

–60

–90

–30

–110

–50

–70

100FREQUENCY (MHz)

0

AMPL

ITUD

E (d

B)

–80

–20

–10

0

20 40 60 80

224112 G08

–100

–40

–60

–90

–30

–110

–50

–70

100FREQUENCY (MHz)

0

AMPL

ITUD

E (d

B)

–80

–20

–10

0

20 40 60 80

224112 G09

–100

–40

–60

–90

–30

–110

–50

–70

100


58

SNR

(dBF

S)

59

61

62

63

600 700 800 900

67

224112 G10

60

100 200 300 400 500 1000

64

65

66

1V RANGE

2V RANGE


SFDR

(dBF

S)

70

80

85

800

224112 G11

60

50

65

75

55

45

40200100 400300 600 700 900500 1000

1V RANGE

2V RANGE


60

SFDR

(dBF

S)

65

75

80

85

95

100 500 700

224112 G12

70

90

400 9001000200 300 600 800

1V RANGE

2V RANGE

LTC2241-12

8224112fc

Typical perForMance characTerisTicsSFDR and SNR vs Sample Rate, 2V Range, fIN = 30MHz, –1dB, LVDS Mode

SFDR vs Input Level, fIN = 70MHz, 2V Range

SNR vs SENSE, fIN = 5MHz, –1dB

IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB

IOVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB


SAMPLE RATE (Msps)0

95

90

85

80

75

70

65

60

50

55

150

SFDR

SNR

224112 G13

50 100 200 250

SFDR

AND

SNR

(dBF

S)

INPUT LEVEL (dBFS)–50

0

SFDR

(dBc

AND

dFB

S)

10

30

40

50

90

70

–40 –20 –10

224112 G14

20

80

60

–30

dBFS

dBc

0SENSE PIN (V)

0.5

64

65

66

0.9

224112 G15

63

62

0.6 0.7 0.8 1

61

60

59

SNR

(dBF

S)

SAMPLE RATE (Msps)0

I VDD

(mA)

190

200

210

150 250

224112 G16

180

17050 100 200

220

230

240

2V RANGE

1V RANGE

SAMPLE RATE (Msps)0

0

I OVD

D (m

A)

10

20

30

40

60

50 100 150 200

224112 G17

250

50

CMOS OUTPUTSOVDD = 1.8V

LVDS OUTPUTSOVDD = 2.5V

LTC2241-12

9224112fc

pin FuncTions(CMOS Mode)AIN

+ (Pins 1, 2): Positive Differential Analog Input.AIN

– (Pins 3, 4): Negative Differential Analog Input.REFHA (Pins 5, 6): ADC High Reference. Bypass to Pins 7, 8 with 0.1µF ceramic chip capacitor, to Pins 11, 12 with a 2.2µF ceramic capacitor and to ground with 1µF ceramic capacitor.REFLB (Pins 7, 8): ADC Low Reference. Bypass to Pins 5, 6 with 0.1µF ceramic chip capacitor. Do not connect to Pins 11, 12.REFHB (Pins 9, 10): ADC High Reference. Bypass to Pins 11, 12 with 0.1µF ceramic chip capacitor. Do not connect to Pins 5, 6.REFLA (Pins 11, 12): ADC Low Reference. Bypass to Pins 9, 10 with 0.1µF ceramic chip capacitor, to Pins 5, 6 with a 2.2µF ceramic capacitor and to ground with 1µF ceramic capacitor.VDD (Pins 13, 14, 15, 62, 63): 2.5V Supply. Bypass to GND with 0.1µF ceramic chip capacitors.GND (Pins 16, 61, 64): ADC Power Ground. ENC+ (Pin 17): Encode Input. Conversion starts on the positive edge.ENC– (Pin 18): Encode Complement Input. Conversion starts on the negative edge. Bypass to ground with 0.1µF ceramic for single-ended encode signal.SHDN (Pin 19): Shutdown Mode Selection Pin. Connecting SHDN to GND and OE to GND results in normal operation with the outputs enabled. Connecting SHDN to GND and OE to VDD results in normal operation with the outputs at high impedance. Connecting SHDN to VDD and OE to GND results in nap mode with the outputs at high impedance. Connecting SHDN to VDD and OE to VDD results in sleep mode with the outputs at high impedance.OE (Pin 20): Output Enable Pin. Refer to SHDN pin function.DB0 - DB11 (Pins 21, 22, 23, 24, 27, 28, 29, 30, 31, 32, 35, 36): Digital Outputs, B Bus. DB11 is the MSB. At high impedance in full rate CMOS mode.OGND (Pins 25, 33, 41, 50): Output Driver Ground.OVDD (Pins 26, 34, 42, 49): Positive Supply for the Out-put Drivers. Bypass to ground with 0.1µF ceramic chip capacitor.

OFB (Pin 37): Over/Under Flow Output for B Bus. High when an over or under flow has occurred. At high imped-ance in full rate CMOS mode.CLKOUTB (Pin 38): Data Valid Output for B Bus. In demux mode with interleaved update, latch B bus data on the fall-ing edge of CLKOUTB. In demux mode with simultaneous update, latch B bus data on the rising edge of CLKOUTB. This pin does not become high impedance in full rate CMOS mode.CLKOUTA (Pin 39): Data Valid Output for A Bus. Latch A bus data on the falling edge of CLKOUTA. DA0 - DA11 (Pins 40, 43, 44, 45, 46, 47, 48, 51, 52, 53, 54, 55): Digital Outputs, A Bus. DA11 is the MSB.OFA (Pin 56): Over/Under Flow Output for A Bus. High when an over or under flow has occurred.LVDS (Pin 57): Output Mode Selection Pin. Connecting LVDS to 0V selects full rate CMOS mode. Connecting LVDS to 1/3VDD selects demux CMOS mode with simultaneous update. Connecting LVDS to 2/3VDD selects demux CMOS mode with interleaved update. Connecting LVDS to VDD selects LVDS mode.MODE (Pin 58): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to 0V selects offset binary output format and turns the clock duty cycle stabilizer off. Connecting MODE to 1/3VDD selects offset binary output format and turns the clock duty cycle stabilizer on. Connecting MODE to 2/3VDD selects 2’s complement output format and turns the clock duty cycle stabilizer on. Connecting MODE to VDD selects 2’s complement output format and turns the clock duty cycle stabilizer off.SENSE (Pin 59): Reference Programming Pin. Connecting SENSE to VCM selects the internal reference and a ±0.5V input range. Connecting SENSE to VDD selects the internal reference and a ±1V input range. An external reference greater than 0.5V and less than 1V applied to SENSE selects an input range of ±VSENSE. ±1V is the largest valid input range.VCM (Pin 60): 1.25V Output and Input Common Mode Bias. Bypass to ground with 2.2µF ceramic chip capacitor.GND (Exposed Pad) (Pin 65): ADC Power Ground. The exposed pad on the bottom of the package needs to be soldered to ground.

LTC2241-12

10224112fc

pin FuncTions(LVDS Mode)AIN+ (Pins 1, 2): Positive Differential Analog Input.AIN– (Pins 3, 4): Negative Differential Analog Input.REFHA (Pins 5, 6): ADC High Reference. Bypass to Pins 7, 8 with 0.1µF ceramic chip capacitor, to Pins 11, 12 with a 2.2µF ceramic capacitor and to ground with 1µF ceramic capacitor.REFLB (Pins 7, 8): ADC Low Reference. Bypass to Pins 5, 6 with 0.1µF ceramic chip capacitor. Do not connect to Pins 11, 12.REFHB (Pins 9, 10): ADC High Reference. Bypass to Pins 11, 12 with 0.1µF ceramic chip capacitor. Do not connect to Pins 5, 6.REFLA (Pins 11, 12): ADC Low Reference. Bypass to Pins 9, 10 with 0.1µF ceramic chip capacitor, to Pins 5, 6 with a 2.2µF ceramic capacitor and to ground with 1µF ceramic capacitor.VDD (Pins 13, 14, 15, 62, 63): 2.5V Supply. Bypass to GND with 0.1µF ceramic chip capacitors.GND (Pins 16, 61, 64): ADC Power Ground.ENC+ (Pin 17): Encode Input. Conversion starts on the positive edge.ENC– (Pin 18): Encode Complement Input. Conversion starts on the negative edge. Bypass to ground with 0.1µF ceramic for single-ended encode signal.SHDN (Pin 19): Shutdown Mode Selection Pin. Connecting SHDN to GND and OE to GND results in normal operation with the outputs enabled. Connecting SHDN to GND and OE to VDD results in normal operation with the outputs at high impedance. Connecting SHDN to VDD and OE to GND results in nap mode with the outputs at high impedance. Connecting SHDN to VDD and OE to VDD results in sleep mode with the outputs at high impedance.OE (Pin 20): Output Enable Pin. Refer to SHDN pin function.D0–/D0+ to D11–/D11+ (Pins 21, 22, 23, 24, 27, 28, 29, 30, 31, 32, 37, 38, 39, 40, 43, 44, 45, 46, 47, 48, 51, 52, 53, 54): LVDS Digital Outputs. All LVDS outputs re-quire differential 100Ω termination resistors at the LVDS receiver. D11–/D11+ is the MSB.

OGND (Pins 25, 33, 41, 50): Output Driver Ground.OVDD (Pins 26, 34, 42, 49): Positive Supply for the Out-put Drivers. Bypass to ground with 0.1µF ceramic chip capacitor.CLKOUT–/CLKOUT+ (Pins 35 to 36): LVDS Data Valid Output. Latch data on rising edge of CLKOUT–, falling edge of CLKOUT+.OF–/OF+ (Pins 55 to 56): LVDS Over/Under Flow Output. High when an over or under flow has occurred.LVDS (Pin 57): Output Mode Selection Pin. Connecting LVDS to 0V selects full rate CMOS mode. Connecting LVDS to 1/3VDD selects demux CMOS mode with simultaneous update. Connecting LVDS to 2/3VDD selects demux CMOS mode with interleaved update. Connecting LVDS to VDD selects LVDS mode.MODE (Pin 58): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to 0V selects offset binary output format and turns the clock duty cycle stabilizer off. Connecting MODE to 1/3VDD selects offset binary output format and turns the clock duty cycle stabilizer on. Connecting MODE to 2/3VDD selects 2’s complement output format and turns the clock duty cycle stabilizer on. Connecting MODE to VDD selects 2’s complement output format and turns the clock duty cycle stabilizer off.SENSE (Pin 59): Reference Programming Pin. Connecting SENSE to VCM selects the internal reference and a ±0.5V input range. Connecting SENSE to VDD selects the internal reference and a ±1V input range. An external reference greater than 0.5V and less than 1V applied to SENSE selects an input range of ±VSENSE. ±1V is the largest valid input range.VCM (Pin 60): 1.25V Output and Input Common Mode Bias. Bypass to ground with 2.2µF ceramic chip capacitor.GND (Exposed Pad) (Pin 65): ADC Power Ground. The exposed pad on the bottom of the package needs to be soldered to ground.

LTC2241-12

11224112fc

FuncTional block DiagraM

Figure 1. Functional Block Diagram

DIFFREFAMP

REFBUF

2.2μF

1μF

0.1μF 0.1μF

1μF

INTERNAL CLOCK SIGNALSREFH REFL

DIFFERENTIALINPUT

LOW JITTERCLOCKDRIVER

RANGESELECT

1.25VREFERENCE

FIRST PIPELINEDADC STAGE

FIFTH PIPELINEDADC STAGE

FOURTH PIPELINEDADC STAGE

SECOND PIPELINEDADC STAGE

ENC+

REFHAREFLB REFLA REFHB

ENC–

SHIFT REGISTERAND CORRECTION

OEM0DEOGND

OF

OVDD

D11

D0

CLKOUT

224112 F01

INPUTS/H

SENSE

VCM

AIN–

AIN+

2.2μF

THIRD PIPELINEDADC STAGE

OUTPUTDRIVERS

CONTROLLOGIC

LVDS SHDN

•••

+–

+–

+–+–

VDD

GND

LTC2241-12

12224112fc

TiMing DiagraMsLVDS Output Mode Timing

All Outputs Are Differential and Have LVDS Levels

Full-Rate CMOS Output Mode TimingAll Outputs Are Single-Ended and Have CMOS Levels

tH

tD

tC

tL

N – 5 N – 4 N – 3 N – 2 N – 1

tAP

N + 1

N + 2 N + 4

N + 3NANALOG

INPUT

ENC–

ENC+

CLKOUT–

CLKOUT+

D0-D11, OF

224112 TD01

tAP

N + 1

N + 2 N + 4

N + 3NANALOG

INPUT

tH

tD

tC

tL

N – 5 N – 4 N – 3 N – 2 N – 1

ENC–

ENC+

CLKOUTB

CLKOUTA

DA0-DA11, OFA

DB0-DB11, OFB

224112 TD02

HIGH IMPEDANCE

LTC2241-12

13224112fc

TiMing DiagraMsDemultiplexed CMOS Outputs with Interleaved UpdateAll Outputs Are Single-Ended and Have CMOS Levels

Demultiplexed CMOS Outputs with Simultaneous UpdateAll Outputs Are Single-Ended and Have CMOS Levels

tH

tD

tC tC

tD

tL

N – 5 N – 3 N – 1

N – 6 N – 4 N – 2

ENC–

ENC+

CLKOUTB

CLKOUTA

DA0-DA11, OFA

DB0-DB11, OFB

224112 TD03

tAP

N + 1

N + 2 N + 4

N + 3NANALOG

INPUT

tH

tD

tC

tD

tL

N – 6 N – 4 N – 2

N – 5 N – 3 N – 1

ENC–

ENC+

CLKOUTB

CLKOUTA

DA0-DA11, OFA

DB0-DB11, OFB

224112 TD04

tAP

N + 1

N + 2 N + 4

N + 3NANALOG

INPUT

LTC2241-12

14224112fc

applicaTions inForMaTionDYNAMIC PERFORMANCE

Signal-to-Noise Plus Distortion Ratio

The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamen-tal input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency.

Signal-to-Noise Ratio

The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the first five harmonics and DC.

Total Harmonic Distortion

Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as:

THD= 20Log V22 + V32 + V42 + ...Vn2( )/V1

where V1 is the RMS amplitude of the fundamental fre-quency and V2 through Vn are the amplitudes of the second through nth harmonics. The THD calculated in this data sheet uses all the harmonics up to the fifth.

Intermodulation Distortion

If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency.

If two pure sine waves of frequencies fa and fb are ap-plied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. The 3rd order intermodulation products are

2fa + fb, 2fb + fa, 2fa – fb and 2fb – fa. The intermodula-tion distortion is defined as the ratio of the RMS value of either input tone to the RMS value of the largest 3rd order intermodulation product.

Spurious Free Dynamic Range (SFDR)

Spurious free dynamic range is the peak harmonic or spuri-ous noise that is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full scale input signal.

Full Power Bandwidth

The full power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal.

Aperture Delay Time

The time from when a rising ENC+ equals the ENC– voltage to the instant that the input signal is held by the sample and hold circuit.

Aperture Delay Jitter

The variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal to noise ratio due to the jitter alone will be:

SNRJITTER = –20log (2π • fIN • tJITTER)

CONVERTER OPERATION

As shown in Figure 1, the LTC2241-12 is a CMOS pipelined multi-step converter. The converter has five pipelined ADC stages; a sampled analog input will result in a digitized value five cycles later (see the Timing Diagram section). For optimal performance the analog inputs should be driven differentially. The encode input is differential for improved common mode noise immunity. The LTC2241-12 has two phases of operation, determined by the state of the dif-ferential ENC+/ENC– input pins. For brevity, the text will refer to ENC+ greater than ENC– as ENC high and ENC+ less than ENC– as ENC low.

LTC2241-12

15224112fc

applicaTions inForMaTionEach pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage residue amplifier. In operation, the ADC quantizes the input to the stage and the quantized value is subtracted from the input by the DAC to produce a residue. The residue is amplified and output by the residue amplifier. Successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and vice versa.

When ENC is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the “Input S/H” shown in the block diagram. At the instant that ENC transitions from low to high, the sampled input is held. While ENC is high, the held input voltage is buffered by the S/H amplifier which drives the first pipelined ADC stage. The first stage acquires the output of the S/H dur-ing this high phase of ENC. When ENC goes back low, the first stage produces its residue which is acquired by the second stage. At the same time, the input S/H goes back to acquiring the analog input. When ENC goes back high, the second stage produces its residue which is acquired by the third stage. An identical process is repeated for the third and fourth stages, resulting in a fourth stage residue that is sent to the fifth stage ADC for final evaluation.

Each ADC stage following the first has additional range to accommodate flash and amplifier offset errors. Results from all of the ADC stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer.

SAMPLE/HOLD OPERATION AND INPUT DRIVE

Sample/Hold Operation

Figure 2 shows an equivalent circuit for the LTC2241-12 CMOS differential sample-and-hold. The analog inputs are connected to the sampling capacitors (CSAMPLE) through NMOS transistors. The capacitors shown attached to each input (CPARASITIC) are the summation of all other capacitance associated with each input.

During the sample phase when ENC is low, the transistors connect the analog inputs to the sampling capacitors and they charge to, and track the differential input voltage. When ENC transitions from low to high, the sampled input

voltage is held on the sampling capacitors. During the hold phase when ENC is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the ADC core for processing. As ENC transitions from high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. If the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. If the input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen.

Common Mode Bias

For optimal performance the analog inputs should be driven differentially. Each input should swing ±0.5V for the 2V range or ±0.25V for the 1V range, around a common mode voltage of 1.25V. The VCM output pin (Pin 60) may be used to provide the common mode bias level. VCM can be tied directly to the center tap of a transformer to set the DC input level or as a reference level to an op amp

Figure 2. Equivalent Input Circuit

CSAMPLE2pFRON

14Ω

RON14Ω

VDD

VDD

LTC2241-12

AIN+

224112 F02

CSAMPLE2pF

VDD

AIN–

ENC–

ENC+

1.5V

6k

1.5V

6k

CPARASITIC1.8pF

CPARASITIC1.8pF

10Ω

10Ω

LTC2241-12

16224112fc

applicaTions inForMaTiondifferential driver circuit. The VCM pin must be bypassed to ground close to the ADC with a 2.2µF or greater capacitor.

Input Drive Impedance

As with all high performance, high speed ADCs, the dy-namic performance of the LTC2241-12 can be influenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and input reactance can influence SFDR. At the falling edge of ENC, the sample-and-hold circuit will connect the 2pF sampling capacitor to the input pin and start the sampling period. The sampling period ends when ENC rises, holding the sampled input on the sampling capacitor. Ideally the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2fS); however, this is not always possible and the incomplete settling may degrade the SFDR. The sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling.

For the best performance, it is recommended to have a source impedance of 100Ω or less for each input. The source impedance should be matched for the differential inputs. Poor matching will result in higher even order harmonics, especially the second.

Input Drive Circuits

Figure 3 shows the LTC2241-12 being driven by an RF transformer with a center tapped secondary. The secondary center tap is DC biased with VCM, setting the ADC input signal at its optimum DC level. Terminating on the trans-former secondary is desirable, as this provides a common mode path for charging glitches caused by the sample and hold. Figure 3 shows a 1:1 turns ratio transformer. Other turns ratios can be used if the source impedance seen by the ADC does not exceed 100Ω for each ADC input. A disadvantage of using a transformer is the loss of low frequency response. Most small RF transformers have poor performance at frequencies below 1MHz.

Figure 4 demonstrates the use of a differential amplifier to convert a single ended input signal into a differential input signal. The advantage of this method is that it provides low frequency input response; however, the limited gain

bandwidth of most op amps will limit the SFDR at high input frequencies.

Figure 5 shows a capacitively-coupled input circuit. The impedance seen by the analog inputs should be matched.

The 25Ω resistors and 12pF capacitor on the analog inputs serve two purposes: isolating the drive circuitry from

Figure 3. Single-Ended to Differential Conversion Using a Transformer

Figure 4. Differential Drive with an Amplifier

Figure 5. Capacitively-Coupled Drive

25Ω

25Ω25Ω

25Ω

10Ω

0.1μF AIN+

AIN+

AIN–

AIN–

12pF

2.2μF

VCM

LTC2241-12ANALOG

INPUT

0.1μF T11:1

T1 = MA/COM ETC1-1TRESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE

224112 F03

25Ω

25Ω

50Ω

AIN+

AIN+

AIN–

AIN–

12pF

2.2μF

3pF

VCM

LTC2241-12

224112 F04

– –

+ +CM

ANALOGINPUT

HIGH SPEEDDIFFERENTIAL

AMPLIFIER

3pF

0.1μF

25Ω0.1μF

VCM

AIN+

AIN+

AIN–

AIN–

100Ω 100Ω

ANALOGINPUT

12pF

224112 F05

2.2μF

0.1μF25Ω

LTC2241-12

LTC2241-12

17224112fc

applicaTions inForMaTionthe sample-and-hold charging glitches and limiting the wideband noise at the converter input. For input frequen-cies higher than 100MHz, the capacitor may need to be decreased to prevent excessive signal loss.

The AIN+ and AIN

– inputs each have two pins to reduce package inductance. The two AIN

+ and the two AIN– pins

should be shorted together.

For input frequencies above 100MHz the input circuits of Figure 6, 7 and 8 are recommended. The balun transformer gives better high frequency response than a flux coupled center-tapped transformer. The coupling capacitors allow the analog inputs to be DC biased at 1.25V. In Figure 8 the series inductors are impedance matching elements that maximize the ADC bandwidth.

Reference Operation

Figure 9 shows the LTC2241-12 reference circuitry consist-ing of a 1.25V bandgap reference, a difference amplifier and switching and control circuit. The internal voltage reference can be configured for two pin selectable input ranges of 2V (±1V differential) or 1V (±0.5V differential). Tying the SENSE pin to VDD selects the 2V range; typing the SENSE pin to VCM selects the 1V range.

The 1.25V bandgap reference serves two functions: its output provides a DC bias point for setting the common mode voltage of any external input circuitry; additionally, the reference is used with a difference amplifier to gener-ate the differential reference levels needed by the internal ADC circuitry. An external bypass capacitor is required for the 1.25V reference output, VCM. This provides a high frequency low impedance path to ground for internal and external circuitry.

The difference amplifier generates the high and low reference for the ADC. High speed switching circuits are connected to these outputs and they must be externally bypassed. Each output has four pins: two each of REFHA and REFHB for the high reference and two each of REFLA and REFLB for the low reference. The multiple output pins are needed to reduce package inductance. Bypass capaci-tors must be connected as shown in Figure 9.

Figure 6. Recommended Front End Circuit for Input Frequencies Between 100MHz and 250MHz

Figure 7. Recommended Front End Circuit for Input Frequencies Between 250MHz and 500MHz

Figure 8. Recommended Front End Circuit for Input Frequencies Above 500MHz

25Ω

25Ω12Ω

12Ω

10Ω

0.1μF AIN+

AIN+

AIN–

AIN–

8pF

2.2μF

VCM

ANALOGINPUT

0.1μF

0.1μF

T1

T1 = MA/COM ETC1-1-13RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE

224112 F06

LTC2241-12

25Ω

10Ω

25Ω

0.1μF AIN+

AIN+

AIN–

AIN–

2.2μF

VCM

ANALOGINPUT

0.1μF

0.1μF

T1

T1 = MA/COM ETC1-1-13RESISTORS, CAPACITORSARE 0402 PACKAGE SIZE

224112 F07

LTC2241-12

25Ω

10Ω

25Ω

0.1μF AIN+

AIN+

AIN–

AIN–

2.2μF

VCM

LTC2241-12ANALOG

INPUT

0.1μF

0.1μF

T1

T1 = MA/COM ETC1-1-13RESISTORS, CAPACITORSARE 0402 PACKAGE SIZE

224112 F08

2.7nH

2.7nH

LTC2241-12

18224112fc

applicaTions inForMaTion

Other voltage ranges in between the pin selectable ranges can be programmed with two external resistors as shown in Figure 10. An external reference can be used by ap-plying its output directly or through a resistor divider to SENSE. It is not recommended to drive the SENSE pin with a logic device. The SENSE pin should be tied to the appropriate level as close to the converter as possible. If the SENSE pin is driven externally, it should be bypassed to ground as close to the device as possible with a 1µF ceramic capacitor.

Input Range

The input range can be set based on the application. The 2V input range will provide the best signal-to-noise performance while maintaining excellent SFDR. The 1V input range will have better SFDR performance, but the SNR will degrade by 5dB. See the Typical Performance Characteristics section.

Driving the Encode Inputs

The noise performance of the LTC2241-12 can depend on the encode signal quality as much as on the analog input. The ENC+/ENC– inputs are intended to be driven differentially, primarily for noise immunity from common mode noise sources. Each input is biased through a 4.8k resistor to a 1.5V bias. The bias resistors set the DC op-erating point for transformer coupled drive circuits and can set the logic threshold for single-ended drive circuits.

Any noise present on the encode signal will result in ad-ditional aperture jitter that will be RMS summed with the inherent ADC aperture jitter.

In applications where jitter is critical (high input frequen-cies) take the following into consideration:

1. Differential drive should be used.

2. Use as large an amplitude as possible; if transformer coupled use a higher turns ratio to increase the amplitude.

3. If the ADC is clocked with a sinusoidal signal, filter the encode signal to reduce wideband noise.

4. Balance the capacitance and series resistance at both encode inputs so that any coupled noise will appear at both inputs as common mode noise. The encode inputs have a common mode range of 1.2V to 2.0V. Each input may be driven from ground to VDD for single-ended drive.

Figure 9. Equivalent Reference Circuit

Figure 10. 1.5V Range ADC

VCM

REFHA

REFLB

SENSETIE TO VDD FOR 2V RANGE;TIE TO VCM FOR 1V RANGE;

RANGE = 2 • VSENSE FOR0.5V < VSENSE < 1V

1.25V

REFLA

REFHB

2.2μF

2.2μF

INTERNAL ADCHIGH REFERENCE

BUFFER

0.1μF

224112 F09

LTC2241-12

2Ω

DIFF AMP

1μF

1μF 0.1μF

INTERNAL ADCLOW REFERENCE

1.25V BANDGAPREFERENCE

1V 0.5V

RANGEDETECT

ANDCONTROL

VCM

SENSE

1.25V

2.2μF8k

12k

0.75V

1μF

224112 F10

LTC2241-12

LTC2241-12

19224112fc


Maximum and Minimum Encode Rates

The maximum encode rate for the LTC2241-12 is 210Msps. For the ADC to operate properly, the encode signal should have a 50% (±5%) duty cycle. Each half cycle must have at least 2.26ns for the ADC internal circuitry to have enough settling time for proper operation. Achieving a precise 50% duty cycle is easy with differential sinusoidal drive using a transformer or using symmetric differential logic such as PECL or LVDS.

An optional clock duty cycle stabilizer circuit can be used if the input clock has a non 50% duty cycle. This circuit uses the rising edge of the ENC+ pin to sample the analog input. The falling edge of ENC+ is ignored and the internal falling edge is generated by a phase-locked loop. The input clock duty cycle can vary from 40% to 60% and the clock duty cycle stabilizer will maintain a constant 50% internal duty

cycle. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require one hundred clock cycles for the PLL to lock onto the input clock. To use the clock duty cycle stabilizer, the MODE pin should be connected to 1/3VDD or 2/3VDD using external resistors.

The lower limit of the LTC2241-12 sample rate is determined by droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency for the LTC2241-12 is 1Msps.

DIGITAL OUTPUTS

Table 1 shows the relationship between the analog input voltage, the digital data bits, and the overflow bit.

Figure 11. Transformer Driven ENC+/ENC–

Figure 12a. Single-Ended ENC Drive,Not Recommended for Low Jitter Figure 12b. ENC Drive Using LVDS

VDD

VDDLTC2241-12

224112 F11

VDD

ENC–

ENC+

1.5V BIAS

1.5V BIAS

0.1μF

T1MA/COM

ETC1-1-13CLOCKINPUT

100Ω8.2pF

0.1μF

0.1μF

50Ω

••

50Ω

4.8k

4.8k

TO INTERNALADC CIRCUITS

224112 F12a

ENC–1.5V

VTHRESHOLD = 1.5VENC+

0.1μF

LTC2241-12

224112 F12b

ENC–

ENC+

LVDSCLOCK 100Ω

0.1μF

LTC2241-120.1μF

LTC2241-12

20224112fc

applicaTions inForMaTionTable 1. Output Codes vs Input Voltage

AIN+ – AIN

–

(2V Range)

OFD11 – D0

(Offset Binary)D11 – D0

(2’s Complement)

>+1.000000V +0.999512V +0.999024V

1 0 0

1111 1111 1111 1111 1111 1111 1111 1111 1110

0111 1111 1111 0111 1111 1111 0111 1111 1110

+0.000488V 0.000000V

–0.000488V –0.000976V

0 0 0 0

1000 0000 0001 1000 0000 0000 0111 1111 1111 0111 1111 1110

0000 0000 0001 0000 0000 0000 1111 1111 1111 1111 1111 1110

–0.999512V –1.000000V

<–1.000000V

0 0 1

0000 0000 0001 0000 0000 0000 0000 0000 0000

1000 0000 0001 1000 0000 0000 1000 0000 0000

Digital Output Modes

The LTC2241-12 can operate in several digital output modes: LVDS, CMOS running at full speed, and CMOS demultiplexed onto two buses, each of which runs at half speed. In the demultiplexed CMOS modes the two buses (referred to as bus A and bus B) can either be updated on alternate clock cycles (interleaved mode) or simultaneously (simultaneous mode). For details on the clock timing, refer to the timing diagrams.

The LVDS pin selects which digital output mode the part uses. This pin has a four-level logic input which should be connected to GND, 1/3VDD, 2/3VDD or VDD. An external resistor divider can be used to set the 1/3VDD or 2/3VDD logic values. Table 2 shows the logic states for the LVDS pin.

Table 2. LVDS Pin FunctionLVDS DIGITAL OUTPUT MODE

GND Full-Rate CMOS

1/3VDD Demultiplexed CMOS, Simultaneous Update

2/3VDD Demultiplexed CMOS, Interleaved Update

VDD LVDS

Digital Output Buffers (CMOS Modes)

Figure 13a shows an equivalent circuit for a single output buffer in the CMOS output mode. Each buffer is powered by OVDD and OGND, which are isolated from the ADC power and ground. The additional N-channel transistor in the output driver allows operation down to voltages as low as 0.5V. The internal resistor in series with the output makes the output appear as 50Ω to external circuitry and may eliminate the need for external damping resistors.

As with all high speed/high resolution converters, the digital output loading can affect the performance. The digital outputs of the LTC2241-12 should drive a minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. The output should be buffered with a device such as an 74VCX245 CMOS latch. For full speed operation the capacitive load should be kept under 10pF.

Lower OVDD voltages will also help reduce interference from the digital outputs.

Digital Output Buffers (LVDS Mode)

Figure 13b shows an equivalent circuit for a differential output pair in the LVDS output mode. A 3.5mA current is steered from OUT+ to OUT– or vice versa which creates a ±350mV differential voltage across the 100Ω termination resistor at the LVDS receiver. A feedback loop regulates the common mode output voltage to 1.25V. For proper operation each LVDS output pair needs an external 100Ω termination resistor, even if the signal is not used (such as OF+/OF– or CLKOUT+/CLKOUT–). To minimize noise the PC board traces for each LVDS output pair should be routed close together. To minimize clock skew all LVDS PC board traces should have about the same length.

LTC2241-12

21224112fc


Data Format

The LTC2241-12 parallel digital output can be selected for offset binary or 2’s complement format. The format is selected with the MODE pin. Connecting MODE to GND or 1/3VDD selects offset binary output format. Connecting MODE to 2/3VDD or VDD selects 2’s complement output format. An external resistor divider can be used to set the 1/3VDD or 2/3VDD logic values. Table 3 shows the logic states for the MODE pin.

Table 3. MODE Pin Function MODE PIN

OUTPUT FORMAT

CLOCK DUTY CYCLE STABILIZER

0 Offset Binary Off

1/3VDD Offset Binary On

2/3VDD 2’s Complement On

VDD 2’s Complement Off

Overflow Bit

An overflow output bit indicates when the converter is overranged or underranged. In CMOS mode, a logic high on the OFA pin indicates an overflow or underflow on the A data bus, while a logic high on the OFB pin indicates an overflow or underflow on the B data bus. In LVDS mode, a differential logic high on the OF+/OF– pins indicates an overflow or underflow.

Output Clock

The ADC has a delayed version of the ENC+ input available as a digital output, CLKOUT. The CLKOUT pin can be used

to synchronize the converter data to the digital system. This is necessary when using a sinusoidal encode. In all CMOS modes, A bus data will be updated just after CLKOUTA rises and can be latched on the falling edge of CLKOUTA. In demux CMOS mode with interleaved update, B bus data will be updated just after CLKOUTB rises and can be latched on the falling edge of CLKOUTB. In demux CMOS mode with simultaneous update, B bus data will be updated just after CLKOUTB falls and can be latched on the rising edge of CLKOUTB. In LVDS mode, data will be updated just after CLKOUT+/CLKOUT– rises and can be latched on the falling edge of CLKOUT+/CLKOUT–.

Output Driver Power

Separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. The power supply for the digital output buffers, OVDD, should be tied to the same power supply as for the logic being driven. For example if the converter is driving a DSP powered by a 1.8V supply then OVDD should be tied to that same 1.8V supply.

In the CMOS output mode, OVDD can be powered with any voltage up to 2.625V. OGND can be powered with any voltage from GND up to 1V and must be less than OVDD. The logic outputs will swing between OGND and OVDD.

In the LVDS output mode, OVDD should be connected to a 2.5V supply and OGND should be connected to GND.

Figure 13b. Digital Output in LVDS Mode

Figure 13a. Digital Output Buffer in CMOS Mode

LTC2241-12

2241 F13a

OVDD

VDD VDD0.1μF

43Ω TYPICALDATAOUTPUT

OGND

OVDD 0.5V TO 2.625V

PREDRIVERLOGIC

DATAFROMLATCH

OE

LTC2241-12

224112 F13b

OVDD

LVDSRECEIVER

OGND

1.25V

D

D

D

D

OUT+

0.1μF2.5V

OUT–

100Ω+

–

3.5mA

10k 10k

LTC2241-12

22224112fc

applicaTions inForMaTionOutput Enable

The outputs may be disabled with the output enable pin, OE. In CMOS or LVDS output modes OE high disables all data outputs including OF and CLKOUT. The data access and bus relinquish times are too slow to allow the outputs to be enabled and disabled during full speed operation. The output Hi-Z state is intended for use during long periods of inactivity.

The Hi-Z state is not a truly open circuit; the output pins that make an LVDS output pair have a 20k resistance be-tween them. Therefore in the CMOS output mode, adjacent data bits will have 20k resistance in between them, even in the Hi-Z state.

Sleep and Nap Modes

The converter may be placed in shutdown or nap modes to conserve power. Connecting SHDN to GND results in normal operation. Connecting SHDN to VDD and OE to VDD results in sleep mode, which powers down all circuitry including the reference and typically dissipates 1mW. When exiting sleep mode it will take milliseconds for the output data to become valid because the reference capacitors have to recharge and stabilize. Connecting SHDN to VDD and OE to GND results in nap mode, which typically dis-sipates 28mW. In nap mode, the on-chip reference circuit is kept on, so that recovery from nap mode is faster than that from sleep mode, typically taking 100 clock cycles. In both sleep and nap mode all digital outputs are disabled and enter the Hi-Z state.

GROUNDING AND BYPASSING

The LTC2241-12 requires a printed circuit board with a clean unbroken ground plane. A multilayer board with an internal ground plane is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital signal alongside an analog signal or underneath the ADC.

High quality ceramic bypass capacitors should be used at the VDD, OVDD, VCM, REFHA, REFHB, REFLA and REFLB pins. Bypass capacitors must be located as close to the

pins as possible. Of particular importance are the capaci-tors between REFHA and REFLB and between REFHB and REFLA. These capacitors should be as close to the device as possible (1.5mm or less). Size 0402 ceramic capacitors are recommended. The 2.2µF capacitor between REFHA and REFLA can be somewhat further away. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible.

The LTC2241-12 differential inputs should run parallel and close to each other. The input traces should be as short as possible to minimize capacitance and to minimize noise pickup.

HEAT TRANSFER

Most of the heat generated by the LTC2241-12 is trans-ferred from the die through the bottom-side exposed pad and package leads onto the printed circuit board. For good electrical and thermal performance, the exposed pad should be soldered to a large grounded pad on the PC board. It is critical that all ground pins are connected to a ground plane of sufficient area.

Clock Sources for Undersampling

Undersampling is especially demanding on the clock source and the higher the input frequency, the greater the sensitivity to clock jitter or phase noise. A clock source that degrades SNR of a full-scale signal by 1dB at 70MHz will degrade SNR by 3dB at 140MHz, and 4.5dB at 190MHz.

In cases where absolute clock frequency accuracy is relatively unimportant and only a single ADC is required, a canned oscillator from vendors such as Saronix or Vec-tron can be placed close to the ADC and simply connected directly to the ADC. If there is any distance to the ADC, some source termination to reduce ringing that may occur even over a fraction of an inch is advisable. You must not allow the clock to overshoot the supplies or performance will suffer. Do not filter the clock signal with a narrow band filter unless you have a sinusoidal clock source, as the rise and fall time artifacts present in typical digital clock signals will be translated into phase noise.

LTC2241-12

23224112fc

applicaTions inForMaTionThe lowest phase noise oscillators have single-ended si-nusoidal outputs, and for these devices the use of a filter close to the ADC may be beneficial. This filter should be close to the ADC to both reduce roundtrip reflection times, as well as reduce the susceptibility of the traces between the filter and the ADC. If the circuit is sensitive to close-in phase noise, the power supply for oscillators and any buffers must be very stable, or propagation delay variation with supply will translate into phase noise. Even though these clock sources may be regarded as digital devices, do not operate them on a digital supply. If your clock is also used to drive digital devices such as an FPGA, you should locate the oscillator, and any clock fan-out devices close to the ADC, and give the routing to the ADC prece-dence. The clock signals to the FPGA should have series termination at the driver to prevent high frequency noise

from the FPGA disturbing the substrate of the clock fan-out device. If you use an FPGA as a programmable divider, you must re-time the signal using the original oscillator, and the re-timing flip-flop as well as the oscillator should be close to the ADC, and powered with a very quiet supply.

For cases where there are multiple ADCs, or where the clock source originates some distance away, differential clock distribution is advisable. This is advisable both from the perspective of EMI, but also to avoid receiving noise from digital sources both radiated, as well as propagated in the waveguides that exist between the layers of multilayer PCBs. The differential pairs must be close together and distanced from other signals. The differential pair should be guarded on both sides with copper distanced at least 3x the distance between the traces, and grounded with vias no more than 1/4 inch apart.

LTC2241-12

24224112fc


Eval

uatio

n Ci

rcui

t Sch

emat

ic o

f the

LTC2

241-

12

A IN+

A IN+

A IN–

A IN–

REFH

ARE

FHA

REFL

BRE

FLB

REFH

BRE

FHB

REFL

ARE

FLA

C19

0.1µ

F

2 1 4 3 6 5 8 7 10 9 12 11

56 55 54 53 52 51 48 47 46 45 44 43 40 39 38 37 36 35 32 31 30 29 28 27 24 23 22 21

R17

100Ω

R3 100Ω

R7 1k

R37

BLM

18BB

470S

N1D

R38

100Ω

R39

100Ω

R40

100Ω

R42

100Ω

R43

100Ω

R18

100Ω

R19

100Ω

R20

100Ω

R21

100Ω

R22

100Ω

R28

100Ω

R30

100Ω

24

OF+

OF–

D11+

D11–

D10+

D10–

D9+

D9–

D8+

D8–

D7+

D7–

D6+

D6–

D5+

D5–

CLKO

UT+

CLKO

UT–

D4+

D4–

D3+

D3–

D2+

D2–

D1+

D1–

D0+

D0–

LTC2

241-

12

GNDGNDGNDGNDVDDVDDVDDVDDVDD

656461166362151413

C26

0.1µ

FC25

0.1 µ

F

2.5V

OVDDOVDDOVDDOVDD

OGNDOGNDOGNDOGND

25334150

26344249

TP6

V CM

ENC+

ENC–

SHDN

OE SENS

EM

ODE

LVDS

V CM

C20

0.1µ

F

C21

0.1µ

F

C23

0.1µ

F

C22

0.1µ

F

TP1

EXT

REF

TP2

GND

SHDN

3V D

D 1

GND

5

4 OE

2

V DD

6 GN

D

2.5V

1V C

M 3

EXT

REF

5

2 4 6

17 18 60 19 20

59

58 572.

5V

2.5V

2.5V

R24

1kJ4

SENS

E

1V D

D 3

GND

5

2 4 2/

36

1/3

J2M

ODE

R6 1

k

R8 1

k

LT17

63CD

E-2.

5

IN IN SHDN

V O V O

10 11 8

SEN

2

21

3 5 6BY

P

GND

GPGP

7

C38

0.01

µF

C34

0.1µ

F

C36

4.7µ

F

J6AU

X PW

RCO

NNEC

TOR

C24

10µF+2

.5V

+3.3

V3.

3V T

P5GN

D TP

42.

5V T

P3(N

O TU

RRET

)

1 2 3

EN12

EN34

EN56

EN78

EN I 1N

I 1P

I 2N

I 2P

I 3N

I 3P

I 4N

I 4P

I 5N

I 5P

I 6N

I 6P

I 7N

I 7P

I 8N

I 8P

V BB

O 1N

O 1P

O 2N

O 2P

O 3N

O 3P

O 4N

O 4P

O 5N

O 5P

O 6N

O 6P

O 7N

O 7P

O 8N

O 8P

VC1VC2VC3VC4VC5

1225264748

VE1VE2VE3VE4VE5

12

233637

U3 F

INII0

8

3.3V

EN12

EN34

EN56

EN78

EN I 1N

I 1P

I 2N

I 2P

I 3N

I 3P

I 4N

I 4P

I 5N

I 5P

I 6N

I 6P

I 7N

I 7P

I 8N

I 8P

V BB

O 1N

O 1P

O 2N

O 2P

O 3N

O 3P

O 4N

O 4P

O 5N

O 5P

O 6N

O 6P

O 7N

O 7P

O 8N

O 8P

VC1VC2VC3VC4VC5

1225264748

VE1VE2VE3VE4VE5

12

233637

U3 F

INII0

8

3.3V3 22 27 46 13 4 5 6 7 8 9 10 11 14 15 16 17 18 19 20 21

45 44 43 42 41 40 39 38 35 34 33 32 31 30 29 28 45 44 43 42 41 40 39 38 35 34 33 32 31 30 29 28

3 22 27 46 13 4 5 6 7 8 9 10 11 14 15 16 17 18 19 20 21

24

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53

56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100

55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99

LVDS

BUF

FER

BYPA

SS

C28

0.1µ

FC2

90.

1µF

3.3V

C30

0.1µ

FC3

10.

1µF

C32

0.1µ

FC3

30.

1µF

C5 0.1µ

FC8 0.

1µF

R16

100k

V CC

24LC

02ST

GND 4 22

4112

AI0

1

8

ARRAYEEPROM

SCL

SDA

WP

A2 A1 A0

6 5 7 3 2 1

C27

0.1µ

F

R46

4990

Ω

R29

4990

Ω

2.5V

R26

4990

Ω

R1 49.9

Ω

R2 49.9

Ω

R44.

99Ω

R54.

99Ω

J7EN

CODE

CLK

C3 0.1µ

FC1

10.

1µF

C4 1.8p

FR41

100Ω

C13

0.1µ

F

C14

0.1µ

F

C15

1µF

C16

1µF

C17

2.2µ

F

R23

100Ω

C12

0.1µ

F

C9 1.8p

F

R11

49.9

Ω

R12

49.9

Ω

R13

4.99

Ω

R14

4.99

Ω

R912

.4Ω

R10

12.4

Ω

C18

2.2µ

F

C10

0.1µ

FR1

549

.9Ω

T2M

ABA-

0071

59-0

0000

0

R27

49.9

Ω

A IN

C6 0.1µ

FJ5 SM

A

C2 0.1µ

F

C7 0.1µ

F

SMA

C1 0.1µ

F

T1M

ABA-

0071

59-0

0000

0

VERS

ION

DEVI

CE

BITS

SA

MPL

E RA

TEDC

997B

-A

LTC2

242-

12

12

250M

sps

DC99

7B-B

LT

C224

1-12

12

21

0Msp

sDC

997B

-C

LTC2

240-

12

12

170M

sps

DC99

7B-D

LT

C224

2-10

10

25

0Msp

sDC

997B

-E

LTC2

241-

10

10

210M

sps

DC99

7B-F

LT

C224

0-10

10

17

0Msp

s

R25

1k

U5

SJ

LTC2241-12

25224112fc

applicaTions inForMaTionSilkscreen Top

Layer 2 GND Plane

Layer 1 Component Side

LTC2241-12

26224112fc

Layer 3 Power/Ground Plane

applicaTions inForMaTionLayer 4 Power/Ground Planes

Layer 5 Power/Ground Planes

LTC2241-12

27224112fc

Layer Back Solder Side Silk Screen Back, Solder Side


LTC2241-12

28224112fc

9 .00 ± 0.10(4 SIDES)

NOTE:1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-52. ALL DIMENSIONS ARE IN MILLIMETERS3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT4. EXPOSED PAD SHALL BE SOLDER PLATED5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 6. DRAWING NOT TO SCALE

PIN 1 TOP MARK(SEE NOTE 5)

0.40 ± 0.10

6463

12

BOTTOM VIEW—EXPOSED PAD

7.15 ± 0.10

7.15 ± 0.10

7.50 REF(4-SIDES)

0.75 ± 0.05R = 0.10

TYP

R = 0.115TYP

0.25 ± 0.05

0.50 BSC

0.200 REF

0.00 – 0.05

(UP64) QFN 0406 REV C

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONSAPPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.70 ±0.05

7.50 REF(4 SIDES)

7.15 ±0.05

7.15 ±0.05

8.10 ±0.05 9.50 ±0.05

0.25 ±0.050.50 BSC

PACKAGE OUTLINE

PIN 1CHAMFER

C = 0.35

package DescripTionPlease refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

UP Package64-Lead Plastic QFN (9mm × 9mm)

(Reference LTC DWG # 05-08-1705 Rev C)

LTC2241-12

29224112fc

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

revision hisToryREV DATE DESCRIPTION PAGE NUMBER

C 10/11 Changed pin names on schematic drawing.Reordered board layers in Applications Information.

2425 - 27

(Revision history begins at Rev C)

LTC2241-12

30224112fc

Linear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 www.linear.com LINEAR TECHNOLOGY CORPORATION 2006

LT 1011 REV C • PRINTED IN USA

relaTeD parTsPART NUMBER DESCRIPTION COMMENTS

LTC1748 14-Bit, 80Msps, 5V ADC 76.3dB SNR, 90dB SFDR, 48-Pin TSSOP

LTC1750 14-Bit, 80Msps, 5V Wideband ADC Up to 500MHz IF Undersampling, 90dB SFDR

LT®1993-2 High Speed Differential Op Amp 800MHz BW, 70dBc Distortion at 70MHz, 6dB Gain

LT1994 Low Noise, Low Distortion Fully Differential Input/Output Amplifier/Driver

Low Distortion: –94dBc at 1MHz

LTC2202 16-Bit, 10Msps, 3.3V ADC, Lowest Noise 140mW, 81.6dB SNR, 100dB SFDR, 48-Pin QFN

LTC2208 16-Bit, 130Msps, 3.3V ADC, LVDS Outputs 1250mW, 77.7dB SNR, 100dB SFDR, 48-Pin QFN


LTC2220-1 12-Bit, 185Msps, 3.3V ADC, LVDS Outputs 910mW, 67.7dB SNR, 80dB SFDR, 64-Pin QFN


LTC2224 12-Bit, 135Msps, 3.3V ADC, High IF Sampling 630mW, 67.6dB SNR, 84dB SFDR, 48-Pin QFN








LTC2255 14-Bit, 125Msps, 3V ADC, Lowest Power 395mW, 72.5dB SNR, 88dB SFDR, 32-Pin QFN

LTC2284 14-Bit, Dual, 105Msps, 3V ADC, Low Crosstalk 540mW, 72.4dB SNR, 88dB SFDR, 64-Pin QFN

LT5512 DC to 3GHz High Signal Level Downconverting Mixer DC to 3GHz, 21dBm IIP3, Integrated LO Buffer

LT5514 Ultralow Distortion IF Amplifier/ADC Driver with Digitally Controlled Gain

450MHz to 1dB BW, 47dB OIP3, Digital Gain Control 10.5dB to 33dB in 1.5dB/Step

LT5515 1.5GHz to 2.5GHz Direct Conversion Quadrature Demodulator High IIP3: 20dBm at 1.9GHz, Integrated LO Quadrature Generator

LT5516 800MHz to 1.5GHz Direct Conversion Quadrature Demodulator High IIP3: 21.5dBm at 900MHz, Integrated LO Quadrature Generator

LT5517 40MHz to 900MHz Direct Conversion Quadrature Demodulator High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator

LT5522 600MHz to 2.7GHz High Linearity Downconverting Mixer 4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz, NF = 12.5dB, 50Ω Single-Ended RF and LO Ports

LTC2241-12 - 12-Bit, 210Msps ADC - Analog

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