The ARM® RealView® family of feature rich development boards provides an exc ell ent env iron ment for prototy ping sys tem-on -c hip des igns. Thro ugh a range of pl ug- in op ti on s, hardware and soft wa re appl ic at io ns can be developed and debugged. The high performance Versatile family enhances the end-user experience for benchmarking and applicat ion dev el opmen t. It simplifies hardware and software development, which shortens time to market. Logic Tiles are the basic building blocks for FPGA prototyping wit h ARM boa rds. Bec aus e of their flexible interc onne ct, Logic Tiles can be used to prototype complete systems on chip, but they are normally used to expand with custom AMBA peripherals the ARM subsystems provided on RealView Platform Baseboards and the RealView Emulation Baseboard. This datasheet describes the Logic Tile for XC5VLX330 Xilinx Virtex-5 FPGA. Logic Tiles are based on a single FPGA to provide the highest flexibility in terms of the number of FPGAs in the system. The signals from the FPGA are routed to the upper and lower stacking headers, so that the design in the FPGA can communicate with the design on the baseboard or on extra Logic Tiles on top of it. Logic Tile for XC5VLX330 FPGA The Logic Tile for the Xilinx XC5VLX330 FPGA is implemented in a 65-nanometer process with wider Look-Up-Tables inputs (6-input LUTs), which reduce critical path delay s, facil it at ing ti min g cl osu re for ASIC pr otot yping. It has the same I/ O interconnect as the Logic Tiles for the Xilinx Virtex-4 FPGA with a maximum clock freque ncy and capacity increase, making system partitioning easier. The Logic Tile for the Xilinx Virtex -5 FPGA also features an on-board 32MB ZBT SRAM. Logic Tiles feature configurable switches, which allow flexible interconnect between boards without the need of cables. The clock architecture of Logic Tiles allows you to stack up to five of them together with minimal clock skew. Mo st of the signals on the Logic Ti le sta cking connectors work at 3. 3V, but one complet e set of connector s have a configurable I/O voltage.
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8/3/2019 LT XC5VLX330 Datasheet
http://slidepdf.com/reader/full/lt-xc5vlx330-datasheet 1/2
The ARM® RealView® family of feature rich development boards provides an
excellent environment for prototyping system-on-chip designs. Through arange of plug-in options, hardware and software applications can bedeveloped and debugged.
The high performance Versatile family enhances the end-user experience forbenchmarking and application development. It simplifies hardware andsoftware development, which shortens time to market.
Logic Tiles are the basic building blocks for FPGA prototyping with ARMboards. Because of their flexible interconnect, Logic Tiles can be used toprototype complete systems on chip, but they are normally used to expandwith custom AMBA peripherals the ARM subsystems provided on RealViewPlatform Baseboards and the RealView Emulation Baseboard.
This datasheet describes the Logic Tile for XC5VLX330 Xilinx Virtex-5 FPGA.Logic Tiles are based on a single FPGA to provide the highest flexibility interms of the number of FPGAs in the system. The signals from the FPGA arerouted to the upper and lower stacking headers, so that the design in theFPGA can communicate with the design on the baseboard or on extra LogicTiles on top of it.
Logic Tile for XC5VLX330 FPGA
The Logic Tile for the Xilinx XC5VLX330 FPGA is implemented in a 65-nanometer
process with wider Look-Up-Tables inputs (6-input LUTs), which reduce critical pathdelays, facilitating timing closure for ASIC prototyping. It has the same I/Ointerconnect as the Logic Tiles for the Xilinx Virtex-4 FPGA with a maximum clock
frequency and capacity increase, making system partitioning easier. The Logic Tile forthe Xilinx Virtex-5 FPGA also features an on-board 32MB ZBT SRAM.
Logic Tiles feature configurable switches, which allow flexible interconnect betweenboards without the need of cables. The clock architecture of Logic Tiles allows you tostack up to five of them together with minimal clock skew.
Most of the signals on the Logic Tile stacking connectors work at 3.3V, but onecomplete set of connectors have a configurable I/O voltage.
8/3/2019 LT XC5VLX330 Datasheet
http://slidepdf.com/reader/full/lt-xc5vlx330-datasheet 2/2
Specification
Logic Tile Features
Virtex-5 XC5VLX330 FPGA
2 JTAG scan-chains for debug and FPGA programming
Configuration Flash to store 2 FPGA images 8 User switches
8 User LEDs
3 programmable clock generators
Push button Battery for FPGA encryption key
On-board 32MB ZBT SRAM
Comparison with Virtex-4 Logic Tiles
Deliverables
Documentation
Example RTL and FPGA bit-files for a LogicTile on top of a RealView Platform Baseboard
or Emulation Baseboard Utility to reprogram the FPGA configurationFlash with RealView ICE or the USB debuggerintegrated on RealView baseboards
I/O signals on stacking connectors
The stacking connectors and I/O connectionsare a superset of the Virtex-II and Virtex-4Logic Tiles.
On-board switches can be configured toconnect signals from the FPGA to these pinsor to route signals straight through the board
Example system: Core Tile for ARM11 MPCore, Emulation Baseboard and Logic Tiles
Ordering Information
Part number Description Distributor
LT330-BD-0239A Logic Tile for XC5VLX330
ARM, ARM Powered, StrongARM, Thumb, Multi-ICE, PrimeCell, RealView, ARM7TDMI, ARM9TDMI, EmbeddedICE and Jazelle are registered trademarks of ARM Limited. ARM7TDMI- S, ARM7EJ-S, ARM720T, ARM920T, ARM922T, ARM9E, ARM926EJ- S, ARM946E-S, ARM966E-S, ARM1020E, ARM1022E, ARM1026EJ-S, ARM11, ARM1136J-S,ARM1136JF-S, ETK11, ETM, ETM7, ETM9, ETM10, ETM10RV, ETM11RV, ETB11, ETB, EmbeddedICE -RT, AMBA, ModelGen, ARM Developer Suite, Embedded Trace Macrocell, PrimeXsys, MOVE, Integrator, and JTEK are trademarks of ARM Limited. Java is a trademark of Sun Microsystems, Inc. XScale is a trademark of Intel Corporation. All other
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information.
LT-XC5VLX330+_Datasheet v2.doc
Feature LT-XC4VLX160LT-XC4VLX200 LT-XC5VLX330
FPGA slices 68K / 89K 331K
Header I/O pins 918 918
External clock signals 21 21ZBT SRAM - 32MB
FPGA block RAM 0.65MB / 0.7MB 1.3MB
User LEDs and switches 8 8Header I/O fold switches Upper and lower Upper and lower
Header Top Bottom
HDRX 144 144
HDRY 144 144HDRZ 107 107
HDRZ through 128
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