Low Noise Oscillator in ADPLL toward Direct-to-RF All-digital Polar Transmitter JIAN CHEN Doctoral Thesis in Electronic and Computer Systems Stockholm, Sweden 2012
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Low Noise Oscillator in ADPLL toward Direct-to-RF
All-digital Polar Transmitter
JIAN CHEN
Doctoral Thesis in Electronic and Computer SystemsStockholm, Sweden 2012
TRITA-ICT/ECS AVH 13:03ISSN 1653-6363ISRN KTH/ICT/ECS/AVH-13/03-SEISBN 978-91-7501-643-6
KTH School of Information andCommunication TechnologySE-164 40 Kista, Stockholm
Sweden
Akademisk avhandling som med tillstand av Kungl Tekniska hogskolan framlaggestill offentlig granskning for avlaggande av teknologie doktorsexamen i Elektronikoch Datorsystem onsdag den 13 mars 2013 klockan 9.00 i Sal D, Forum 120, KunglTekniska hogskolan, Kista 164 40, Stockholma.
c© Jian Chen, September 2012
Tryck: Universitetsservice US AB
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Abstract
In recent years all-digital or digitally-intensive RF transmitters (TX) haveattracted great attention in both literature and industry. The motivation isto implement RF circuits in a manner suiting advanced nanometer CMOSprocesses. To achieve that, information is encoded in the time-domain ratherthan voltage amplitude. This enables RF design to also benefit from CMOSprocess scaling. In this thesis an improved architecture of a digitally-intensivetransmitter is proposed and validated experimentally. The techniques to loweroscillator phase noise and all-digital phase-locked loop (ADPLL) quantizationnoise are discussed and proved by both simulation and measurements.
The impact of device sizing on 1/f2 noise is analyzed and validated bymeasurements. Seven oscillators in 180-nm CMOS with the same LC-tank,operation frequency and power consumption but different core device widthare compared. The conclusion clarifies the different suggestions on devicesizing in the literature. It is illustrated that tail noise contribution is stronglypositive dependent to core device sizing, while the contribution of core devicesthemselves is weakly dependent. Measurements demonstrate that there is a14-dB phase noise increase when sizing core devices from 40 µm to 280 µmin the case of noisy tail current. If tail current is clean, the increase is only4 dB. For 1/f3 phase noise, the investigation reveals that the capacitancemodulation is the dominant factor accounting for the 1/f or flick noise up-conversion, which is proved by measurements of 180-nm CMOS designs.
A class-C oscillator with ensured start-up and constant amplitude is pre-sented. It achieves a 3.9-dB phase noise reduction in theory and 5-dB reduc-tion in measurements, compared to a conventional LC-tank oscillator operat-ing at the same frequency and power. With the help of a digital bias voltageand bias current control loop, a 191 Figure-of-Merit (FoM) is achieved, show-ing the ability for low power and noise application.
The previous oscillator optimization techniques have been applied in de-signing a digital controlled oscillator (DCO) for an ADPLL. A fine tuningvaractor is proposed to reduce quantization noise, achieving a frequency stepof only several hundreds Hz. In order to measure this small frequency stepwhen the DCO is free-running, a method based on the narrow-band frequencymodulation (FM) theory is proposed. The ADPLL wide-band FM is fulfilledby using a digital two-point modulation so that the modulation bandwidth isnot limited by the ADPLL loop dynamic.
Finally an all-digital polar TX is proposed based on an improved archi-tecture. The ADPLL is used for FM while a one-bit low-pass Σ∆ modulatorusing the phase modulated ADPLL output as the clock accomplishes ampli-tude modulation. A simple AND gate is adopted to increase the fundamentalpower as mixers. A class-D power amplifier stages deliver 6.8-dBm powerto antenna through a on-chip band-pass pre-filter. The filter also acts assingle-ended to differential-end conversion and matching network.
keywords: all-digital, digitally-intensive, frequency modualtion, phasemodulation, amplitude modulation, polar, transmitter, oscillator, digital con-troled oscillator, DCO, VCO, voltage controled oscillator, class-C oscillator,class-D PA, ADPLL, phase noise, RF, CMOS.
Acknowledgement
It is a long but exciting journey (since 2006) to reach the destination of a PhDstudy. I would like to take this opportunity to appreciate sincerely all the peoplehelping me during the road, although I might forget their names due to my badmemory.
First I would like to thank my supervisors Prof. Li-Rong Zheng, Prof. HannuTenhunen and Prof. Dian Zhou for giving the opportunity to study at KTH, sup-porting me along the way and sharing with me their knowledge.
Special thanks go to my technology supervisor Dr. Fredrik Jonsson, who opensthe door of RF analog circuits for me, inspires me to progress by his deep insightsand intuitive understanding on this field, and walks beside me during the way. ThePhD journey would not be of such great fun if without his knowledge and advice.
I wish to thank Dr. Qiang Chen for sharing his experience and suggestions forboth work and life. I would like to thank Prof. Axel Jantsch, Agneta Herling, AlinaMunteanu and Robin Gehrke for their support and assistance, and Prof. HakanOlsson for interesting discussion. I also want to thank all colleagues at KTH fortheir help who have made the PhD more enjoyable by complaining together andentertaining talks during lunch time: Geng Yang, Botao Shao, Dr. Huimin She,Qiansu Wan, Liang Rong, Jue Shen, Jie Gao, Yi Feng, Li Xie, Zhiying Liu, JianLiu, Zhi Zhang, Peng Wang, Ning Ma, David S. Mendoza, Ana Lopez Cabezas, Dr.Zuo Zhou, Qin Zhou, Jia Mao, Zhai Chuanying, Xueqian Zhao, Pei Liu, Ming Liu,Yasar Amin, Zhibo Pan, Shaoteng Liu, Yajie Qin, Xiaolong Yuan, Dr. JinliangHuang, Dr.Jinfeng Du, Dr. Majid Baghaei Neijad, Dr. Saul Rodriguez Duenas,Dr. Roshan Weerasekera and Assoc. Prof. Zhonghai Lu.
I also would like to express my sincere gratitude to Assoc. Prof. Svante Signellfor reviewing the thesis, Prof. Georges Gielen from Katholieke Universiteit Leuvenas my opponent, as well as Dr. Sven Mattisson from Ericsson, Assoc. Prof. RobertBogdan Staszewski from TU Delft, Prof. Peter Handel and Prof. Mark Smith forserving as my committee members.
I performed this PhD project together with Catena Wireless Electronics AB,Kista and after 2010 I fully worked there since I finished the PhD study except thedefense. I sincerely thank my industry supervisors: Mats Carlsson and Dr. Char-lotta Hedenas for their invaluable discussion. Also special thanks to Jan Rapp,Kave Kianush and Rien Geurtsen for their support during writing the thesis and
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impressive talks, Paul Stephansson for cooperating an ADPLL project, FredrikPusa and Andreas Drejfert for the fun time together, Magnus Bohman and GitiAmozandeh for reviewing design, Rob Visser and Marcel van de Gevel at Delft forreviewing a manuscript, and all other colleagues for your help during that period.Since 2012, I work at Ericsson, Kista where I would like to thank all my colleaguesand my manager Ali Ladjemi for helping me to involve into the new place, answer-ing my questions regarding to both work and life, encouraging me to pursue newtechnology, and sharing the fun time during work and Friday Fika.
Finally I would like to thank my family, my wife, my parents, and my brotherfor your unconditional love and support, and for always encouraging me. I alsowant to thank my mother in-law for helping us to take care of my small son. Youare always my motivation to move forward.
Abbreviations
ACPR adjacent channel power ratioADC analog to digital converterADPLL all digital phase lockedAM amplitude modulationASIC application specific integrated circuitASK amplitude shift keyingAWGN additive white Gaussian noiseBER bit error rateBW bandwidthCKR sampled reference clockCKV digitally-controlled oscillator clockCMOS complementary-metal-oxide semiconductorCNR carrier to noise ratioDAC digital-to-analog converterDCO digitally-controlled oscillatorDSP digital signal processingECG electrocardiographyEEG electroencephalographyFCW frequency control wordFM frequency modulationFoM figure of meritFPAA field-programmable analog arrayFPGA field-programmable gate arrayFSM finite state machineGMSK Gaussian filtered mnimum shift keyingIC integrated circuitIoT Internet-of-thingsISF impulse sensitivity functionIQ inphase quadratureKTH Royal Institute of TechnologyKDCO digitally-controlled oscillator gainLC-VCO LC-tank voltage-controlled oscillatorLMS least-mean square
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LNA low noise amplifierLTE long-term evolutionLTI linear time-invariantLTV linear time-variantLO local oscillatorMEMS micro-electro-mechanical systemsNTF noise transfer functionNMF noise modulation functionOFDM orthogonal frequency division multiplexingPA power amplifierPAPR peak to average power ratioPM phase modulationPLL phase locked loopPSD power spectral densityPVT process voltage temperaturePW-VCO pulse-wave voltage-controlled oscillatorQoS quality of serviceREF reference clockRF radio frequencyRF-DAC radio frequency digital-to-analog converterRFID radio frequency identificationRX receiverSDR software-defined radioSoC system-on-chipSSB single side bandTDC time-to-digital converterTX transmitterVPA variable phase accumulatorVCO voltage-controled oscillatorWCDMA wideband code division multiple accessWIMAX worldwide interoperability for microwave
accessWLAN wireless local area network
Contents
Contents ix
List of Figures xi
1 Introduction 51.1 Digitally-intensive RF Design . . . . . . . . . . . . . . . . . . . . . . 71.2 Thesis Investigation Scope . . . . . . . . . . . . . . . . . . . . . . . . 81.3 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . 111.4 Included Papers and Contribution . . . . . . . . . . . . . . . . . . . 12
2 Phase Noise and Jitter 172.1 Definition and Metrics . . . . . . . . . . . . . . . . . . . . . . . . . . 172.2 Phase Noise Propagation in Systems . . . . . . . . . . . . . . . . . . 202.3 Phase Noise Requirement of Oscillators . . . . . . . . . . . . . . . . 222.4 Fast Oscillator Phase Noise Measurement . . . . . . . . . . . . . . . 25
3 Phase Noise Optimization for CMOS LC Oscillators 293.1 Large Signal Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 293.2 Phase Noise Sources and Conversion Mechanisms . . . . . . . . . . . 333.3 Device Sizing for 1/f2 Phase Noise . . . . . . . . . . . . . . . . . . . 383.4 Sizing for 1/f3 Phase Noise . . . . . . . . . . . . . . . . . . . . . . . 393.5 Pulse-wave or Class-C Oscillator . . . . . . . . . . . . . . . . . . . . 413.6 Hand Calculations for a Start Point . . . . . . . . . . . . . . . . . . 44
4 Quantization Noise and Spurs in ADPLL 494.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494.2 ADPLL Noise Analysis: s-domain, z-domain and Time-domain . . . 514.3 Quantization Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544.4 Spurious Tones . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564.5 Ill Condition: Steady-state Bandwidth Variation . . . . . . . . . . . 574.6 Frequency Tuning Resolution . . . . . . . . . . . . . . . . . . . . . . 58
5 Direct Digital-RF Polar Transmitter 63
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x CONTENTS
5.1 Contemporary Transmitters: more digital . . . . . . . . . . . . . . . 645.2 The Proposed All-digital Polar Transmitter . . . . . . . . . . . . . . 665.3 Phase Modulation: ADPLL with two-point modulation . . . . . . . 695.4 Amplitude Modulation: low-pass ∆Σ modulator . . . . . . . . . . . 705.5 H-bridge Class-D PA Stages and on-chip Matching Filter . . . . . . 72
6 Summary and Future Work 756.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
A Phase spectral density and voltage spectral density 79
B Jitter and phase noise 81B.1 Synchronouse jitter and noise floor . . . . . . . . . . . . . . . . . . . 81B.2 Accumulating jitter and 1/f2 phase noise . . . . . . . . . . . . . . . 82
Bibliography 85
7 Included Papers 97
List of Figures
1.1 Communication based networking. . . . . . . . . . . . . . . . . . . . . . 5
1.2 Internet user worldwide. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 Minimum feature size trend for Intel microprocessor technologies [1] . . 6
1.4 Digital polar transmitter with the D/A interface before antenna. . . . . 7
1.5 The die photographs and simplified schematics of (a) LC-tank VCOwith the tail noise filter, (b) LC-tank VCO with a tail capacitor and (c)pulse-wave or class-C VCO. . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.6 (a) the ADPLL block diagram and (b) the die photograph. . . . . . . . 10
1.7 The all-digital TX die photograph and the block diagram. . . . . . . . . 11
2.1 Phase noise in the frequency domain . . . . . . . . . . . . . . . . . . . . 17
2.2 Normalized single-side-band(SSB) PSD . . . . . . . . . . . . . . . . . . 18
2.3 Synchronous jitter and accumulating jitter . . . . . . . . . . . . . . . . . 19
2.4 Phase noise propagation in buffers. . . . . . . . . . . . . . . . . . . . . . 21
2.5 Phase noise propagation in frequency dividers. . . . . . . . . . . . . . . 21
2.6 Phase noise propagation in buffers. . . . . . . . . . . . . . . . . . . . . . 22
2.7 Phase noise propagation in mixers. . . . . . . . . . . . . . . . . . . . . . 22
2.8 Reciprocal mixing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.9 (a) 8PSK Constellation, (b) symbol boundary and (c) probability dis-tribution function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.10 TX leakage in a RFID reader. . . . . . . . . . . . . . . . . . . . . . . . . 25
2.11 TX leakage to adjacent channels. . . . . . . . . . . . . . . . . . . . . . . 25
2.12 Phase noise measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.1 A simplified schematic of an all-PMOS LC-tank oscillator . . . . . . . . 30
3.2 The feedback contained in a LC-tank oscillator . . . . . . . . . . . . . . 30
3.3 The steady-state time domain waveforms of the drain current, the common-source voltage and the gate voltage. . . . . . . . . . . . . . . . . . . . . 31
3.4 The schematic of the switched capacitor unit cell. . . . . . . . . . . . . . 32
3.5 (a) Tank voltage and (b) the ISF of active devices. . . . . . . . . . . . . 33
3.6 The different phase noise contributions in the LC-VCO. . . . . . . . . . 34
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xii List of Figures
3.7 (a)Output voltage, (b) tail noise modulation function - Gtail and (c)effective tail noise ISF - Γtail. ∆t is the conduction time. . . . . . . . . 36
3.8 (a) Output voltage, (b) switch pair noise modulation function - Gm and(c) effective tail noise ISF - Γsp. ∆t is the conduction time. . . . . . . 37
3.9 Flicker noise up-conversion mechanism. . . . . . . . . . . . . . . . . . . 403.10 The schematic of PW-VCO. . . . . . . . . . . . . . . . . . . . . . . . . . 413.11 The time domain waveform of the PW-VCO. . . . . . . . . . . . . . . . 423.12 Start-up circuit block diagram . . . . . . . . . . . . . . . . . . . . . . . 43
4.1 (a) Block diagram of ADPLLs and (b) phase accumulators and (c) thefractional variable phase . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.2 Quantization noise in ADPLL . . . . . . . . . . . . . . . . . . . . . . . . 514.3 S-domain model of the ADPLL . . . . . . . . . . . . . . . . . . . . . . . 514.4 Z-domain model of the ADPLL . . . . . . . . . . . . . . . . . . . . . . . 534.5 Phase noise (1/f2) of a time-domain free-running DCO: -120 dBc/Hz
phase noise at 1-MHz offset from the 3.15-GHz center frequency and -150 dBc/Hz noise floor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.6 (a) phase noise and (b) phase error from a time-domain model withdifferent bandwidth: 40 kHz (blue), 100 kHz (gree) and 300 kHz (red).DCO phase nosie: -120 dBc/Hz @ 1-MHz offset and - 150 dBc/Hz noisefloor. Ideal DCO frequency tuning. Ideal TDC. . . . . . . . . . . . . . . 55
4.7 Phase error code demonstrating a certain pattern. . . . . . . . . . . . . 574.8 Phase noise when sweeping TDC resolution tres: 5 ps, 10 ps, 20 ps and
40 ps. DCO phase nosie: -100 dBc/Hz @ 1-MHz offset. Ideal DCOfrequency tuning. The PLL BW: 100 kHz. . . . . . . . . . . . . . . . . . 58
4.9 Fine tuning arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . 594.10 Measurement of the fine tuning step . . . . . . . . . . . . . . . . . . . . 60
5.1 (a) The polar transmitter and (b) the quadrature (IQ)transmitter . . . 635.2 Mobile standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645.3 The frequency up-conversion in digital transmitters . . . . . . . . . . . . 655.4 The proposed all-digital polar transmitter . . . . . . . . . . . . . . . . . 675.5 The operation of the proposed all-digital polar transmitter . . . . . . . . 685.6 The two point modulation scheme of the ADPLL . . . . . . . . . . . . . 695.7 The linear z-domain model of the first-order low-pass ∆Σ modulator . . 705.8 The noise shaping function of the ∆Σ modulators with different orders. 715.9 H-bridge Class-D PA Stages and on-chip Matching Filter . . . . . . . . 72
B.1 Synchronous jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81B.2 Accumulating jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
List of Publications
Papers included in the thesis
Journal Papers
1. Jian Chen, Fredrik Jonsson, Mats Carlsson, Charlotta Hedenas and Li-RongZheng. “Flicker Noise Conversion in CMOS LC Oscillators: Capacitancemodulation dominance and core device sizing”. Journal of Analog IntegratedCircuits and Signal Processing, vol. 68, no. 2, pp. 145-154, Aug. 2011.(Included Paper 3)
2. Jian Chen, Fredrik Jonsson, Mats Carlsson, Charlotta Hedenas and Li-RongZheng. “A Low Power, Startup Ensured and Constant Amplitude Class-CVCO in 0.18 µm CMOS”. IEEE Microwave and Wireless Components Letters(MWCL), vol. 21, no. 8, pp. 427-429, Aug. 2011. (Included Paper 5)
3. Jian Chen, Liang Rong, Fredrik Jonsson, Geng Yang and Li-Rong Zheng.“The Design of All-Digital Polar Transmitter Based on ADPLL and PhaseSynchronized ∆Σ Modulator ”. IEEE Journal of Solid-State Circuits (JSSC),vol. 47, no. 5, pp. 1154-1164, May 2012. (Included Paper 7)
4. Jian Chen, Fredrik Jonsson, Mats Carlsson, Charlotta Hedenas, Dian Zhouand Li-Rong Zheng. “Experimental Validation of Device Sizing on CMOSLC-VCO Phase Noise”. Manuscript. (Included Paper 2)
Conference Papers
5. Jian Chen, Fredrik Jonsson, Li-Rong Zheng, Hannu Tenhunen and DianZhou. “Sizing of MOS device in LC-tank Oscillators”. Proc. the 25th IEEENorchip Conference, Denmark, pp. 1-6, Nov. 2007. (Included Paper 1)
6. Jian Chen, Fredrik Jonsson, Hakan Olsson, Li-Rong Zheng and Dian Zhou.“A Current Shaping Technique to Lower Phase Noise in LC Oscillators”.Proc. 15th IEEE International Conference on Electronics, Circuits and Sys-tems (ICECS), Malta, pp. 392-395, Aug. 31-Sept. 3, 2008. (IncludedPaper 4)
7. Jian Chen, Liang Rong, Fredrik Jonsson and Li-Rong Zheng. “All-digitaltransmitter based on ADPLL and phase synchronized delta sigma modulator”. Proc. IEEE Radio Frequency Integrated Circuits Symposium (RFIC),pp.1-4, Jul. 2011. (One of 16 best student paper finalists) (IncludedPaper 6)
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Publications related but not included in the thesis:
Journal Papers
8. Geng Yang, Li Xie, M. Mantysalo, Jian Chen, Fredrik Jonsson, Hannu Ten-hunen and Li-Rong Zheng. “Bio-Patch Design and Implementation Based ona Low-Power System-on-Chip and Paper-based Inkjet Printing Technology”.IEEE Transactions on Information Technology in Biomedicine (T-ITB), Vol.16, No.6, pp. 1043-1050, Nov. 2012.
9. Geng Yang, Jian Chen, Li Xie, Jia Mao, Hannu Tenhunen and Li-RongZheng. “A Hybrid Low Power Bio-Patch for Body Surface Potential Mea-surement”. IEEE Transactions on Information Technology in Biomedicine(T-ITB), 2012 (second-round review with minor revision).
Conference Papers
10. Jian Chen, Fredrik Jonsson, Li-Rong Zheng, Mats Carlsson, Charlotta Hedenasand Dian Zhou. ”Quantitative Comparison of 1/f Noise Upconversion inCMOS LC Oscillators”. Proc. the 8th IEEE Swedish System-on-Chip Con-ference, Arild, Sweden, May 4-5, 2009.
11. Jian Chen, Fredrik Jonsson and Li-Rong Zheng. “A Fast and AccuratePhase Noise Measurement of Free Running Oscillators Using a Single Spec-trum Analyzer ”. Proc. the 28th IEEE Norchip Conference, Tampere, Fin-land, pp. 1-4, Nov. 15-16, 2010.
12. Jia Mao, Sarmiento M, D., Qin Zhou, Jian Chen, Peng Wang, Zhuo Zou,Fredrik Jonsson and Li-Rong Zheng . “A 90nm CMOS UHF/UWB asymmet-ric transceiver for RFID readers”. Proc. IEEE European Solid-State CircuitsConference (ESSCIRC 2011),Helsinki, Finland, pp. 179 - 182, Sept. 12-16,2011.
13. Chen Yao, Fredrik Jonsson, Jian Chen and Li-Rong Zheng. “A high-resolution Time-to-Digital Converter based on parallel delay elements”. Proc.IEEE International Symposium on Circuits and Systems (ISCAS 2012),Seoul,Korea, pp. 3158 - 3161, May 20-23, 2012.
14. Geng Yang, Jian Chen, Fredrik Jonsson, Hannu Tenhunen, Li-Rong Zheng.“A Multi-Parameter Bio-Electric ASIC Sensor with Integrated 2-Wire DataTransmission Protocol for Wearable Healthcare System”. Proc. Design Au-tomation & Test in Europe (DATE 2012),Dresden, German, pp. 443 - 448,March 12-16, 2012.
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15. Geng Yang, Jian Chen, Fredrik Jonsson, Hannu Tenhunen, Li-Rong Zheng.“Bio-chip ASIC and printed flexible cable on paper substrate for wearablehealthcare applications”. ACM Proc. Of the 4th International Symposium onApplied Sciences in Biomedical and Communication Technologies (ISABEL2011), Article No. 76, Oct. 2011.
16. Geng Yang, Jian Chen, Fredrik Jonsson, Hannu Tenhunen, Li-Rong Zheng.“A 1.0 V 78 µW reconfigurable ASIC embedded in an intelligent electrode forcontinuous remote ECG applications”. Proc. IEEE Engineering in Medicineand Biology Society (EMBC 2009), pp.2316-2319, Minneapolis, USA, Sept.3-6,2009.
17. Geng Yang, Jian Chen, Fredrik Jonsson, Hannu Tenhunen, Li-Rong Zheng.”Intelligent electrode design for long-term ECG monitoring at home: Pro-totype design using FPAA and FPGA”. Proc. the IEEE 3rd InternationalConference on Pervasive Computing Technologies for Healthcare (Pervasive-Health 2009), pp.1-4, Apr. 2009.
18. Geng Yang, Jian Chen, Fredrik Jonsson, Hannu Tenhunen, Li-Rong Zheng.”An ASIC Solution for Intelligent Electrodes and Active-Cable used in aWearable ECG Monitoring System”. Proc. International Conference onBiomedical Electronics and Devices (BIODEVICES 2009), pp.209-213, Jan.2009.
19. Geng Yang, Jian Chen, Ying Cao, Li-Rong Zheng, ”A Novel Wearable ECGMonitoring System Based on Active-Cable and Intelligent Electrodes”. Proc.IEEE 10th international conference on e-Health Networking, Applications andServices (Healthcom08). 2008.
20. Geng Yang, Ying Cao, Jian Chen, Hannu Tenhunen, Li-Rong Zheng, ”AnActive-Cable Connected ECGMonitoring System for Ubiquitous Healthcare”.Proc. IEEE 3rd International Conference on Convergence and hybrid Infor-mation Technology (ICCIT08), 2008.
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Chapter 1
Introduction
Cloud Computing
Internet
Figure 1.1: Communication based networking.
Modern technologies have shaped our living style considerably. As one notice-able example, the Internet plays an important role in our daily life as shown inFigure 1.1. It connects people, personal computers (PCs) and mobile devices to-gether allowing them to interact with each other real time, resulting in a smallerworld. It has been reported that there are 2.3 billion global Internet users in 2011 asillustrated in Figure 1.2. The ubiquitous idea evolved from the internet is Internet-of-Thing (IoT) [2], which connects all uniquely identifiable objects (things). TheIoT technology has been applied in different fields such as smart home, food track-ing, intelligent shopping and remote health care.
Wireless communication is one of the backbone technologies for IoT, which
5
Figure 1.2: Internet user worldwide.
has been widely used for the interaction among PCs, mobile phones, servers, tagsand readers. Useful data are both acquired and transferred wirelessly. Radio-Frequency (RF) transceiver System-on-Chips (SoCs) [3] are the key player to fulfillcontemporary wireless communications such as GSM, Bluetooth, Zigbee, UWB,WiFi, WCDMA, WiMax, LTE and so on. The demand to design a general RFtransceiver leads to the concept of software defined radios (SDRs) [4]. The SDRscan be programmed to meet most of applications, demonstrating high functionalityand flexibility.
Micron
0.001
0.01
0.1
1
10
1
10
100
1000
10000
nm
1970 1980 1990 2000 2010 2020
Figure 1.3: Minimum feature size trend for Intel microprocessor technologies [1]
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Arising at the end of 1950’s, integrated circuits (ICs) have been embedded intoeach corner of the society. According to Moore’s law [5], the number of transistorson a IC will double approximately every two years, as in shown Figure 1.3. However,the size of tranditional Complementary Metal Oxide Semiconductor (CMOS) tran-sistors will one day reach atomistic and quantum mechanical physics boundaries,and new materials and device structures are needed to extend the scaling [6, 7]. Onthe other hand, there is an another trend called More than Moore (MtM) [8] hav-ing been followed by the global semiconductor industry. As to MtM, added valuesare fulfilled by integrating more functionalities onto the die (SoC) or the package(System-in-Package, SiP). The functionalities can include MEMs, image sensors,power devices and RF blocks and so on, which do not necessary scale according toMoore’s Law.
The topic of this theis covers the related design issues of fully-integrated CMOSRF transmitters for wireless communication applications.
1.1 Digitally-intensive RF Design
D/A
InterfaceQ
I
Digital Signal Domain Analog Signal Domain
Digital RF
Figure 1.4: Digital polar transmitter with the D/A interface before antenna.
One enabling techology for SDRs is to digitize RF circuits making them all-digital or digitally-intensive. The digital RF design illustrates high programmabilityand can be integrated together with digital baseband. It enjoys shortened redesigntime and performance improvements when processes are down-scaling, as it relieson the timing performance of transistors not the voltags.
Due to the analog real world, analog signals can not be totally removed in RFtransceivers. Hence the technology direction toward digital RF transceivers is tomove digital-to-analog (D/A) interface closer to antennas, as shown in Figure 1.4where most of signal processing in an all-digital polar transmitter is accomplishedin digital domain and only analog signals appear in the interface.
The goal of this thesis project is to achieve a RF all-digital transmitter, whichshould be highly programmable, compact and low power. It begins with the keybuilding blocks such as oscillators and phase locked loops (PLLs) and then comesto transmitter system design.
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1.2 Thesis Investigation Scope
(a) (b) (c)
IBIAS IBIAS IBIAS
VBIAS
Figure 1.5: The die photographs and simplified schematics of (a) LC-tank VCOwith the tail noise filter, (b) LC-tank VCO with a tail capacitor and (c) pulse-waveor class-C VCO.
The content of the thesis is organized in the order of bottom-up design hierarchy,starting with oscillators, followed by ADPLLs and finally a transmitter. The theo-retical work is validated by both simulation and measurements of three oscillatorsin 0.18-µm CMOS, one ADPLL in 90-nm CMOS and one all-digital transmitter in90-nm CMOS.
8
TX Building Block: oscillator
Oscillators are one of the key building blocks in communication systems whose phasenoise determines the overall performance. For a phase modulated scheme, phasenoise damages phase information contained in carriers increasing the receiver biterror rate (BER) and it also contaminates the down-converted information throughreciprocal mixing. Phase noise has received a great attention in the literature forexample about model [9–15] and about phase noise reduction [16–25].
The first part of this thesis concerns phase noise reduction techniques in RFCMOS integrated oscillators. There are two topologies that can be adopted inCMOS integrated oscillator designs for low phase noise application: Colpitts andLC-tank. The LC-tank oscillators is discussed in this thesis since it is widelyadopted in both academia or industry and shows better phase noise performancein the 1/f2 region [26]. Three different LC-tank oscillators have been designed andtaped out in 0.18 µm CMOS process as shown in Figure 1.5 to investigate how coredevice sizing, different noise filter techniques and different topologies will impactthe phase noise performance and power consumption.
To evaluate the oscillator design the widely adopted Figure-of-Merit (FoM) [27]in the literature is defined as phase noise normalized by power and frequency:
FoM(∆f) = L (∆f)− 20log (fo/∆f) + 10log (PDC) |mW (1.1)
where L (∆f) is phase noise at the offset frequency ∆f from the carrier fo and PDC
is power consumption in mW unit.
TX Building Block: ADPLL
Oscillators usually operate in the presence of a PLL in order to provide a clocksignal with accurate frequency. Traditionally PLLs are analog designs where analogsignals circulate within the loop. For an analog PLL, especially the one with apassive integrated loop filters, a large silicon area is needed. With process scalingthe analog design will also suffer from lower voltage headroom.
The motivations for saving silicon area, easing control and system integration,shortening redesign time and improving performance when process scaling makeall digital PLLs (ADPLLs) in Figure 1.6 [28–31] being the new trend in futureradio applications. The design is mixed-signal including both RF analog circuitsand digital standard cells. All analog features of the building blocks in ADPLLsare terminated at the interface even though they are analog internally. Only thehigh frequency blocks such as digital controlled oscillator (DCO) and time-to-digitalconvertor (TDC) are custom-designed while rest of the system is digital standardcell implementation enjoying the digital design automation. The ADPLL designwith fine tuning DCO and direct frequency modulation (FM) is the second part ofthe thesis.
9
+Loop
FilterFCW +
-Σ
TDC & Σ
CKV
Digital Std Cell Design
(MHz)
RF Custom Design
(GHz)
NI+F
NI+F
REF
CKR
CKRΣ: Phase Accumulator
FCW: Frequency Control Word
(a)
(b)
Figure 1.6: (a) the ADPLL block diagram and (b) the die photograph.
ADPLL based All-digital Polar TX
Based on the investigation made on the building blocks, a whole RF transmittercan be built. The proposed RF transmitter is digitally-intensive as illustratedbriefly in Figure 1.7. Compared to the conventional analog RF transmitter, signalsare processed in the digital domain. All information is encoded into the timing
10
7
1
2
3
5
4
98
6
900 µm
ADPLL1-bit
∆Σ
Passive
FilterPhase θ
Envelope ρ
Digital Signal Domain Analog Domain
PM AM Class-D PA
(a)
(b)
AND
Shaper
Figure 1.7: The all-digital TX die photograph and the block diagram.
of waveforms such as the zero-crossing instants and the pulse density instead ofvoltage amplitudes. It demonstrates high programmability and is a compact designsuitable for SoC integration.
1.3 Thesis Organization
In Chapter 2, phase noise definitions and the relation between phase noise andjitter are discussed. Followed by how phase noise propagates in systems and howto derive the phase noise specification from different requirements. Finally a fastand simple free-running oscillator phase noise measurement method is proposed.
11
In Chapter 3, different phase noise reduction methods for LC-tank oscillators arediscussed and large signal behaviors are examined. Different noise sources and theirphase noise conversion process are analyzed based on a time-variant method. Thenthe impact of device sizing on 1/f2 and 1/f3 phase noise are discussed and designimplications are concluded. Class-C or pulse-wave VCOs are proposed demonstrat-ing low phase noise and power consumption. The design procedure to obtain aquick start point is briefly discussed, which is based on a first-order analysis.
In Chapter 4, the topics first cover the different models for analyzing the con-tribution of different noise sources in ADPLLs. Then quantization noise, spurioustone and ill condition are discussed. Finally a frequency tuning scheme with a smallstep size and the relevant measurement method are proposed.
In Chapter 5, we present an all-digital transmitter based on ADPLL and phasesynchronized ∆Σ modulator. It covers the operation principle, the phase path andamplitude path.
In Chapter 6, we summarize the thesis and briefly introduce the included papers.
1.4 Included Papers and Contribution
Seven papers are included. In the following, we summarize the included papers andthe authors’ contributions.
Oscillator optimization: device sizing
• Paper 1. Jian Chen, Fredrik Jonsson, Li-Rong Zheng, Hannu Tenhunen andDian Zhou. “Sizing of MOS device in LC-tank Oscillators”. Proc. the 25thIEEE Norchip Conference, Aalborg, Denmark, pp. 1-6, Nov. 19-20, 2007.
• Paper 2. Jian Chen, Fredrik Jonsson, Mats Carlsson, Charlotta Hedenas,Dian Zhou and Li-Rong Zheng. “Device Sizing and 1/f2 Phase Noise inCMOS LC-tank Oscillators”. Manuscript.
• Paper 3. Jian Chen, Fredrik Jonsson, Mats Carlsson, Charlotta Hedenasand Li-Rong Zheng. “Flicker Noise Conversion in CMOS LC Oscillators: Ca-pacitance modulation dominance and core device sizing”. Journal of AnalogIntegrated Circuits and Signal Processing, vol. 68, no. 2, pp. 145-154, Aug.2011.
There are different opinions in the literature concerning core device sizingin LC-tank oscillators. The investigation in Paper 1 and paper 2 are aimedto clarify the different opinions. The relationship between 1/f2 phase noiseand core device sizing are examined based on closed-form expressions andintuitive explanations are given. Design implications are concluded, whichare confirmed by measurement results of seven different width VCOs. Thenoise transfer functions are adopted to intuitively explain how different noisesources attack the LC-tank and hence induce phase noise.
12
Several 1/f noise up-conversion in oscillators have been proposed in the liter-ature, however their relative weight is still under investigation. This informa-tion is important, since a certain 1/f noise suppression methods can mitigatethe effect of one up-conversion mechanism but may increase the effects of oth-ers. Hence the dominant one should be identified. Paper 3 distinguishes therespective impact of different 1/f noise up-conversion mechanism by using asystematic simulation method in order to facilitate oscillator design in termsof reducing 1/f3 phase noise. It demonstrates that capacitance modulationdue to parasitic capacitance is the dominant mechanism, which leads design-ers to minimizing parasitic capacitance for a low 1/f3 phase noise oscillator.This conclusion is validated by measuring fourteen VCOs with different coredevice size and a little different topology.
Oscillator optimization: Pulse-wave (class-C) oscillator
• Paper 4. Jian Chen, Fredrik Jonsson, Hakan Olsson, Li-Rong Zheng andDian Zhou. “A Current Shaping Technique to Lower Phase Noise in LC Os-cillators”. Proc. 15th IEEE International Conference on Electronics, Circuitsand Systems (ICECS), Malta, pp. 392-395, Aug. 31-Sept. 3, 2008.
• Paper 5. Jian Chen, Fredrik Jonsson, Mats Carlsson, Charlotta Hedenas andLi-Rong Zheng. “A Low Power, Startup Ensured and Constant AmplitudeClass-C VCO in 0.18 µm CMOS”. IEEE Microwave and Wireless ComponentsLetters, vol. 21, no. 8, pp. 427-429, Aug. 2011.
Besides sizing device properly and increasing Q-value of LC-tanks anotherway to reduce phase noise is the topology improvement. Paper 4 proposes amodified topology calling PW-VCO or class-C VCO where the drain current isshaped into a pulse wave, so it generates a larger fundamental tone under thesame bias current compared to conventional LC-tank oscillators (LC-VCOs).Closed-form equations are derived, showing that PW-VCOs can achieve atheoretic minimum phase noise reduction of 3.9 dB. Including the reductionin bias noise, the total phase noise reduction can be in the range of 5-10 dB.
The class-C VCO may suffer from a startup difficulty since the gate biasvoltage is lowered (NMOS VCO case) to fulfill the class-C operation. An au-tomatic bias voltage control loop is also proposed to obtain a robust design.The stable amplitude is achieved during the whole tuning range by an inher-ently stable digital amplitude control loop. Paper 5 demonstrates the designdetails of both the bias voltage loop and the digital amplitude control loop.Measurement results of the design in a 0.18 µm validates the proposed ideas.
ADPLL based all-digital polar transmitter
• Paper 6. Jian Chen, Liang Rong, Fredrik Jonsson and Li-Rong Zheng. “All-digital transmitter based on ADPLL and phase synchronized delta sigma
13
modulator ”. Proc. IEEE Radio Frequency Integrated Circuits Symposium(RFIC),pp. 1-4, Jul. 2011.
• Paper 7. Jian Chen, Liang Rong, Fredrik Jonsson, Geng Yang and Li-RongZheng. “The Design of All-Digital Polar Transmitter Based on ADPLL andPhase Synchronized ∆Σ Modulator ”. IEEE Journal of Solid-State Circuits,vol. 47, no. 5, pp. 1154-1164, May 2012.
The digitally-intensive RF demonstrates several advantages such as high flexi-bility or programmability, high integration and performace improving with processscaling. On the other hand analog intensive design will be trapped in a dilemmawith scaling where the continousely lowered voltage leads to insufficient voltageheadroom. Paper 6 proposes a digitally-intensively RF transmitter. It is a po-lar topology based on ADPLL and one-bit low-pass ∆Σ modulator. Only analogwaveform appears at the last stage after on-chip filter. It is the interface betweenthe digital transmitter and antenna. Paper 7 demonstrates the design detail ofeach building block of the digital transmitter. Measurements of the design in a90nm CMOS process validates the concept and shows good performance in powerefficiency and silicon area.
14
Chapter 2
Phase Noise and Jitter
2.1 Definition and Metrics
Phase Noise
Noise is stochastic process, making signal behavior non-deterministic. As one sortof noise, phase noise [9–11, 13, 15, 32] gives rise to the non-deterministic behaviorof signal phase. In the frequency domain, an ideal sinusoidal signal (vo(t) = Ao ·cos(2πfot)) has all power concentrated at one frequency (fo) as shown in Figure2.1(a). However when corrupted by phase noise, its power is spread to the neighborfrequency as “skirt” or “tail” shown in Figure 2.1(b). The degree of spreadingindicates the level of phase noise.
(a) Ideal Case
fo
(b) Real Case
fo
Ao·cos(2πfo·t + φ(t) )Ao· cos(2πfo·t)
1Hz
∆f
a dB
Figure 2.1: Phase noise in the frequency domain
The signal contaminated by phase noise can be expressed as
vo(t) = Ao · cos(2πfot+ ϕ(t)). (2.1)
17
where (ϕ(t)) is phase error. Phase noise is characterized by the power spectraldensity (PSD) Sϕ of the phase error ϕ(t). However, it is not able to measure Sϕ
directly using spectrum analyzers without the assistance of phase detectors [33–37],hence the normalized single-side-band (SSB) PSD of the signal vo(t) is commonlyused for instead in both the industry and the academia to characterize phase noise:
L(∆f) =Svo(fo +∆f)
po(2.2)
where Svo is the PSD of vo(t), po is the power of vo(t) and ∆f is the offset frequencyfrom the carrier frequency fo. The unit is dBc/Hz where dBc means it is normalizedto the power of the carrier. For example, the signal shown in Figure 2.1(b) yields−a dBc/Hz phase noise at ∆f offset frequency from the carrier fo.
For RF CMOS integrated oscillators, there are three regions of interest in thenormalized SSB PSD as shown in Figure 2.2.
Offset Frequency (Hz)
Ph
ase N
ois
e (
dB
c/H
z)
0
Noise Floor
(Buffers or instruments)
-20dB/decade
(thermal noise induced)
-30dB/decade
(1/f noise induced)
Figure 2.2: Normalized single-side-band(SSB) PSD
When ϕ(t) << 1 and at the moderate frequency offset1, there is a relationshipbetween phase noise Sϕ and the normalized SSB PSD L(∆f):
L(∆ω) =1
2· Sϕ(∆ω) (2.3)
The derivation process of this relationship can be found in Appendix A.
1The moderate frequency offset is where the phase noise component of Svo dominates overthe amplitude noise component.
18
tPD
tPD+Js
as bs
as
bs
as
bs
Ideal Case
Real Case
ba
To To To
To+J1
PDF: Probability density function
tPD: Nominal propagation delay
To: Nominal period
tPD
Real Case
To
Ideal Case
tPD
To
(a) Synchronous Jitter (b) Accumulated Jitter
To+J2 To+Jn
Figure 2.3: Synchronous jitter and accumulating jitter
Jitter
Phase noise is a quantity in the frequency domain when examined in the timedomain its equivalent is called jitter. Jitter causes non-deterministic behaviors ofsignals in the timing events such as the transition across a certain threshold.
For oscillators or PLLs, there are two types of jitter of interest: synchronousjitter and accumulated jitter [38]. Synchronous jitter shows up in driven circuitswhere the output transition is the direct response of the input transition. The inputis taken as a reference when calculating synchronous jitter. Synchronous jitter is thevariation of the delay between the input transition and the corresponding outputtransition as illustrated in Figure 2.3(a).
On the other hand, accumulated jitter exists in autonomous systems where thereis no input and the current output transition depends on the previous output tran-sition. It takes the previous timestamp as a reference. Hence the timing uncertaintyaccumulates along with time like a random wander, as shown in Figure 2.3(b).
Relation of Phase Noise and Jitter
Phase noise and jitter convey the same information but expressed in different do-mains. Therefore it is intuitive that they are convertible to each other. Synchronousjitter relates to the flat region of the phase noise spectrum (noise floor in Figure2.2), while accumulated jitter relates to the 1/f2 region with a -20 dB/decade slope
19
as in Figure 2.2 if it is assumed that both jitter are caused by a white Gaussianstationary or T-cyclo-stationary random process [38].
The equation relates the accumulated jitter ja and 1/f2 phase noise is
L(f) = 1
2Sϕ(f) =
1
2(2πfo)
2Sja(f) (2.4)
where Sja is the PSD of accumulated jitter. This equation is based on the fact that
ϕ(t) = 2πja(t)
To= 2πfoja(t) (2.5)
The synchronous jitter js is related to the noise floor Lo as
js = To/2π ·√
Lo · fo (2.6)
More information about how to derive the above equations can be found inAppendix B.
2.2 Phase Noise Propagation in Systems
In order to calculate phase noise at the output of systems, it is necessary to un-derstand how phase noise propagates in different blocks such as buffers, frequencydividers, frequency multipliers and mixers. We will discuss them in this section.
High order phenomenons are discarded in this first order analysis such as theAM-to-FM conversion or the frequency folding [37]. Although some informationwould be lost, the intuitive analysis establishes a reasonable baseline needed for thesystem design stage by merely hand calculation.
Buffers
Buffers are used [39] to isolate oscillators from other noisy circuits that degradesphase noise performance. Different kinds of buffers can be used depending onapplications, such as the open drain buffer [40], the rail-to-rail buffer [41], andself-biased buffer [42]. Under the assumption that buffers are noiseless devices,the phase noise gain of buffers is unit, meaning the timing variation at the inputwill be transferred to the output without any amplification as shown in Figure 2.4.In reality, output phase noise shows a higher level and buffers can often be thedominating source of noise at large frequency offset [10, 13, 15].
20
Noisless
BufferJ1 J2 J3 J4
vout(t)vin(t)
J1 J2 J3 J4
Jitter: Jout = Jin
Phase Noise: ∆φout = Jout·2π·fout= Jin·2π·fin= ∆φin
Figure 2.4: Phase noise propagation in buffers.
Frequency Dividers
Frequency dividers are widely used in frequency synthesizers and transceivers. Fora division ratio N , only one of N clock cycles is passed to the output while N -1clock cycles are swallowed. During the time when the input is passed to the output,the same amount of the timing variation at the input will appear at the output.Since the output frequency is 1/N the frequency of the input, the resulting phasevariation at the output is 1/N of that at the input [37] as shown in Figure 2.5.
J1 J2 J3 J4
vout(t)vin(t)
Frequency
Divider
1/N
N=2
Jitter: Jout = Jin
Phase Noise: ∆φout = Jout·2π·fout= Jin·2π·fin/N
= ∆φin/N
J1 J3J2 J4
Figure 2.5: Phase noise propagation in frequency dividers.
Frequency Multipliers
For frequency multipliers with the ratio N , the amount of the timing variation atthe output is kept the same. However the output frequency is N times smaller thanthe inputs, phase variation at the output is N times larger than that at the input,as shown in Figure 2.6
21
vout(t)vin(t)
Frequency
Multiplier
N
N=2
Jitter: Jout = Jin
Phase Noise: ∆φout = Jout·2π·fout= Jin·2π·fin·N
= ∆φin·N
x
J1 J3J2 J4 J1 J2 J3 J4
Figure 2.6: Phase noise propagation in buffers.
Mixers
For mixers the output demonstrates the phase variation either equal to the sub-traction or summation of the phase variations of two inputs due to their behaviors[43, 44], as shown in Figure 2.7. If these two inputs are independent to each other,phase noise at the output will be the sum of phase noise of the inputs. On theother hand, if the two inputs show some correlation, the output phase noise can behigher or lower than the sum of input phase noise depending on the phase relationof two inputs.
xMixer
vin1(t), ∆φin1
vin2(t), ∆φin2
vout(t), ∆φout=∆φin1±∆φin2
Figure 2.7: Phase noise propagation in mixers.
2.3 Phase Noise Requirement of Oscillators
From Reciprocal Mixing Effects
Phase noise will cause reciprocal mixing effects in receivers as shown in Figure 2.8.It occurs when a weak desired signal is accompanied by a strong interferer or ablocking signal at a small offset frequency ∆f . Because of phase noise (”tail” orside band) of local oscillators (LOs), the interferer is also down-converted to thefrequency band of interest, decreasing the signal-to-noise (S/N) ratio.
Given the received signal power Psig, the interference power Pint and the min-imum signal-to-noise ratio S/N required at the output of mixers, the LO phasenoise L(∆f) requirement can be estimated [39]. The power of the desired signalafter down-conversion can be expressed as PsigGmixer where Gmixer is the conver-
22
sion gain of down-conversion mixers. The power of the down-converted interfereris PintGmixer. Due to LO phase noise, the sideband of the down-converted interfererwill appear in the frequency band of interest with the power of PintGmixerL(∆f)BWwhere BW is the noise bandwidth. With the above equations the phase noise re-quirement can be derived:
S/N = 10logPsigGmixer
PintGmixerL(∆f)BW(2.7)
L(∆f)|dB = Psig|dB − S/N |dB − Pint|dB −BW |dB (2.8)
fIF+fo fo
∆f∆f
x
Mixer
fIF
Signal
Interference
In-band noise
Down-converted Signal
Noisy LO
Down-converted
Interference
Figure 2.8: Reciprocal mixing.
From RMS Phase Error
Phase noise causes symbol points in a constellation diagram to spread from the idealposition on the angular axis as shown in Figure 2.9(a). When the phase spread (orphase error) is large enough to cross the symbol boundary as illustrated in Figure2.9(b), the bit error occurs. From the statistics point of view, the phase spreadcan be characterize by the probability density function (PDF) as shown in Figure2.9(c).
23
For wireless communication links the bit error rate (BER) is an important mea-sure of the quality of service (QoS). BER is the ratio of bits received in error tobits sent correctly. Phase noise is one of the contributors to BER and is related toit through RMS phase error as
ϕrms =
√
∫ fH
fL
2 · 10L(∆f)/10df (2.9)
where L(∆f) is SSB normalized phase noise at the offset frequency ∆f in dBc/Hz.One key relationship is that the RMS phase error is identical to the standarddeviation (σ) of the phase error. So given the RMS phase error and the digitalmodulation scheme, the number of σ needing to cross the symbol boundary can becalculated and hence the probability of the bit error can be calculated by integratingthe area of the PDF from the minus infinity to the symbol boundary as shown inFigure 2.9(c).
Perr(v < a) =
∫ b
−∞
PDF (v)dv (2.10)
Symbol Boundary
22.5o
Symbol
Boundary
σ
µ
σ
b
(a)
(b) (c)
v
b
Figure 2.9: (a) 8PSK Constellation, (b) symbol boundary and (c) probability dis-tribution function
24
From TX Leakage
PA
LNA
BPF
Circulator
Figure 2.10: TX leakage in a RFID reader.
The non-ideal isolation between the RX chain and the TX chain in transceiverscauses part of the transmitted power to leak into the RX chain, degrading perfor-mance such as noise figure. The TX chain and the RX chain are connected througha duplexer with finite isolation and can operate simultaneously. Take the RF iden-tification (RFID) systems with passive tags as an example. As seen in Figure 2.10,the reader receives the back-scattered information from tags and transmits power (acontinuous wave signal from the LO at the same frequency) to tags simultaneously.Besides the high isolation requirement of duplexers, it also places a requirement onLO phase noise specification.
PA
LO
CH2
Leakage
CH3CH1
Figure 2.11: TX leakage to adjacent channels.
For another kind of TX leakage, the transmitted power leaks into adjacent chan-nels due to phase noise as in Figure 2.11. Especially in a narrowband applicationlike the GSM with 200 kHz channel, this leakage imposes a strict specification onphase noise.
2.4 Fast Oscillator Phase Noise Measurement
As mentioned in Section 2.1, the real phase noise of a sinusoidal signal
vo(t) = Ao · cos(2πfot+ ϕ(t)) (2.11)
25
is the PSD Sϕ of phase error ϕ(t). When ϕ << 1 and at the moderate offsetfrequency, L(∆f) (the SSB normalized PSD of vo(t)) is used to represent phasenoise Sϕ, as there is a relationship as indicated by Equation 2.4 which is repeatedhere:
L(f) = Sϕ(f)
2(2.12)
X Spectrum
PLL
DUT
Reference Phase detector
(mixer)
(a) Phase Decter
Delay Line
ɸ
X Spectrum
90o
90o
(b) Frequency discriminator
Figure 2.12: Phase noise measurement.
The SSB normalized phase noise is easier to be measured using spectrum analyz-ers. There are several conventional methods to measure phase noise of free-runningoscillators such as 1) a PLL based system to lock oscillators to a clear reference[33–35] as in Figure 2.12(a); 2) a delay line as frequency discriminators [35] as inFigure 2.12(b); 3) injection locking oscillators to a clear reference [36]. Some extracomponents are needed for all those methods such as clean stable reference sourceswith the same frequency (GHz) of oscillators under test, double balanced mixers,multiple long delay cables and low pass filters, which makes these methods a littlebit expensive. For the injection locking method [36], the locking bandwidth shouldbe as small as possible in order to read close-in phase noise directly. Within the
26
locking bandwidth, phase noise of the oscillators under test is suppressed so thatsome post-processes [36] are needed to retrieve original phase noise.
In order to make a fast and simple setup without losing accuracy, we proposeda measurement method as published in our paper [45]. It only uses a modern spec-trum analyzer without other assistant components. The basic idea is to calculatephase noise based on the measured I and Q data of the free-running oscillator out-put. The I and Q data are acquired by the spectrum analyzer and stored in itsembedded memory. With the I/Q data, the instantaneous phase is calculated usingthe expression:
ϕ = actanI
Q= actan
sin(ϕ)
cos(ϕ)(2.13)
Then the phase variation away from the ideal phase is calculated. Phase noise isthe PSD of the phase variation.
This method is simple and fast which is validated by measurements [45]. Thelimitation of how close-in phase noise can be measured depending on the long-termfrequency instability or frequency drift of the oscillator under test and the size ofthe embedded memory. Also noise of spectrum analyzers should be small enoughcompared to oscillators under test.
27
Chapter 3
Phase Noise Optimization for
CMOS LC Oscillators
Phase noise of oscillators impacts the performance of the whole radio front-end. Italso consumes a large proportion of system power. That’s why researchers have beencontinuing to pay their efforts to reduce both phase noise and power of oscillatorssuch as [10, 11, 13–15, 17–27, 32, 46–55].
In this chapter, LC-tank oscillators are covered. First, the large signal behaviorsare discussed. Second, the phase noise sources and their conversion mechanismswith time-variant operation points are handled. Based on these analyses, phasenoise optimization by device sizing and an improved topology (pulse-wave or class-C oscillator) are presented. Finally a hand calculation based design procedure fora start point is presented.
3.1 Large Signal Analysis
Start Oscillation
Oscillators are autonomous circuits, demonstrating positive feedbacks at certainbias conditions. It can generate continuous periodic signal without any input exceptnoisy DC bias. For the LC-tank oscillator in Figure 3.1, the nominal oscillationfrequency (fo) is determined by the equivalent tank inductance (Ltank) and theequivalent tank capacitance (Ctank)
1 as
fo =1
2π√Ltank · Ctank
(3.1)
1The harmonic-rich drain current will change the oscillation frequency indicated by (3.1)known as Groszkowski effect [56]. This effect is neglected here without affecting the validation ofthe following analysis.
29
Ibias
Vdd
vs
vg1 vg2id1 id2
M1 M2
Ctank
Ltank
Rp
+ vo -n p
Figure 3.1: A simplified schematic of an all-PMOS LC-tank oscillator
IB
Vdd
vs
H(s)
FeedBack
+ H(s)noise=
+
X(s) Y(s)
Figure 3.2: The feedback contained in a LC-tank oscillator
Both Ctank and Ltank include the parasites from active devices and metal inter-connections of the layout.
To understand the oscillation of LC-tank oscillators, it is examined as a feedbackcircuit shown in Figure 3.2:
Y (s)
X(s)=
H(s)
1 +H(s)(3.2)
30
t
IB
t
vg1(t)
∆t
0
0
Voltage
Current
Ao
id2(t) id1(t)
E
vg2(t)
vs(t)
vth,pDevice Off
Figure 3.3: The steady-state time domain waveforms of the drain current, thecommon-source voltage and the gate voltage.
If there is a frequency ωo and so = jωo, the open loop gain H(s) meets the followingconditions
|H(so)| ≥ 1 (3.3)
6 H(so) = 180o (3.4)
then self-oscillation can happen. Since the closed-loop feedback becomes positive,the small noise signal at ωo can be amplified infinitely. These two conditions arethe Barkausen creteria, which are necessary [46] but not sufficient for oscillation.The oscilation frequency from the Barkhausen creteria agrees with (3.1).
Though the LC-tank oscillator can start oscillation when |H(so)| = 1, it isbetter to design |H(so)| as 2 or 3 in reality to make sure it can oscillate under allprocess, voltage and temperature (PVT) variations.
Voltage Waveforms
In steady state the common-source node (vs) is assumed as virtual ground and theoutput voltage (vo) is sinusoidal2. The bias current (IB) is switched completelybetween two cross-coupled switch pair devices (M1 and M2), leading to the drain
2It is assumed that the Q-value of LC-tanks is so high that the output voltage waveform issinusoidal.
31
n
Vc
Switched Capacitor Unit
p
vM(t)
t0
Voltage
AM
vM(t)
(a)
(b)
n p
AC Ground
Ron
1
2Ron
1
2
C1 C1 C1 C1
Equivalent
Vc=VDD
vM(t)
Figure 3.4: The schematic of the switched capacitor unit cell.
current with a near rectangular shape. Figure 3.3 illustrates the time domainwaveforms. The switch pair devices are turned off when the gate-source voltage(vg-vs) is smaller than the threshold (vth,p) as the shadowed area in Figure 3.3.
The output voltage vo = vg2 − vg1 is the gate-drain voltage of the switch pairdevices. High amplitude can cause reliability problem of the switch pair devices,which should be taken in account at design stage.
The switched capacitor bank is usually based on the unit cell [57] as shown inFigure 3.4(a). When the control signal Vc = VDD, the voltage swing (Figure 3.4(b))at the node M can cause the PN junctions of drain-substrate and source-substrateto be positively biased. The swing (AM ) at M is
AM =1
2Ao
1
Qc + 1(3.5)
where Ao is the differential oscillation amplitude, Qc = 2/(ωoC1 ·Ron) is the qualityfactor of the half branch when Vc = VDD as shown in the right of Figure 3.4(a). Although AM is small 3, oscillator designers should be aware positive biased PNjunctions may appear.
32
Vo(t)
Γ(t)
(a)
(b)
0
0
Figure 3.5: (a) Tank voltage and (b) the ISF of active devices.
3.2 Phase Noise Sources and Conversion Mechanisms
Phase noise of oscillators has been widely studied in the literature using lineartime invariant (LTI) analysis [58], linear timing varying analysis (LTV) [11, 49] orrigorous mathematical analysis [14]. Osicllators are time-varying systems, so LTVmodels are more accurate compared to LTI ones.
Due to the intuitive feature, the LTV model - impulse sensitive function (ISF)[11, 12] is utilized here. The ISF describes how much phase shift is resulted whena unit current impulse is injected into one node of oscillators at a certain instantof one period. Figure 3.5(b) shows the ISF of active devices (switch pair devices)of LC-tank oscillators. As seen, oscillator phase is more sensitive to device noisewhen the tank voltage (Figure 3.5(b)) is at zero-crossing instants A.
Given the noise current (n2/∆f) and the associated ISF (Γ), induced phase
3Because Ron is usually small in order not to lower Q-value of LC-tanks, so most of the voltageis dropped over the capacitor C1
33
noise can be calculated as [11, 12]
L(∆ω) = 10log
(
i2n∆f
Γ2rms ·
1
2q2max∆ω2
)
. (3.6)
where Γrms is the root mean square (RMS) of Γ, ∆ω is the offset frequency fromωo and qmax is the maximum charge swing at the node where the noise current isinjected. When the noise current is injected over LC-tanks, qmax = Ao · Ctank (Ao
is the oscillation amplitude and Ctank is the total capacitance in LC-tanks).
The second term in (3.6) 1/(2q2max∆ω2) is same for different noise current in-jecting the same node, so we only examine the first term (It is called effective noise[24]) in the following discussion:
Neff = Γ2rms · i2n/∆f. (3.7)
IB
Vdd
vs
id1 id2
M1 M2
Ctank
Ltank
Rp
+ vo -n p
itank
itail
Vn,m1 Vn,m2
io
Figure 3.6: The different phase noise contributions in the LC-VCO.
34
Cyclo-stationary Noise
The cyclo-stationary noise in(t) can be expressed as a stationary part ino multipliedby a noise modulation function (NMF) α(t):
in(t) = ino · α(t). (3.8)
For the oscillator attacked by cyclo-stationary noise, it is taken as the stationarypart ino attacks the oscillator with an effective ISF Γeff [11]:
Γeff = Γ · α(t). (3.9)
where Γ is the ISF associated stationary noise.
LC-Tank
As to noise (i2tank/∆f) from the LC-tank loss as shown in Figure 3.6, the associatedISF can be approximated as the first-order derivative of the normalized outputvoltage [11, 26]:
Γtank(t) = sin(2πfot) (3.10)
So the RMS of Γtank is 1/2 and the effective noise of LC-tanks is
Neff,tank =1
2· i
2tank
∆f(3.11)
Tail Devices
When the bias current IB is incorporated with a small signal noise itail as IB + itailas in Figure 3.6, the differential output current Io injecting the LC-tank can beapproximated using first-order Taylor expansion as
Io(t, IB + itail) = Io(t, IB) +∂Io∂IB
· itail = Io(t, IB) +Gtail(t) · itail (3.12)
where
Gtail(t) =∂Io∂IB
(3.13)
is the tail noise modulation function (NMF) describing how tail current noise ispropagated to LC-tanks. Figure 3.7(b) illustrates the waveform of Gtail.
So that the effective ISF (Figure 3.7(c)) of i2tail/∆f is [11]
Γtail(t) = Gtail(t) · Γtank(t) (3.14)
The effective noise of tail noise i2tail/∆f is
Neff,tail = ΓRMS,tail · i2tail/∆f (3.15)
where ΓRMS,tail is the RMS of Γtail.
35
t
Gtail(t)
1/2
-1/2
0
Гtail(t)
Гtail(t) = Гtank(t)·Gtail(t)
Гtank(t)
To
To
To/2
Larger Width M1,2
Larger Width M1,2
To/2
∆t
(b)
(c)
t
Vo(t)
Ao
-Ao
0
ToTo/2
(a)
Figure 3.7: (a)Output voltage, (b) tail noise modulation function - Gtail and (c)effective tail noise ISF - Γtail. ∆t is the conduction time.
Switch Pair Device
Switch pair drain noise is modeled as input-referred gate voltage noise (vn,m1 andvn,m2) as shown in Figure 3.6. As the switch pair devices are switched on and offperiodically, vn,m1 and vn,m2 are the cyclo-stationary noise expressed as
vn,m1(t) = vno,m · αm(t) (3.16)
where vno,m is the stationary part of the cyclo-stationary noise and αm(t) is thenoise modulation function.
By using the similar first-order analysis as in the above section, the differential
36
t0
Larger Width M1,2
Гtank(t)
Gsp(t)
t0
Larger Width M1,2
Гsp(t)
Гsp(t) = Гtank(t)·Gsp(t)
t
Vo(t)
Ao
-Ao
0
ToTo/2
(b)
(c)
(a)
Figure 3.8: (a) Output voltage, (b) switch pair noise modulation function - Gm and(c) effective tail noise ISF - Γsp. ∆t is the conduction time.
output current Io (Figure 3.6) in the case of switch pair noise can be approximated
Io(t, vo + vn,m1 + vn,m2) = vo(t, vo) +∂Io∂vo
· (vn,m1 + vn,m2) (3.17)
37
Inserting all the expressions in (3.17), 3.17 can be simplified as
Io(t, vo + vn,m1 + vn,m2) = vo(t, vo) +
√
∂Io∂vo
· vno,m (3.18)
Hence the cyclo-stationary switch pair noise can be taken as the stationary noisevno,m with the noise modulation function (Gsp):
Gsp(t) =
√
∂Io∂Vo
(3.19)
Then the effective ISF of i2sp/∆f is [11]
Γsp(t) = Gsp(t) · Γtank(t) (3.20)
Figure 3.8(b) illustrates the waveform of Gsp. The effective noise of switch pairnoise is
Neff,sp = ΓRMS,sp · v2no,m/∆f (3.21)
where ΓRMS,sp is the RMS of Γsp.
3.3 Device Sizing for 1/f 2 Phase Noise
The impact of core device sizing on phase noise is discussed in this section. Threephase noise contributors as tail noise, switch pair noise and LC-tank noise areexamined respectively.
Tail Noise
As shown in Figure 3.7(a), the tail noise modulation function has the same periodas the oscillator, meaning the tail noise components around even harmonics arefolded to the vicinity of the fundamental tone at the LC-tank producing phasenoise. This can also be seen from the effective ISF in Figure 3.7(c) where it showshalf period of the oscillator and thus only contains power at even-order harmonics.
The noise modulation function peaks when only one of the switch pair FETs isON, meaning all tail noise injects and perturbs the LC-tank. On the other handwhen both of the FETs are ON, the noise modulation function is small or evenzero (at the equilibrium point A) , because only the differential part of drain noisecurrent produces phase noise. Therefore there is an intuitive induction to lowertail phase noise that the switch pair devices should switch slowly or the time whenonly one switch pair device is ON should be reduced. It is verified in Figure 3.7(c)where the dotted line is the case of larger switch pair width. As ssen the smallerthe width the smaller phase noise is, as 1/f2 phase noise depends on the RMS valueof the effective ISF (or the curve encompassed area) in Figure 3.7(c).
As seen in Figure 3.7(c), the effective ISF Γtail is a odd harmonic functionwith a zero DC value, meaning no low-frequency noise is up-converted. It is not
38
true in reality, as the tail current source is usually the dominant 1/f3 phase noisecontributor [22]. This discrepancy comes from the assumption of the tank ISF in(3.10) and hence Γtail is not an odd harmonic function in reality.
Switch Pair Noise
The noise modulation function for switch pair noise (Figure 3.8(b)) has a periodtwo times of the oscillator, so that noise around the fundamental tone and otherodd harmonics are folded and produces phase noise. This property is also demon-strated by the effective ISF Γsp in Figure 3.8(c), since it only contains power at thefundamental tone and odd harmonics.
From Figure 3.8(b) when only one switch pair FET is ON, no noise is output andthus no phase noise, which is similar to the noise rejection mechanism in a cascadedconfiguration where output noise is dominated by tail current devices other thancascaded devices. It seems we should reduce the time when both devices are ONor have a fast switch by increasing the width of switch pair devices. However, thisaction will increase the peak of Gsp as shown in Figure 3.8(b). These two effectscancel each other, making the RMS of Γsp approximately same, so sizing switch pairdevices has weak impact on the phase noise contribution of switch pair themselves.
LC-tank Noise
Noise of the passive components in the LC resonator attacks the LC-tank directly,which is also not impacted by sizing of switch pair FETs [17]. To reduce its phasenoise contribution, a method is to improve the Q-value of the LC-tank.
Sizing Strategy for 1/f2 Phase Noise
Based on the above discussions, phase noise due to LC-tank loss and switch pairFETs are relatively independent of the width of switch pair FETs and phase noisedue to tail noise is positively dependent on it, therefore the width should be min-imized for the optimal design as long as other design constraints are not violatedsuch as the oscillator start-up constraint. Especially in the case when tail noiseis the dominant contribution, the minimum switch pair width should be adopted.The sizing strategy is discussed and validated by measurements in our includedPaper 1 [23] and Paper 2.
Besides phase noise consideration, minimizing the width also help to increasethe tuning range, since it reduces the parasitic capacitance from switch pair devices.
3.4 Sizing for 1/f 3 Phase Noise
1/f3 phase noise is caused by flicker noise or 1/f noise of CMOS devices. There areseveral up-conversion mechanisms as shown in Figure 3.9 to cause low frequencyflicker noise to appear in the 1/f3 region of phase noise.
39
M1 M2
Vbias
Ctail
CM node
Cvar=f(vnois)
Cfixed
2fo
2
3
1
io
io
Figure 3.9: Flicker noise up-conversion mechanism.
1. Harmonic modulation or Groszkowski effect [17, 56]: flicker noise from tailFETs and switch pair FETs modulates the harmonic content of differentialoutput current going into LC-tanks and hence modulates the oscillation fre-quency causing phase noise.
2. Capacitance modulation: tail flicker noise is up-converted to AM noise aroundthe oscillation frequency fo by switch pair devices and then causes phase noisethrough AM-to-FM conversion [49]; tail flicker noise and switch pair flickernoise modulate the equivalent capacitance of tail capacitance (at common-mode node) seen by LC-tanks and hence modulates the oscillation frequencyresulting in phase noise [17].
3. Common-mode modulation: tail flicker noise is up-converted to 2fo at thecommon-mode node by the channel length modulation effect of tail devicesand then the up-converted flicker noise is down-converted to around fo atLC-tanks by switch pair devices resulting in both AM noise and FM noise[50].
Several up-conversion mechanisms account for low frequency flicker noise up-converted to be 1/f3 phase noise. Different mechanisms can have different weightson phase noise contribution. A certain suppression method to mitigate one up-conversion mechanism may increase the effect of others, hence it is better to dis-tinguish their relative weights and find the dominate one.
We perform a two-step simulation in our included paper 3 [59] in order todistinguish their respective impacts: without device parasitic capacitance and with
40
Ibias
Vdd
vs
vg1 vg2id1 id2
M1 M2
Ctank
Ltank
Rp
+ vo -n p
Ctail
Vbias
Figure 3.10: The schematic of PW-VCO.
device parasitic capacitance. Without device parasitic capacitance, the harmonicmodulation and the common-mode modulation are the only two mechanisms4 fornoise up-conversion. Comparing the results of each step, it has been demonstratedthat the capacitance modulation is the dominant mechanism, which implies activedevices should have small size to reduce the parasitic capacitance. This conclusionhas been validated by measurements of fourteen VCOs in 0.18-µm CMOS in theincluded paper 3 [59].
3.5 Pulse-wave or Class-C Oscillator
1/f2 phase noise of LC-VCOs can be expressed as [18, 26]:
LLC(∆ω) ∝(
1
Q2· 1
Psig· FLC
)
(3.22)
FLC = 1 + γ + ηtail (3.23)
4There is no varactor in the simulated VCO, so the non-linear parasitic capacitance of activedevices is the only source of capacitance modulation
41
t
IB
t
vg1(t)
Φ
0
Vbias
Voltage
Current
id2(t)
id1(t)
vg2(t)
vs(t)
vth,p
Device Off
Figure 3.11: The time domain waveform of the PW-VCO.
where Q the Q-value of LC-tanks, Psig the power consumption of LC-tanks and FLC
the noise factor including the contributions of tank loss: 1, switch pair devices: γ,and tail devices: ηtail. If tail noise can be filtered out entirely, the best noise factoris FLC = 1+ γ. Further improvement needs efforts paid on topology improvement.
The pulse-wave (PW) VCO [24, 25, 60], shown in Figure 3.10, is proposed tofurther improve performance. The drain current (Id1 and Id2) are shaped into apulse-wave (Fig. 3.11) so that higher amplitude is obtained under the same DCpower consumption. High frequency tail noise is filtered out by the tail capacitorCtail.
The phase noise improvement can also be explained by the ISF theory [11]:oscillators are most sensitive at the zero-crossing instant of oscillation voltage vo(t)and insensitive at peak instants. The PW-VCO (Figure 3.11) delivers drain currentsto LC-tanks mainly at the time when the oscillator is insensitive and hence smallphase noise is induced.
Start-up Circuits
At the optimal operating point, the bias voltage Vbias may be so large (PMOS oscil-lator case) to cause the oscillator start-up failure. A start-up circuit is introducedas shown in Figure 3.12. The bias voltage is set to 0 when amplitude is small. Aslong as oscillation amplitude is larger than the pre-defined value, the bias voltageis switched to Vop for the optimal phase noise performance.
42
Vbias
A_det
Hysteresis
Comparator
Vref
Amplitude
Detector
0Vop
Figure 3.12: Start-up circuit block diagram
The low pass filter (LPF) is adopted to avoid fast transients in the bias voltagecontrol loop, potentially stopping the oscillation. It can also filter out noise fromthe reference voltage and the switch.
Oscillation amplitude of PW-VCO
Oscillators are designed to operate in the current limited region [13] where theoscillation amplitude is found as
Ao = I1 ·Rp (3.24)
where I1 is the fundamental tone of the output current Io across LC-tanks and Rp
is equivalent LC-tank parallel resistance.The first harmonic is found by Fourier expanding drain current
I1 =1
π
∫ Φ
−Φ
Io(φ) cos(φ)dφ (3.25)
When the drain current is a narrow pulses meaning a small conduction angle Φ.The oscillation amplitude can be approximated [25]:
I1,PW = Ibias (3.26)
This result is identical to the oscillation amplitude of a Colpitts oscillator [26].As to LC-VCOs, the drain current is a near rectangular waveform where the
fundamental tone can be approximated as
I1,LC =2Ibiasπ
(3.27)
43
Parameter Value
Tuning Range 3.0 GHz - 4.2 GHz
Phase Noise -125 dBc/Hz @ 1-MHz offset from 3.6 GHz
Power Consumption 4 mA from 1.2 V supply
Table 3.1: Example oscillator spec
So that pulse-wave VCOs produce an amplitude of 1.57 (=π/2) times higherthan that of LC-VCOs, i.e. the reduction of 3.9-dB phase noise.
The detailed analysis and relevant measurements of pulse-wave VCOs with anautomatic start-up loop and a digital amplitude control are presented in our in-cluded paper 4 [25] and paper 5 [45].
3.6 Hand Calculations for a Start Point
Given the requirements of oscillators as shown in Table 3.1, quick hand calculationscan be done to obtain a start point for further optimization. For the LC-tankoscillator as shown in Figure 3.1, these calculations give rise to rough estimationof the size of the transistors (M1,2), the amount of bias current (IB), the values ofthe differential inductor (L) and the total capacitance (C).
For a first-order analysis, phase noise equations based on time-invariant assump-tions can be used. Since the negative resistance (Rn) provided by cross-coupledswitch pair devices exactly cancel the loss of the parallel resistance (Rp) of LC-tanks at the oscillation frequency ωo
5, i.e. Rn = −Rp, the impedance of LC-tanks(Figure 3.1) at the frequency ωo +∆ω can be simplified as
z(ωo +∆ω) =1
1/Rn + 1/Rp + j(ωo +∆ω)C + 1j(ωo+∆ω)L
(3.28)
=1
j(ωo +∆ω)C + 1j(ωo+∆ω)L
(3.29)
≈ Rpωo
j2Q∆ω(3.30)
where Q is the Q-value of the LC-tank equal to Rp · ωoC = Rp/ωoL. The aboveequation is simplified based on the relationship of 1
xo+∆X ≈ 1xo
− ∆x 1x2o
when
∆x << xo.According to the definition, normalized SSB phase noise is the PSD of noise
voltage normalized by signal power as
L(∆ω) = 10 · log(
|z(ωo +∆ω)|2 · i2n/∆f
2 · v2sig
)
(3.31)
5It is assumed that it is at steady state with constant amplitude.
44
where i2n/∆f the PSD of noise current and v2sig the mean square value of signalvoltage. 1/2 means half of the noise power causes phase noise [44].
Noise currents include the contributions of the LC-tank loss Rp and active de-vices, which can be expressed using a noise factor F :
i2n∆f
= F · 4kT/Rp (3.32)
Inserting (3.32) into (3.31), we can get
L(∆ω) = 10 · log(
ω2o
Q2∆ω2
kTF
2Psig
)
(3.33)
where Psig = v2sig/Rp = A2o/(2Rp) and Ao is the amplitude of the voltage across
LC-tanks.
Design Step
Oscillator design involvs several trade-offs and often require a long optimizationprocedure. In the following discussion we derive an initial design as the start pointfor further improvement based on hand calculations.
First it is assumed that the Q-value of LC-tanks as Q = 10 (there is no problemto achieve a Q-value larger than 10 in nowadays CMOS processes.), the noise factorF = 3 and temperature T = 300 K (27o).
1) Given the phase noise requirement in Table (3.1) that L(1 MHz) ≤ −125dBc/Hz at 3.6 GHz and (3.33), we can obtain
Psig ≥ 2.55 mW
2) Given Psig = A2o/(2Rp), Ao = 4/π · IB ·Rp
6 and IB = 4 mA, we get
Rp ≥ 196.04 Ohm
3) GivenQ = Rp/(ωoL) = RpωoC, we have the total inductance and capacitanceof the LC-tank:
L ≥ 0.87 nH
C ≤ 2.26 pF
4) The proper start-up margin is necessary, so that the loop gain should largerthan unit as gm ·Rp/2 ≥ 1:
gm ≥ 10.2 mS
5) Since gm =√
µnCoxIB ·W/L =√
KnIB ·W/L where Kn = µnCox7, we
obtainW
L=
g2mKn
6It is assumed the oscillator operates in current-limited region [13].7Where µn is the mobility of charge carriers and Cox is the gate capacitance per unit length.
45
After the above five steps we obtain a quick start point. Although some as-sumptions and first-order analysis are adopted, it gives a reasonable estimation ofnoise performance. Further refinements are performed using simulators.
46
Chapter 4
Quantization Noise and Spurs in
ADPLL
All-digital Phase Locked Loops (ADPLLs) have attracted great attention in theliterature [30, 31, 61–81]. It makes use of the timing resolution of CMOS tran-sistors instead of the voltage resolution, so that the CMOS process scaling-downleads to performance improvements due to faster devices. It can also save siliconarea, shorten redesign time and enhance high programmability and integration-level, since most of the building blocks are pure digital such as loop filters, phasedetectors and so on. On the contrary, analog PLLs encounter several design diffi-culties with process scaling due to lower voltage headroom and higher leakage.
4.1 Introduction
The ADPLL shown in Figure 4.1(a) works in a similar way as analog ones [37, 82–84]. The phase detector (PD) compares the phase of the reference clock (REF)ΦR and that of the digital controlled oscillator (DCO) clock (CKV) ΦV , and theresulting phase error Φe is feed back to the DCO to control its frequency untilit being locked. The difference lies in that all the signals are expressed as finite-length digital numbers instead of analog values, which allows use of the digitalsignal processing.
The reference phase ΦR is estimated by the reference phase accumulator (RPA)by counting in CKR clock with an increment of FCW (frequency control word) ineach clock as shown in Figure 4.1(b). The DCO phase ΦV includes two parts. Theinteger part ΦV,I is estimated by the variable phase accumulator (VPA) as shownin Figure 4.1(b). The fractional part ΦV,F is estimated by the TDC as shown inFigure 4.1(c). The VPA counts in CKV clock with an increment of 1 in each clock.When locked, the DCO frequency is FCW times of the reference clock CKR.
As to noise performance, ADPLLs are not contaminated by noise and spurioustones originating from charge pumps as in the case of analog PLLs where the charge
49
+Loop
Filter
FCW +
-
1
Σ
REF
+
TDC
CKR
CKR
CKV
Phase Decter
ΦR
ΦV =ΦV,I - ΦV,F
Φe
Σ : Accumulator
FF : D Flip Flop
FCW : Frequency Control Word FF Σ
Variable Phase
Accumulator (VPA)
Reference Phase
Accumulator (RPA)
VPA
RPA
ΦV,F
ΦV,I
ΦR
ΦV,I
FFREF
CKV
CKR
CKV
REF
TDC ΦV,F = 4/6
(a)
(b) (c)
1
FCW = 4
0 CKR
Figure 4.1: (a) Block diagram of ADPLLs and (b) phase accumulators and (c) thefractional variable phase
pump is usually the dominant contribution of performance degradation. The AD-PLL is constituted by a linear phase detector and noise-immune digital circuits. Aslong as the quantization induced phase noise can be suppressed, ADPLLs are thepreferred option in the contemporary fully integrated radio systems, illustratinghigh programmability or flexibility for multi-mode applications and high compact-ness for SOC integration.
There are two quantization scenarios in ADPLLs: phase estimation and oscil-lator frequency tuning as shown in Figure 4.2. Time-to-digital converters (TDCs)are used to reduce the quantization effect in phase estimation and Σ∆ modulatorsare commonly used to alleviate frequency tuning quantization. Special frequencyfine tuning schemes [85–88] can also help to lessen frequency tuning quantization
50
+ LPF(s)
KDCO/s
ΦV
ΦR
Φe+
-
x
FCW
1. Phase Quantization
2. Frequency Tuning
Quantization
Figure 4.2: Quantization noise in ADPLL
issues. As the CMOS process scaling down, both the resolution of TDCs and fre-quency tuning will be improved making the ADPLL be a promising candidate forRF applications compared to its analog counterpart.
4.2 ADPLL Noise Analysis: s-domain, z-domain and
Time-domain
s-domain
x x++ LFP(s) +
KDCO
2. Φn,fres
2π/S
1. Φn,TDC
1/2πFCW
ΦR ΦV
ΦE+
-
Figure 4.3: S-domain model of the ADPLL
All building blocks of an ADPLL have digital interface, though some of themsuch as DCOs and TDCs are internally analog and custom-designed but their analogfeatures are terminated at their interfaces. Hence signals are processed or encodedin the digital domain. The s-domain model can still be used to predict the ADPLLbehaviors as long as the concerned offset frequency is much lower than that of thesampling frequency i.e. the reference clock REF [62, 84]. The s-domain model isproposed in [62, 63], reorganized in Figure 4.3.
The unit of KDCO in the Figure 4.3 is Hz/second, so there is a 2π in the modelof the DCO to represent the conversion from frequency (Hz) to phase (Radian).There is a 1/2π after the phase detector (PD) to make the phase error be an unit-
51
less digital number. In the following discussion it is assumed LPF (s) = α, so thatit is a first-order type-I PLL loop.
The closed-loop noise transfer function of TDC quantization noise is
Hcl,TDC(s) =1
1 + s/α ·KDCO(4.1)
It illustrates a low-pass feature with the 3-dB cut-off frequency at αKDCO/2π Hz.The roll-off is 20 dB/decade. So there are two ways to suppress TDC quantizationnoise: 1) reduce loop bandwidth and 2) improve TDC resolution. The first methodis to suppress the conversion and the second one is to suppress noise source itself.
The noise transfer function for reference clock noise is
Hcl,Fref (s) =FCW
1 + s/α ·KDCO(4.2)
It is also a low-pass function with the 3-dB cut-off frequency at αKDCO/2π Hz andthe roll-off of 20 dB/decade.
As seen, both reference noise and TDC quantization noise show up within theADPLL band. Hence it is better to make a narrow band PLL if they are thedominant in-band noise contributions. In most case TDC quantization noise con-tribution is much higher than reference noises within the frequency range from kHzupto the ADPLL bandwidth [88]. At low frequency offsets, for example < 1 kHz,reference noise becomes the dominant contribution.
The noise transfer function of DCO frequency tuning quantization noise is
Hcl,Fres(s) =2π
α ·KDCO
1
1 + s/α ·KDCO(4.3)
It is a low-pass function with the 3-dB cut-off frequency at αKDCO/2π Hz and20-dB/decade roll-off. The contribution to phase noise can be reduced by using∆Σ modulators to push quantization noise to high offset frequency [30, 63] or otherspecial varactor design [85–88] to reduce the tuning step size. The impact of thisquantization noise is usually smaller than TDC quantization noise [63].
The noise transfer function of DCO phase noise is
Hcl,Fres(s) =s/α ·KDCO
1 + s/α ·KDCO(4.4)
which demonstrates a high-pass function with the 3-dB cut-off frequency at αKDCO/2πHz and 20-dB/decade roll-off. Note that from the oscillator phase noise point ofview, the ADPLL band should be as wide as possible. As expected there is a trade-off between DCO noise suppression and TDC noise suppression, hence it is usefulto make the ADPLL bandwidth programmable in order to achieve the near optimalperformance. Due to the digital feature, the ADPLL bandwidth can be easily madeprogrammable by changing the gain of digital loop filters using shift registers.
52
z-domain
The z-domain model is accurate [62, 89] for the digital systems as ADPLL, as shownin Figure 4.4.
x + LFP(z)
KDCO
FCW
∆fV/fVΦE+
-
1/(1+z)
1/(1+z)
∆fR/fR
Figure 4.4: Z-domain model of the ADPLL
The z-domain model can be related to the s-domain by the following approxi-mation [62]:
z = es/fR = ej2πf/fR ≈ 1 + s/fR (4.5)
which results in
s = fR(z − 1) (4.6)
Since the s-domain model is straightforward to use and it is well approximatedwithin the frequency of interest. The s-domain analysis is adopted in this work.
Time-domain
The s-domain model is a linear model with high-order effects ignored. The s-domain model can be used in early design stages to quickly check the feasibilityof specifications and figure out the bottleneck of performance. On the other handtime-domain models [90–92], which include high-order effects such as quantization,TDC nonlinearity, DCO tuning nonliearity and so on, should be utilized to predictthe real performance of ADPLLs.
Since signals are digital in ADPLLs, the time-domain model can be fulfilledusing hardware description language such as Verilog and VHDL. The time-drivensimulators can be adopted to perform simulation, saving simulation time consider-ably.
Digital building blocks can be modeled in both register-transfer level (RTL)level or behavioral level depending on the trade-off between speed, accuracy andcomplexity. The RF analog building blocks such as TDCs and DCOs are modeledbehaviorally.
As the most importance parameter in DCO, phase noise is modeled as jitter [38,63, 90]. 1/f2 phase noise of DCOs is modeled as the accumulated jitter. While noisefloor is modeled as the synchronous jitter. Figure 4.5 illustrates simulated phasenoise of the DCO time-domain model where the simulation agrees with modeling.
53
103
104
105
106
107
108
109
1010
−160
−150
−140
−130
−120
−110
−100
−90
−80
−70
−60
Frequency (Hz)
Pha
se N
oise
(dB
c/H
z)
Figure 4.5: Phase noise (1/f2) of a time-domain free-running DCO: -120 dBc/Hzphase noise at 1-MHz offset from the 3.15-GHz center frequency and - 150 dBc/Hznoise floor
As to TDC models, both nonlinearity and quantization effects can be modeledin behavioral models. The nonlinearity is model by making the quantization levelnot equally spanned.
Figure 4.6 demonstrates the simulation results of the ADPLL time-domainmodel with different ADPLL bandwidths.
4.3 Quantization Noise
As mentioned before two quantization effects exist in ADPLLs: phase estimationquantization and frequency tuning quantization as shown in Figure 4.2. TDCscannot resolve the phase smaller than its resolution, leading to the phase estimationquantization. The finite capacitance step size achieved in a CMOS process causesthe frequency tuning quantization in DCOs.
If it is assumed that the variation of quantizer (TDC and DCO here) inputsspans several quantization levels, the power of the resulting quantization noise canbe expressed as (double-sided) [63]
σ2∆ =
(∆)2
12. (4.7)
54
103
104
105
106
107
108
109
1010
−160
−150
−140
−130
−120
−110
−100
−90
Frequency (Hz)
Pha
se N
oise
(dB
c/H
z)
0 50 100 150 200 250 3000
20
40
60
80
100
120
140
160
180
200
Reference Cycle
Pha
se E
rror
Figure 4.6: (a) phase noise and (b) phase error from a time-domain model withdifferent bandwidth: 40 kHz (blue), 100 kHz (gree) and 300 kHz (red). DCOphase nosie: -120 dBc/Hz @ 1-MHz offset and - 150 dBc/Hz noise floor. IdealDCO frequency tuning. Ideal TDC.
55
where ∆ is the quantization step. This noise power is spread up to the half of thesampling frequency( fR the frequency of the reference clock CKR in this case) as
L =σ2∆
fR. (4.8)
When ADPLLs are not yet locked, the previous assumption is always met. Thephase noise contribution of TDC quantization noise is
LTDC =
(
2π∆TDC
TV
)2
/12/fR (4.9)
where ∆TDC is the TDC resolution and TV is the period of DCO clocks.The phase noise contribution of DCO frequency tuning noise is
LDCO = (∆freq)2/12/fR (4.10)
where ∆freq is the frequency step of DCO frequency tuning. The impact of quanti-zation noise of DCOs can be reduced using ∆Σ modulators [63] or special varactordesign [85–88]. As a result the quantization of TDCs is usually the dominant causeof in-band phase noise [63]. It is one of the hot topics in the literature [76, 93–106]to design high performance TDCs with high resolution.
When ADPLLs are locked, the assumption is not valid anymore. The phasevariation or the DCO control word variation is smaller than the quantization level atmost of time. The resulting quantizer output may demonstrate a certain repeatingpattern, leading to spurious tones in the spectrum of the ADPLL.
4.4 Spurious Tones
The quantization of TDCs and DCOs may lead to spurious tones in output spec-trums. The quantization effects (both TDCs and DCOs), phase noise or environ-mental changes cause the DCO frequency to drift away the nominal frequency,producing a certain phase error in each reference clock cycle. Only when the ac-cumulated phase error exceeds the TDC quantization step (∆TDC) can the TDCresolve it and hence activate ADPLL loops to correct the phase error. After thecorrection, ADPLL loops keep quiet again until the new accumulated phase error islarge enough to be resolved by TDCs. In this way, TDC outputs may demonstrate acertain repeating pattern as shown in Figure 4.7, producing spurious tones. Dithermethod can be adopted to suppress this sort of the spurious tones [68, 71–74, 107].It perturbs the phase error in purpose, making it crossing the TDC quantizationlevel more frequently. If the introduced perturbation noise degrades performancetoo much then noise cancellation methods should be utilized [68, 71, 73, 74] at thecost of design complexity.
The non-linearity of TDCs is also the cause of spurious tones [107]. Thesespurious tones are located at the offset frequency usually lower than the spurs
56
0 500 1000 1500 2000
Reference Clock Cycle
Ph
ase E
rro
r c
od
e
Figure 4.7: Phase error code demonstrating a certain pattern.
caused by TDC quantizations since the impact of the TDC non-linearity can onlyshow up when the TDC inputs traverse the whole TDC dynamic range, which needsmore number of reference clock cycles. The DCO clock CKV rotating method isproposed in [107] to address this kind of spurious tones.
4.5 Ill Condition: Steady-state Bandwidth Variation
When the ADPLL is locked, the variation of the phase error may much smaller thanthe TDC resolution, leading to such scenario where the TDC keep quiet at mostof time. Then the gain of the quantizer (the TDC) is not one as being modeled inthe s-domain model in the previous section but smaller than one. This conclusioncan be forecasted by Figure 4.8 where the loop dynamics of the ADPLL are samefor different cuvers and the only difference is TDC resolution. As seen the ADPLLoutput spectrum illustrates a smaller loop bandwidth when the TDC resolution isincreased.
57
103
104
105
106
107
108
109
1010
−160
−140
−120
−100
−80
−60
−40
Frequency (Hz)
Pha
se N
oise
(dB
c/H
z)
5 ps10 ps20 ps40 ps
Figure 4.8: Phase noise when sweeping TDC resolution tres: 5 ps, 10 ps, 20 psand 40 ps. DCO phase nosie: -100 dBc/Hz @ 1-MHz offset. Ideal DCO frequencytuning. The PLL BW: 100 kHz.
4.6 Frequency Tuning Resolution
MASH ∆Σ Modulator
To reduce the phase noise contribution of the discrete frequency tuning of DCOs,one method is using ∆Σ Modulators to push or shape low frequency noise to highfrequency. The shaped noise is then filtered by the 1/s effect of DCOs. The noisetransfer function (NTF) of a n order ∆Σ Modulator is
NTF =(
1− z−1)n
=[
e−j ∆ω
2fdth
(
e−j ∆ω
2fdth − ej ∆ω2fdth
)]n
=
[
e−j ∆ω
2fdth
(
2j · sin( ∆ω
2fdth)
)]n
where fdth is the sampling frequency of ∆Σ Modulators.The spectrum of frequency tuning quantization noise (4.10) is shaped by the
NTF and then the DCO’s 1/s effect. Hence the phase noise contribution is
Ldth(∆f) =∆2
freq
12
1
fdth
(
2sinπ∆f
fdth
)2n
· 1
∆f2(4.11)
58
Despite of the 1/s filtering effect, ∆Σ Modulators should be carefully designed inorder to make sure shaped quantization noise do not raise the far-away noise floor[63].
DCO Fine Tuning Bank Resolution
n p
c
wmin=120nm
wmin+∆min=125nm
Mini. Bank Basic Unit
Figure 4.9: Fine tuning arrangement
Another method to get a fine tuning resolution is to use the arrangement as shownin Figure 4.9, which is presented in our included paper 6 [45] and paper 7 [88].There are two devices with a small difference in size used. One is the minimum size(120nm in a 90nm process) allowed in processes. The other is the minimum sizeplus the minimum increment (5nm in a 90nm process). By doing in this way, thecapacitance step is the delta capacitance (30 aF) of these two switched varactors.This method has no noise penalty as ∆Σ Modulators but attention should be paidin the layout stage to avoid mismatch.
59
Spectrum
(b)
Amcos(ωmt)
KDCO
(a)
ωo ωo+ωmωo-ωm
Aocos( KDCOAmcos(ωmt)dt+ωot)∫0
t
∆dB
Figure 4.10: Measurement of the fine tuning step
It is not easy to measure the small tuning step ( around 200 Hz) when DCOsare free-running, since the carrier frequency is drifting due to electronic noise orenvironmental changes. The drifted frequency can be larger than this small fre-quency tuning step. To address the difficulty, the narrow band modulation theoryis explored. The tuning control of the DCO is modulated by a sinusoidal waveform(Amcos(ωmt)) 1 as shown in Figure 4.10(a). In the spectrum there are two side-bands around the main carrier as indicated in Figure 4.10(b). The power difference(∆dB) between the sidebands and the carrier is related to the tuning step KDCO
of the DCO as
KDCO =10
∆dB20 2fmAm
(4.12)
The detailed information about ADPLL fine tuning design and measurements canbe found in the included paper 6 [45] and paper 7 [88].
1The peak value of the sinusoidal wave is chosen to be smaller enough so that only the finetuning bank is active.
60
Chapter 5
Direct Digital-RF Polar
Transmitter
90o
+ LPF
PA
I
Q
PA
PLL
I
Q
a
θ
0
Polar Coordinate
x
y
θ
a
PLL
(b)
(a)
a·cos(ωot+θ)
a·cos(ωot+θ)
Suppress Harmonics
Figure 5.1: (a) The polar transmitter and (b) the quadrature (IQ)transmitter
For RF transmitters polar architecture (Figure 5.1(a)) [31, 45, 88, 108–112] is
63
an effective solution in terms of the number of components (die area) and powerefficiency, compared to quadrature (IQ) transmitters (Figure5.1(b)). No mixer isneeded since frequency up-conversion is accomplished by PLLs, eliminating theharmonics caused by mixers. Switching mode power amplifiers (PAs) can be usedinstead of linear mode PAs, which are able to achieve higher efficiency. Especiallyin the contemporary wireless protocols with orthogonal frequency-division multi-plexing (OFDM) schemes the high peak-to-average power ratio (PAPR) lowers theefficiency of the linear PAs considerably. The LO pulling issue can also be relaxedin polar transmitters since LOs and PAs demonstrate the same frequency modu-lation. The I/Q mismatch problem is also eliminated. However, challenges lie inAM/PM path delay mismatch [113] and baseband spectral expansion [114, 115].
In this chapter, we introduce briefly an all-digital polar transmitter based onan ADPLL and an phase sychronized ∆Σ modulator, which was published in ourincluded paper 6 [45] and paper 7 [88]. All modulation is completed in the dig-ital domain illustrating digital waveforms. The only analog signals appear at theinterface to die pads where a band-pass analog filter suppresses shaped quanti-zation noise and acts as both a matching network and differential-to-single-endedconversion.
5.1 Contemporary Transmitters: more digital
3500
CDMA 800
700
Freq
(MHz)1200 1700 2200 2700 3200
CDMA 1
CDMA 2
WCDMA850
GSM 1800
GPRS
EDGE
HSPA
LTE
TD-SCDMA
Bluetooth
WiFi
WiMax
GPSL2
GPSL1
GSM 1900
GSM 800
GSM 900
UMTS
CDMA 2000
WCDMA 850, UMTS 850
Figure 5.2: Mobile standards
Several mobile communication standards exist nowadays in the frequency rangefrom 700 MHz to 3500 MHz, as shown in Figure 5.2. The need of covering multiplestandards from the market leads to the transmitters with high programmability orflexibility in frequency selection (from 700 MHz to 3500 MHz), modulation scheme
64
(GMSK, QPSK, QAM and so on) and output power level (more than 10 dB backoff). Those programmabilities are relatively easy to fulfill in the digital domain ordigitally-intensive transmitters.
On the other hand, CMOS process down-scaling brings several difficulties totranditional analog designs such as reduced voltage head room and high leakagecurrent. Hence long redesign time is needed to move analog designs toward anadvanced process. However, digital circuits can benefit from the scaling in terms ofspeed, matching, power consumption and integration level. As far as process scalingis concerned, more digital circuits1 or digital signal processing should be adoptedin RF transmitters to replace analog circuits [31]. So the technology direction forRF transmitters is to move digital signal processings closer to antennas.
(a)
Band Pass
Σ∆ MODBaseband RF
4fo
Low Pass
Σ∆ MODBaseband
RF
fo
AND
RF-DACBaseband RF
fo
(b)
(c)
Figure 5.3: The frequency up-conversion in digital transmitters
In the literature several digitally intensive transmitters have been proposed,based on polar architecture [30, 31, 45, 88, 109, 112] or IQ [114, 116–119] architec-ture. Low-pass or band-pass ∆Σ modulators are widely used in digitally intensivetransmitters to push quantization noise away interesting bands. The frequency up-conversion function of mixer can be achieved by band-pass ∆Σ modulators (Figure5.3(a)), however the modulator should operate at higher frequency than the carrierfrequency usually four times higher [112, 116]. For the architecture with low-pass
1Digital circuits here means both standard cells or analog circuits with the digital interface.
65
∆Σ modulators the frequency up-conversion is fulfilled by mixers that can be sim-ple AND gates (Figure 5.3(b)) [88, 112] or multiplexers [116]. Other researcherscombine the functions of analog mixers and digital-to-analog converters (DACs),yielding the RF-DAC (Figure 5.3(c)) solution [120–122]. All the up-conversionmethods in Figure 5.3 take baseband signals directly without the need of DACs.For the architecture with ∆Σ modulators, switching mode PAs can be used toachieve high power efficiency.
5.2 The Proposed All-digital Polar Transmitter
For RF transmitter design there are several aspects needed to be taken into accountsuch as LO pulling, spectral purity and power efficiency.
LO Pulling
The LO pulling is caused by PAs with large power transmission and certain mod-ulation. It pulls LOs away the nominal frequency. One solution is to operate LOsat a frequency far away from PAs frequency [39]. For polar transmitters the LOpulling issue is mitigated since the LO is also modulated as PAs instead of providinga fixed frequency carrier.
Spectral Purity
The spectral purity means the output spectrum should be confined within certainrange. The impact to adjacent channels due to harmonics, spurious tones 2 andnoise floor should be minimized. Adjacent-channel power rejection (ACPR) is usedtoo evaluate the spectral purity [123]. As far as PAs are concerned, the linearityperformance should be optimized to increase spectral purity or reduce spectralregrowth[124].
Power Efficiency
The power efficiency is one of the most important parameters for PA designs. Forconstant envelop modulation applications, linear PAs are used. The efficiency oflinear PAs is reduced considerably when the envelop is varying and hence switchingmode PAs are preferred in this case.
Proposed All-digital Polar Transmitter
The proposed all-digital polar transmitter is shown in Figure5.4. The spectralpurity performance is improved by the combination of an one-bit ∆Σ modulator
2Harmonics are generated by modulators and PAs while spurious tones are from mixers, os-cillators, parasitic resonator and nonlinearity in PAs [39].
66
Digital Base
Band
Envelope
ρ
dθ
dt
Phase
θ
DCODigital
PLL
Loop
ADPLL
Low Pass
Σ∆ MOD
Class-D
PA
SD
CKVD
CKVD
CKV
Pulse
ShaperTrim.
Delay
Vdiff
Phase
Modulation
Amplitude
ModulationP
N
∆t
Matc
hin
g &
Filte
r
Figure 5.4: The proposed all-digital polar transmitter
and an switching mode class-D PA. The switching mode PA can be regarded asa linear stage for digital signals [125]. Hence the linearity of the transmitter isdetermined by the ∆Σ modulator. A well-designed one-bit ∆Σ modulation is linear[126] which assures the linearity property of the proposed transmitter and hence thespectral purity. As to the power efficiency, the switching mode PA demonstratesbetter efficiency compared to its linear counterparts.
The operation principle of the proposed transmitter in Figure 5.4 is explainedas follows. Phase information θ modulates the carrier frequency directly throughthe ADPLL. The output of the ADPLL CKV is a phase modulated clock. The∆Σ modulator performs amplitude modulation by taking CKV as an oversamplingclock so that the output SD is phase synchronized to CKV except a fixed delay tPD
caused by the propagation delay of the ∆Σ modulator as shown in the waveforms ofCKV and SD in Figure 5.5(a). SD contains both phase and amplitude information.However the power around the carrier frequency fs or fCKV is still quite low whilemost of the power is located at the baseband as shown in Figure 5.5(b). To increasethe power at fs, a pulse shaper (AND gate) is used acting as mixers to upconvertthe baseband power to fs. The delay tPD between the transition edges of SD andCKV should be compensated before the pulse shaper, otherwise power efficiencywould be lowered and more harmonics would be produced. This is accomplishedby the delay block (Trim. Delay in Figure 5.4). As seen in Figure 5.5(c), the poweraround fs is raised after the use of the pulse shaper. The H-bridge arrangement orthe differential style further increase the power around fs by 3 dB in the ideal caseand suppress the power at DC and other odd harmonics as shown in Figure 5.5(d).
67
CKVD
SD
P = CKVD & SD
Vdiff = P - N
N = CKVD & SD
CKVD
Vout
BPF
Freq.
signal
alias
0 2fsfs=fCKV
Freq.0 2fsfs=fCKV
On-chip
filter
Freq.0 2fsfs=fCKV
CKV
q. noisesinc
tPD
(a)
(b) The spectrum of SD
(c) The spectrum of P and N
(d) The sepctrum of Vdiff
Figure 5.5: The operation of the proposed all-digital polar transmitter
As the last stage, the band-pass filter removes shaped quantization noise and theharmonics, generating the final analog output Vout as shown in Figure 5.5(a).
68
5.3 Phase Modulation: ADPLL with two-point modulation
+ Σ
TDC & Σ
+ α FCW
y[k]
+
-
+Σ
TDC & Σ
+ αFCW
y[k]
+
-
1
NG
+ Σ
TDC & Σ
++ αFCW
Two point
Modulationy[k]
+
-
(a)
(b)
(c)
BW
BW
BW
BW BW
+
∆f[i]
∆f[i]
∆f[i]
Figure 5.6: The two point modulation scheme of the ADPLL
As mentioned before, phase or frequency modulation is accomplished by theADPLL. The modulating data is added to FCW (Figure 5.6(a)), resulting in thefrequency modulation of the ADPLL. Based on the z-domain model [62, 89] thetransfer function of the path from y[k] to ∆f [i] is illustrated as
H(z) =αKDCO/(z − 1)
1 + αKDCO/fR · 1/(z − 1)(5.1)
where α is the scale factor, KDCO is the gain of the DCO. As shown in Figure5.6(a), the transfer function shows a low-pass response in the frequency domain,
69
meaning it cannot modulate wideband baseband signals.The two point modulation scheme [30] can be adopted to overcome this limi-
tation. The ADPLL with the two point modulation is illutrated in Figure 5.6(c).The z-domian transfer function of the additional path from y1[k] to ∆f [i] is
H(z) =KDCO
1 + αKDCO/fR · 1/(z − 1)(5.2)
The frequency reponse of the additional path (Figure 5.6(b)) demonstrate a highpass feature shown in Figure 5.6(b).
As long as the cut-off frequency of these two paths can be matched, an all-passfrequency response can be achieved as plotted in Figure 5.6(c).
The z-domain total transfer function is
H(z) =KDCO/NG · (z − 1 + α ·NG)
z − 1 + αKDCO/fR(5.3)
The extra modulation path will introduce a zero which cancels the pole resulting aall-pass transfer function when
NG =KDCO
fR(5.4)
Hence, besides phase noise the modulation accuracy is impacted by the estimationof the KDCO. Several techniques have proposed in the literature to accuratelyestimate KDCO such as the LMS method [127].
5.4 Amplitude Modulation: low-pass ∆Σ modulator
++1
Z - 1U(z)
E(z)
+
-
V(z)
Figure 5.7: The linear z-domain model of the first-order low-pass ∆Σ modulator
Amplitude modulation is performed using a low-pass first-order one-bit ∆ΣModulator. The z-domain model of the ∆Σ Modulator is shown in Figure 5.7. Thesignal transfer function (STF) from U(z) to V (z) is written as
V (z) = U(z) · z−1 (5.5)
70
which shows one clock delay.
The noise transfer function (NTF) of quantization noise E(z) in the Figure 5.7can be expressed as
Q(z) = E(z) · (1− z−1) (5.6)
As expected it demonstrates a high-pass frequency response. Low frequency noiseis pushed out of interesting bands and then suppressed by filters. After replacingz with ej2πfT , the PSD of quantization noise ouput can be expressed
SQ(f) = (2 · sin(πfT ))2 · SE(f) (5.7)
0
2
4
6
8
0.2 0.4 0.60
Normalized Frequency (f/fs)
No
ise T
ran
sfe
r F
un
cti
on
Figure 5.8: The noise shaping function of the ∆Σ modulators with different orders.
The order of ∆Σ Modulators impacts the noise shaping property, causing dif-ferent in-band and out-of-band behaviors as shown in Figure 5.8. In this case,a first-order modulator is chosen since it has simple implementation and meetsrequirements.
As mentioned, the combination of the ∆Σ Modulator with the switching modePA illustrates a linear operation, since the switching PA is linear for digital inputsand the ideal implementation of the ∆Σ Modulator assures the linearity. How-ever, in a real design the linearity can be degraded by device mismatch and otherimperfection [128, 129].
71
5.5 H-bridge Class-D PA Stages and on-chip Matching
Filter
PAD
H-bridge Class-D PA
k
Vdiff
P
N
Vout
Filter & Matching
Figure 5.9: H-bridge Class-D PA Stages and on-chip Matching Filter
The H-bridge or differential style class-D PA stage is adopted as shown in Figure5.9. The differential style can increase the power at the fundamental tone by 3 dBideal (compared to the single-ended method [112]). At the same time the differentialstyle suppresses the DC power and the second-order harmonic, alleviating the on-chip filter requirement. The device size of the class-D PA is optimized for powerefficiency.
The on-chip filter filters out shaped quantization noise and other unwantedharmonics, lessening the contamination to adjacent channels. Digital waveformsare now converted to analog, therefore this filter is the interface between the digitaldomain and the analog domain. It also acts as the matching network between off-chip loads and the transmitter, diminishing the impact of package parasitics. Thedifferential signal is transformed to the single-ended one by this filter.
72
Chapter 6
Summary and Future Work
6.1 Summary
In this thesis, we first study the RF CMOS oscillator phase noise performance opti-mization through core device sizing and topology improvement. Then the ADPLLwith a fine frequency tuning is proposed and the noise analysis is discussed. Fi-nally it presents an all-digital polar transmitter showing a improved architecture.A number of design techniques have been proposed and verified in three oscillatorand one transmitter implementations.
The basics of phase noise and jitter are introduced, and the relation betweenphase noise and jitter , how phase noise propagates in the system and how toderive the phase noise specification are described. A fast phase noise measurementmethod for free running oscillators is proposed. This method is accurate for mostRF integrated oscillators with only the need of a single spectrum analyzer withoutother assistant circuits such as phase detectors, delay lines or mixers.
Phase noise of LC-tank oscillators is optimized through core device sizing.Closed-form expressions are derived based on the linear time-variant (LTV) ISF[11] theory and verified in both SepctreRF simulations and real implementationin 0.18-µm CMOS process. It is concluded that the minimum size of core device(the switch pair devices) is preferable for both 1/f2 and 1/f3 phase noise reductionpurpose.
A modified topology (PW-VCO or class-C) is proposed. The bias noise is decou-pled by tail capacitors. The phase noise contribution due to core devices is reducedas the drain current is shaped into a pulse wave. The PW-VCO demonstrates atheoretic reduction of 3.9 dB in phase noise at 1-MHz offset compared to LC-tankoscillators without considering the reduction of bias noise. Measurements of thedesign in a 0.18 µm CMOS process illustrates that phase noise can be reduced inthe range of 5-10 dB at 1-MHz offset from different carrier frequency.
The ADPLL with a small frequency tuning step and wideband two-point FM isdesigned in a 90-nm CMOS process. The small frequency tuning step is achieved
75
by making use of the capacitance difference of two transistors with slightly differentwidth (5 nm in 90-nm CMOS process). By doing so the achieved capacitance stepis 30 aF. The small frequency step (around 200 Hz) of the free-running oscillatoris measured based on the narrow-band frequency modulation theory in order toconquer the frequency drift problem.
An improved transmitter architecture is proposed based on the designed AD-PLL and a phase synchronized ∆Σ modulator. It is a polar transmitter with thedifferential H-bridge class-D PA stages. The ADPLL with high programmability isadopted to accomplish the phase noise modulation due to the low noise and low spu-rious output. The amplitude modulation is done by using a first-order low-pass ∆Σmodulator since it is inherently linear, relaxing the need of a complex calibration.The differential H-bridge class-D PA stages increases the power of the fundamentaltone and suppresses the power at DC and even harmonics. The on-chip filter filtersthe quantization noise, converts the differential-end to the single-end and also pro-vides a matching to the antenna. Measurements of the design fabricated in a 90nmCMOS process illustrates this improved architecture achieve good power efficiency,small area with decent modulation accuracy.
6.2 Future Work
One technology direction is digitally-intensive RF design. To go towards it, oscil-lators will be purely digital code controlled instead of analog voltage controlled,becoming a DCO. Phase noise reduction is still a future attempt never ending.Other efforts will be paid on how to achieve a fine frequency tuning step with awide frequency tuning range and how to achieve a linear DCO gain.
For ADPLL design the techniques to reduce different types of spurs and increasethe design automation as well as the high resolution TDC deserves to the furtherinvestigation.
The wideband all-digital transmitter is definitely a very interesting topic sinceseveral challenges are still existing. For example how to achieve a wideband mod-ulation with reasonable modulation accuracy if the polar architecture is adopted,how to keep the efficiency and linearity for PAs driven by high PAPR signals andhow to remove the shaped quantization noise if several standard signals exist si-multaneously.
76
Appendix A
Phase spectral density and voltage
spectral density
At moderate offset frequencies the normalized PSD can well approximate the realphase noise spectrum if the phase variation is small, |ϕ(t)| << 1 rad. With thecondition of a small phase variation, the equation vo(t) = cos[ωot + ϕ(t)] can beapproximated:
vo(t) = cos(ωot)cos[ϕ(t)]− sin(ωot)sin[ϕ(t)]
≈ cos(ωot)− ϕ(t)sin(ωot)(A.1)
where the amplitude noise is ignored and ωo is the carrier frequency.
Now let’s consider the situation when ϕ(t) is a single tone, ϕ(t) = ϕp · sin(ωmt)where |ϕp| << 1. Substitution of ϕ(t) into equation (A.1) gives
vo(t) ≈ cos(ωot)− ϕpsin(ωmt)sin(ωot)
≈ cos(ωot)−ϕp
2{cos[(ωo + ωm)t]− cos[(ωo − ωm)t]}
(A.2)
i.e. the output signal have two side-bands at the frequency of ωo+ωm and ωo−ωm
respectively with a power of ϕ2p/8. Then the normalized phase noise at the frequency
ωo + ωm caused by the single tone ϕ(t) is calculated according to the definition -noise power density normalized to the carrier power as:
L(∆ω) =ϕ2p/8
1/2=
ϕ2p
4(A.3)
As ϕ(t) is a single tone (ϕ(t) = ϕp · sin(ωmt)), the PSD is
Sϕ(∆ω) =ϕ2p
2. (A.4)
79
Together with equation (A.3) and equation (A.4), we obtain the following rela-tion:
L(∆ω) =Sϕ(∆ω)
2. (A.5)
The approximation in equation (A.5) is accurate as long as the phase deviation issmall and the offset frequency ∆ω is moderate.
80
Appendix B
Jitter and phase noise
In this appendix, we are going to discuss the relation among jitter, the noise floor(frequency independent) and 1/f2 phase noise of oscillators.
B.1 Synchronouse jitter and noise floor
Ideal timestamp
Time Error
Distribution
To0 2To
tjs[1]=To+∆t[1]0 tjs[2]=2To+∆t[2]
∆t[2]∆t[1]
Actual timestamp
Figure B.1: Synchronous jitter.
The noise floor is related the synchronous jitter [38, 63] in the time domain.The synchronous jitter occurs in driven systems where the output is the responseof the input. As seen in Figure B.1, the current time error ∆t[i] has nothing to dowith other time errors and the current timestamp tjs[i] equals
tjs[i] = iTo +∆t[i] (B.1)
where To is the period of the ideal input signal.It is assumed the time error is caused by thermal noise or white Gaussian sta-
tionary or T-cyclo-stationary noise process [38]. Given the double-side noise floorL of phase noise curve and the sample frequency fo (fo = 1/To is the frequency of
81
the input), the power of the time error can be expressed as
σ2js = Lfo ·
(
To
2π
)2
(B.2)
where the term To/2π converts a phase error to a time error. Based on the statisticstheory, the RMS value is identical to the standard deviation for white Gaussiannoise and hence the RMS synchronous jitter is
σjs =√
Lfo ·(
To
2π
)
(B.3)
B.2 Accumulating jitter and 1/f 2 phase noise
To
To
Ideal timestamp
Actual timestamp
To0 2To
0 tja[1]=To+∆t[1] tja[2] = tja[1]+To+∆t[2]
∆t[1] ∆t[2]Time Error
Distribution
Figure B.2: Accumulating jitter.
The 1/f2 phase noise region is related to the accumulating jitter [38, 63]. Theaccumulating jitter happens in autonomous systems such as oscillators. From itsname it can be seen that the effect is accumulating along time so the currenttimestamp tja[i] is based on the previous one tja[i − 1] as demonstrated in FigureB.2:
tja[i] = tja[i− 1] + To +∆t[i] = i · To +
j=i∑
j=1
∆t[j] (B.4)
The 1/f2 phase error can also be expressed in terms of the accumulating jitterja as
ϕ(t) = 2πja(t)
To(B.5)
where
ja(i) =
j=i∑
j=1
∆t[j] (B.6)
82
The value of the accumulating jitter ja(t) is the integration of synchronous jitters∆t[i] i.e. like the case of random walk.
Assume that the synchronous jitters ∆t[i] is a white Gaussian stationary or T-cyclo-stationary noise process (this excludes flicker noise). Then its single-sidedpower spectral density (PSD) is
Sjs(f) = 2 · c (B.7)
where c is constant in the frequency of interest.Phase noise is the PSD of phase error (B.5). With (B.6) and (B.7), the 1/f2
phase noise equals
L(f) = 1
2(2πfo)
2Sja(f)
=1
2(2πfo)
2 1
(2πf)2Sjs(f) = c · f
2o
f2.
(B.8)
where Sja(f) is the PSD of the accumulating jitter (B.6).
83
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