M.S.Ramaiah School of Advanced Studies, Bangalore 1 Name : Rama Krishna P. Reg No : CGB0911012 Course : M.Sc. [Engg.] in VLSI System Design Module : Integrated Circuit Analysis and Design Module Leader : Prof. Cyril Prasanna Raj P. LOW POWER TECHNIQUES IN NANOMETER TECHNOLOGY
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M.S.Ramaiah School of Advanced Studies, Bangalore 1
Name : Rama Krishna P.Reg No : CGB0911012Course : M.Sc. [Engg.] in VLSI System DesignModule : Integrated Circuit Analysis and DesignModule Leader : Prof. Cyril Prasanna Raj P.
LOW POWER TECHNIQUES IN NANOMETER TECHNOLOGY
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Discussion
Why low power?
Types of power consumption
• Dynamic power
• Static power
Low power techniques
• Clock gating
• Multi vdd
• Multiple vth
• Power gating
Trade off
Future scope
Conclusion
References
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Why low power...?
Desirability of portable devices.
Advent of hand held battery operated devices.
Large power dissipation requires larger heat sinks hence increased area.
Cost of providing power has resulted in significant interest in power reduction
of non portable devices.
Lowering transistor threshold voltage.
Pavg=Pswitching+Pshort-circuit + Pleakage
=α0 1CL Vdd2 fclk + Vdd Isc +Ileakage Vdd
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Types of Power Consumption
Dynamic power
During the switching of transistors
Depends on the clock frequency and switching activity
Consists of switching power and internal power.
Static Power
Transistor leakage current that flows whenever power is applied to the device
Independent of the clock frequency or switching activity.
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PMOS
NMOS
VoutCdrain+
Cinterconnect+Cinput
Vdd
A
BCload
Dynamic power( Pswitching =CL Vdd
2 fclk )
capacitance
1) Output node capacitance of the logic gate: due to the drain
diffusion region.
2) Total interconnects capacitance: has higher effect as technology
node shrinks.
3) Input node capacitance of the driven gate: due to the gate
oxide capacitance.
Input voltage
Internal node voltage swing can be only Vi which can be smaller than
the full voltage swing of Vdd leading to the partial voltage swing.
Frequency
F increases then power automatically increases.
Fig 1:cmos inverter
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(Pshort-circuit =Vdd Isc )
To get equal rise/fall balance transistor sizing
2.5V
2.5V
0V
Vin
Vout
Vthn
Vdd- |Vthp|
More rise/fall time more short circuitLower threshold voltage more short
circuit
Vthn<Vin<Vdd-|Vthp|
NMOScurve
PMOScurve
Vdd<Vthn+|Vthp|
Both PMOS and NMOS are conducting
for a short duration of time
short between supply power and ground
Fig 2:shorte circuit Fig 3:Trance analysis of cmos
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Static power(Pleakage =Ileakage Vdd)
1). Diode reverse bias–I1 2). Sub threshold current – I2