Low Power Processor --- For Mobile Devices Ziwei Zheng Wenjia Ouyang.

Low Power Processor--- For Mobile Devices

Ziwei ZhengWenjia Ouyang

Agenda• Introduction

• Roadmap

• The trend during past years

• The recent technologies

• Future

User Experience Perspective For Low Power Mobile Devices:

• Active time of the deviceo Time interval of performing a well defined set

of tasks (defined use mode: audio play , voice call, web browsing, video playback, etc ) between two battery charges

• Standby time of the deviceo Time interval between two battery charges

when the device is fully functional ready to be activated, but does not perform any user driven tasks.

What kind of processors are available for mobile devices?

• Qualcomm Snapdragono Nokia Lumia 635

• Samsung Exynos o Samsung Galaxy S4

• MediaTek o Lenovo

• NVIDIA's Tegra• Intel• Cortex

• Reference:Bohr, Mark, and Kaizad Mistry. "Intel’s revolutionary 22 nm transistor technology." Rob Willoner at Innovation (2011).

Roadmap--Intel

Reference:Bohr, Mark, and Kaizad Mistry. "Intel’s revolutionary 22 nm transistor technology." Rob Willoner at Innovation (2011).

Roadmap--ARM

Reference: ARM Roadmap MWC 2013

http://forwardthinking.pcmag.com/none/310089-mobile-chip-makers-the-basic-building-blocks

Power Consumption in Digital Systems

• Ptotal=Pactive+Pleakage

• Pactive = Pinternal + Pswitching = Pinternal + αCV2f • V – voltage

f – frequencyC – capacitive load

• α – activity factor

• Pleakage= static power

• Pleakage ———— Intel: High-K & Tri-Gate

• Pactive ———— Symmetric multiprocessing

• Pactive ———— Nvidia vSMP• Pactive ———— Qualcomm aSMP

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Intel: High-K Metal Gate• Intel introduced a High-K Metal Gate technology in 2007 for 45nm

transistors, to create transistor gate of lower leakage current.

o Further reduction in the thickness of the layer o Silicon dioxide was replaced with a thin layer of material which

has a high level of dielectric k.

• High-K dielectric reduces leakage substantially.

o less unwanted current flowo easier manufacturing process

Reference: Kamata, Yoshiki. "High-k/Ge MOSFETs for future nanoelectronics." Materials today 11.1 (2008): 30-38.

Intel: Tri-gate Technology• Recently Intel announced production of a new transistor

technology called “3D Tri-Gate” that incorporated a three dimensional structure.

• 3D Tri-Gate transistors enable chips to operate at lower voltage with lower leakage.

• Driven by the need for higher on-off speeds and reduced power consumption, planar transistor size had been reduced to nanometer.

• Growing leakage currents from gate to channel.

• Form conducting channels on three sides of a vertical fin structure.

• The gate wraps around source and drain “fins” that protrude upward.

• Multiple fins connected together to increase total drive strength for higher performance

• Increased surface area between gate and the inversion layer significantly improve gate control.

Current-Voltage Characteristics

• Tri-Gate transistors provide a steeper sub-threshold slope that reduces leakage current

• Reference:Bohr, Mark, and Kaizad Mistry. "Intel’s revolutionary 22 nm transistor technology." Rob Willoner at Innovation (2011).

• Pleakage ———— Intel: High-K & Tri-Gate• Pactive ———— Symmetric

multiprocessing• Pactive ———— Nvidia vSMP• Pactive ———— Qualcomm aSMP

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Symmetric multiprocessing (SMP)• Symmetric multiprocessor system hardware and

software architecture where two or more identical processors connect to a single, shared main memory.

• Each processor ave full access to all I/O devices, and are controlled by a single operating system instance that treats all processors equally, reserving none for special purposes.

• Most multiprocessor systems today use an SMP architecture.

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Symmetric multiprocessing (SMP) • SMP systems shared Main Memory, usually each

processor has an associated private cache to speed-up the MM data access and to reduce the system bus traffic.

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• Pleakage ———— Intel: High-K & Tri-Gate• Pactive ———— Symmetric

multiprocessing• Pactive ———— Nvidia vSMP• Pactive ———— Qualcomm aSMP

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Nvidia Tegra 3

• Variable Symmetric Multiprocessing



Tegra 3: “companion” core

The companion core is manufactured with a special low power silicon process, that uses less power at low clock rate but does not scale well to high clock rates.

The goal is for a mobile phone or tablet to be able to power down all the normal cores and run on only the companion core, using comparatively little power, during standby mode.

Active Standby mode• "Companion" core, which will handle low

frequency tasks in the background.• Each of the five, count them, five, not four, five

cores are identical ARM Cortex A9 CPUs, each of them enabled and disables via aggressive power gating based on work load. (aka when they're needed, they're fired up.)

• First four cores are not aware of the fifth, but automatically take advantage of it - this saving both software efforts and new coding requirements as it flows.

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Optimized For Key Mobile Use Cases

• 80% of time in active standby state• 20% of time in intensive mobile application• Think about your device sitting in your pocket as

“Active Standby”.• Processor is either running background tasks or

low performance applications that do not require user interactions.

• Example: receive notification, send information to server.

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Power Consumption• Why combine fast process technologies and low

power process technologies?• Transistors on fast process technologies• consume high leakage power• very fast switching times• normal voltage levels

• Transistors on low power process technologies• low leakage power• slower switching times• low voltage levels

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Power Consumption

• Reference: nvidia white paper Variable SMP – A Multi-Core CPU Architecture for Low Power and High Performance 24

Power Advantage• 4 + 1 Cores• Low Power Companion Core

• Reference: nvidia white paper Variable SMP – A Multi-Core CPU Architecture for Low Power and High Performance

Summary• Variable Symmetric Multiprocessing(vSMP) not

only minimized active standby state power consumption, but also delivers on-demand maximum four core performance.

• In addition to four main high-performance CPU cores, nvidia has a fifth low power, low leakage CPU core called ‘Companion’ CPU core that is optimized to minimize active standby state power consumption, and handle less demanding processing tasks.

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• Pleakage ———— Intel High-K Metal Gate• Pactive ———— Symmetric

multiprocessing• Pactive ———— Nvidia vSMP• Pactive ———— Qualcomm aSMP

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Qualcomm Snapdragon 800

• asynchronous SMP (aSMP) design.

• Unlike synchronous SMP designs where all cores must run at the same frequency and voltage when operational, the asynchronous SMP power design provides independent clocking and voltage per core, allowing each to work independently.

Asynchronous SMP (aSMP)

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Asynchronous SMP (aSMP)

• Provides Highly efficient design this substantial power savings by intelligently adjusting Technology over Traditional SMP performance to suit the needs of the Application.

• Asynchronous SMP is a sort of dynamic power sensing chip architecture that automatically applies different voltages to each of the four cores depending require computing loads and this control peak performance per core. When a core performs a less important and low computing load requirement jobs, it inputs low voltages to make the best use of power budget.

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vSMP vs aSMP• vSMP has more cores meaning extra area.

• vSMP requires more software customize meaning limited market.

• aSMP may consume same power as vSMP as long as has aSMP has better design.

• Qualcomm has other saving power technology.

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Future Trend: The Next Step

• Smaller transistor size

• Multi-core: o Quad-core to Oct-core and Hex-core

Let’s Look Out to Decades• 3D chip stacking technology:o keeping a signal on-chip can reduce its

power consumption. o Shorter wires reduce power consumption

by producing less parasitic capacitance.

Questions?

Thanks