ISSN 2322-0929 Vol.03, Issue.06, August-2015, Pages:0785-0790 www.ijvdcs.org Copyright @ 2015 IJVDCS. All rights reserved. Low Power Area Efficient ROM Embedded SRAM Cache M. SWATHI 1 , D. NAGESHWAR RAO 2 , D. SUDHAKAR 3 1 PG Scholar, Dept of ECE, TKR College of Engineering & Technology, TS, India, E-mail: [email protected]. 2 Professor & HOD, Dept of ECE, TKR College of Engineering & Technology, TS, India. 3 Associate Professor, Dept of ECE, TKR College of Engineering & Technology, TS, India. Abstract: In a VLSI design contains area, power, speed, system performance all these are the features along with there are many important applications, such as math function evaluation, digital signal processing, and built in self-test, whose implementations can be faster and simpler if it have large on-chip tables stored as read-only memories (ROMs). But on-chip ROM’S are limited in size in order t i increase ROM’S memory size, the conventional de fact standard 6T and 8T static random access memory (SRAM) bit cell can embed ROM data without area overhead or performance degradation on the bit cells. Just by adding an extra word line (WL) and connecting the WL to selected access transistor of the bit cell (based on whether a 0 or 1 is to be stored as ROM data in that location). The bit cell can work both in the SRAM mode and in the ROM mode. In standard 6T&8T SRAM having mainly a drawback i.e data lost whenever power not present, to overcome these problems & increase performance we deal with ROM-embedded SRAM cache. In the proposed ROM-embedded SRAM (R-SRAM), during SRAM operations, ROM data is not available. To retrieve the ROM data, special write steps associated with proper via connections load ROM data into the SRAM array. The ROM data is read by conventional load instructions with unique virtual address space assigned to the data. It allows the ROM-embedded cache (R-cache) to bypass tag arrays and translation look-aside buffers, leading to fast ROM operations. Here example applications to illustrate how the R-cache can lead to low-cost logic testing and faster evaluation of mathematical functions. Keywords: Cache Design, Random Access Memory (RAM), Read-Only Memory (ROM), ROM-Embedded Static RAM (SRAM), SRAM Design. I. INTRODUCTION CMOS devices have been scaled down for about 40 years to achieve better performance, higher speed, Area reduction and Low power consumption. Due to high speed and low power and area efficient SRAM based memories are used compared to DRAM cells. Although technology scaling has led to integration of large number of transistors into a chip, large on-chip read only memory (ROM) is not suitable choice for designer. Most of the designers choose a suitable size of on chip Read Only Memories (ROM). Large dedicated ROM‟s increase Area, Cost and Power, but also impair chip floor plan and results interconnect delay. Let us consider a few examples where on-chip ROMs can be effectively used as “accelerators.” Coefficients for fast Fourier transform library are stored in external nonvolatile memory instead of on-chip ROMs. Coefficients for fast Fourier transform library are stored in external nonvolatile memory instead of on-chip ROMs. Note that on-chip ROMs can significantly improve the performance of such applications. The interweaver for Turbo codes is designed by a dedicated logic to generate addresses on the fly, instead of dedicated on-chip ROMs. Pseudo-random-pattern generators (PRPGs) produce test data to avoid storing test data in on-chip ROMs for built-in self- test (BIST). Note that on-chip ROMs can significantly improve the performance of such applications. For evaluation of math functions, math libraries are used. Such libraries are usually stored off-chip, leading to degradation in performance. The speed gap between a processor and an external memory grows with every technology generation, resulting in major roadblocks to high-performance system design. In this paper, we organized as follows. Section 2 deals with existing method i.e. 6 Transistor SRAM cell design. 6 Transistor SRAM cell Write operation and Read operation. Section 3 describes the proposed ROM Embedded SRAM cell operation, i.e. SRAM mode operation and ROM mode operation based on word line connection. Section 4 describes 8 Transistor RSARM cell how to storing “0” and “1”. Section 5 describes Simulation results of 6 Transistor SRAM cell and 6 Transistor RSRAM cell. Section 6 describes the Conclusion of the project. II. EXSISTING METHOD A. Conventional 6t SRAM Cell The most commonly used SRAM type is the 6T SRAM which offers better electrical performances from all aspects (speed, noise immunity, standby current). The smallest 6T SRAM cell that has been fabricated till today has an area of 0.08μm2 and it was fabricated in the 22nm process using immersion and EUV lithography. Conventional SRAM cell is implements with six transistors. In these SRAM cell two
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ISSN 2322-0929
Vol.03, Issue.06,
August-2015,
Pages:0785-0790
www.ijvdcs.org
Copyright @ 2015 IJVDCS. All rights reserved.
Low Power Area Efficient ROM Embedded SRAM Cache M. SWATHI
1, D. NAGESHWAR RAO
2, D. SUDHAKAR
3
1PG Scholar, Dept of ECE, TKR College of Engineering & Technology, TS, India, E-mail: [email protected].
2Professor & HOD, Dept of ECE, TKR College of Engineering & Technology, TS, India.
3Associate Professor, Dept of ECE, TKR College of Engineering & Technology, TS, India.
Abstract: In a VLSI design contains area, power, speed, system performance all these are the features along with there are many
important applications, such as math function evaluation, digital signal processing, and built in self-test, whose implementations
can be faster and simpler if it have large on-chip tables stored as read-only memories (ROMs). But on-chip ROM’S are limited
in size in order ti increase ROM’S memory size, the conventional de fact standard 6T and 8T static random access memory
(SRAM) bit cell can embed ROM data without area overhead or performance degradation on the bit cells. Just by adding an
extra word line (WL) and connecting the WL to selected access transistor of the bit cell (based on whether a 0 or 1 is to be stored
as ROM data in that location). The bit cell can work both in the SRAM mode and in the ROM mode. In standard 6T&8T SRAM
having mainly a drawback i.e data lost whenever power not present, to overcome these problems & increase performance we
deal with ROM-embedded SRAM cache. In the proposed ROM-embedded SRAM (R-SRAM), during SRAM operations, ROM
data is not available. To retrieve the ROM data, special write steps associated with proper via connections load ROM data into
the SRAM array. The ROM data is read by conventional load instructions with unique virtual address space assigned to the data.
It allows the ROM-embedded cache (R-cache) to bypass tag arrays and translation look-aside buffers, leading to fast ROM
operations. Here example applications to illustrate how the R-cache can lead to low-cost logic testing and faster evaluation of